Open access peer-reviewed chapter

Main Differences in Processing Si and SiC Devices

Written By

Fan Li and Mike Jennings

Submitted: 30 November 2017 Reviewed: 07 March 2018 Published: 12 September 2018

DOI: 10.5772/intechopen.76293

From the Edited Volume

Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Edited by Yogesh Kumar Sharma

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Due to the different physical properties of Si and SiC, many conventional Si device processing techniques cannot be directly transferred to SiC device fabrication. To deliver high-performance SiC commercial power devices, new techniques quite different from Si industry were developed in past decades for processing device, such as dopant implantation, metal contact, MOS interface, etc. On the other hand, the physics model behind many of these SiC processing technologies is not updated in the same pace that the success of them can still not be fully understood.


  • SiC processing
  • dopant implantation
  • metal contact
  • MOS interface
  • physics model

1. Introduction

Silicon has dominated the electronics industry ever since it was born. In power electronics area, nearly all commercial power devices are made of Si nowadays. However, due to the target of a more environmental friendly society, there has been a continuously increasing demand of power devices working in more harsh conditions such as higher power, higher temperature, higher frequency or even higher radiation, some of which are well beyond the physical limits of Si. For the first time, the position of Si is challenged by some other materials, most of which have a larger band gap than Si, thus called wide band gap (WBG) semiconductors, including silicon carbide (SiC), gallium nitride (GaN) and diamond. SiC may be the most promising candidate at the moment, whose technology is most mature among WBG semiconductors with commercial devices readily on the market [1, 2], and most importantly, SiC is the only WBG semiconductor with SiO2 as the nature oxide, which is used extensively in power devices as insulators, dielectrics and diffusion barriers [3]. Just as the SiC substrate and epilayer growth technologies which had gone through decades of developments before power device quality level wafers can be delivered, SiC device processing techniques were improved as well at the same time. It has been studied intensively in last 20 years, and although there is still plenty of room to be improved, commercial power MOSFETs and Schottky diodes with some more conventional structures are not an issue anymore. This chapter will talk about the state-of-the-art processing techniques for SiC devices, including intentional doping, electrical activation, metal/semiconductor interfaces and MOS interface. Particularity, the difference between Si and SiC processing in these areas will be discussed.


2. Intentional doping in SiC

In 1930, Bernhard Gudden [4] was the first one to report that the electrical carriers of semiconductors are actually the impurities within their crystal lattices. If the impurity concentration is too high, the semiconductor becomes metallic, and if too low, more like an insulator.

2.1. Thermal diffusion and ion implantation

Impurities are usually introduced to the bulk semiconductor in early stages of a device fabrication process. Most commonly used dopants are from group V (N, P and As) for n-type and group III (B, Al and Ga) for p-type doping purposes. Doping a bulk semiconductor can be relative easily achieved by adding dopant elements into the epilayer growing process, and the impurity level can be modulated by controlling the precursor gas concentrations [5]. Take a typical vertical MOSFET structure as an example; on the epilayer surface, specific n-type and p-type regions are required to form ohmic contact, MOS channel and body diode. The selective doping area is usually defined by doping masks made of dielectrics or metals using standard photolithography processes. Nowadays the selective doping of semiconductor is achieved mostly in two ways, namely, thermal diffusion and ion implantation.

It is well known that molecules tend to move from higher to lower concentration regions, and this process can be enhanced by increasing the ambient temperature, pressure or concentration gradient in-between. This idea is adopted in semiconductor industry to introduce impurities using dopant sources with various phases: gas, liquid or solid. Thermal diffusion-based doping process often occurs in a quarts tube (see Figure 1) in an inert gas atmosphere to minimise contaminations. The dopants firstly arrived at the semiconductor surface form a relative high impurity concentration region; consequently, a concentration gradient exists between the surface and bulk, after which the diffusion is initiated by the thermal energy provided. With time going on, dopants diffuse deeper into the semiconductor bulk, and when the desired doping profile is obtained, it can be stopped quite conveniently by simply cutting the heat supply.

Figure 1.

Schematic graph showing a typical dopant thermal diffusion process using a gas source.

Attributed to the developments of experimental physics, ion implanting dopants directly into semiconductors are also an option now. Ion implanters were not widely available to device engineers until the 1970s [6], while now it is commonly used in both lab and industry processing. In an ion implantation system, dopants are ionised atoms generated from an ion source shown in Figure 2. Being ionised, the dopant atoms can be accelerated by electromagnetic field to gain energy so high that, when hitting the target surface, they are able to break the semiconductor chemical bonds and penetrate into the crystal lattices. The implantation depth can be controlled by changing the electromagnetic field strength, and the resultant impurity concentration (cm−3) is determined by the amount of dopants supplied by the source, which is called ‘dose’, and the unit is number per specific area (cm−2).

Figure 2.

The schematic diagram of an ion implantation system [7].

In Si device processing, both thermal diffusion and ion implantation can be used depending on specific requirements. In fact, implantation followed by a short time thermal diffusion is becoming popular nowadays. For WBG semiconductors such as SiC, however, diffusion coefficients of common dopants are so low that are negligible below 1800°C [8], which leaves ion implantation the only option, and the PIA process is essential.

Even being a more complex and expensive system, ion implantation proved to be more controllable than thermal diffusion. Also, the movement of dopants in a thermal diffusion process may involve unexpected spreading in other directions, leading to poor doping profiles. This is not an issue for ion implantation since dopant movement in the semiconductor is minimal, which means the elimination of dopant out-diffusion. There are, of course, also limitations for ion implantations. First of all, it is essentially a dopant bombarding process, which means damages are inevitably induced to the target, mainly in the surface region. Secondly, as-implanted dopants are almost always interstitial (not chemically bonded), namely, not active carriers. An extra post-implantation annealing (PIA) process is typically required to recover the lattice damage and put the implanted dopants into substitutional positions so they can contribute to current conduction, called dopant activation.

2.2. Activating implanted dopants in SiC

The activation of dopants in 4H-SiC has been intensively studied, and the efforts are mainly put into two directions, namely, protecting the semiconductor surface morphology while at the same time maximising the active concentration of implanted dopants.

The temperature required for SiC post-implantation activation (PIA) is very high that above 1400°C [9, 10] is common for n-type and even higher (>1600°C) for p-type [11, 12, 13] since acceptors generally sit deeper in the band gap than donors, namely, more difficult to activate. This high temperature means conventional quartz tubes are not up to the task and high melting point tubes made of Al2O3 and SiC or similar have to be used. Also, high-temperature annealing leads to a roughened semiconductor surface (known as ‘step bunching’), enhanced at implanted regions. This can deteriorate the performance of interface features such as Schottky contacts and FET channels [14, 15, 16]. A protection capping layer is often used to preserve the SiC surface; such cap materials studied for 4H-SiC include AlN [17, 18], BN/AlN [19] and graphite [12, 15]. AlN and BN/AlN processes are found complex and expensive, thus not widely accepted. The graphite cap proved to be effective in preserving surface morphology up to 1800°C [11] but may reduce the MOSFET channel mobility due to the excessive silicon vacancies, which are most likely induced by the reaction between diffused Si atoms and the graphite [11, 20]. A SiO2 layer should not react with Si or C at the common annealing temperatures and can be easily deposited by CVD method and removed via HF etching. It was also studied and resulted a similar surface roughness level as a graphite cap with the same annealing conditions [21]. In the few literatures on 3C-SiC, n-type implanted 3C-SiC was studied for different annealing conditions (1150–1400°C) with [22] and without [23, 24] a graphite cap, and it turned out that there was little advantage of using a graphite cap in terms of protecting the 3C-SiC surface, probably because the temperature limited by Si substrates is not high enough to make the difference.

For a given implanted doping level, the active dopant concentration in SiC generally increases with the PIA temperature. And for a fixed PIA temperature, the active dopant concentration increases with the implanted doping level [25], although the percentage of activated dopants (activation rate) seems to decrease [9]. Complete activation of N-type implanted 4H-SiC has been demonstrated by annealing at 1700°C and using phosphorous as dopant [26], while P-type material still remains a challenge [12].


3. Ohmic contact on SiC

Most metals are known as highly electrical and thermal conductive attributed to their delocalised electrons, not to mention the convenient alloying process which helps to form reliable interactions for packaging. Consequently, they are the most widely used material for contact materials in semiconductor industry. Dating back to Braun’s discovery in 1874 [27], the study of metal/semiconductor (M-S) interface is almost as old as the semiconductor device itself. A lot of huge efforts were put into exploring the M-S interface, and there had been classic physics models that were well developed. Yet still, this area remains active with new discoveries reported, and novel theories developed continuously. The emergence and adoption of WBG semiconductors raise discussions on new experimental results, and the well-established theories are challenged.

3.1. Metal contact interface: classic theory

It can be seen in Figure 3 that the work functions of most metals used in electronic industry are quite big compared with Si affinity, that is, an inherent energy barrier exists between metal/Si interfaces, preventing free carrier exchange. And due to a much lower affinity value (except for 3C-SiC), this barrier is only getting higher at a metal/SiC interface, which also explains why Schottky behaviour is typically observed for as-deposited metal contacts on 4H-SiC. To fabricate an ohmic contact, increasing the contact region local doping level (via thermal diffusion or ion implantation) is the most common way for both Si and SiC. When the contact region is lowly doped, the depletion region is quite wide that the electron exchange at the M-S interface is only possible when electrons overcome the barrier by gaining enough energy as shown in Figure 4, usually thermally activated and thus called thermionic emission (TE). If doping level is very high, the depletion region becomes quite narrow, and electrons can tunnel through the barrier freely with the help of an external electric field, which is called field emission (FE). And if the doping value is in the middle, the depletion region is narrowed but not enough to enable electron tunnelling. In this case, electrons still need extra thermal energy to ‘climb up’ the barrier, but not as much as TE. The energy required just needs to be adequate for the electrons to ‘climb’ to a position shallow enough for tunnelling that begins to take effect. Since both TE and FE mechanisms are involved, this is therefore called as thermionic/field emission (TFE).

Figure 3.

Band diagrams of Si, 3C-, 4H- and 6H-SiC and work functions of commonly used metals in electronic industry [28, 29].

Figure 4.

Metal-semiconductor (n-type) interface carrier conduction mechanisms for different doping levels.

Among all, FE is the most desired conduction mechanism for deletion-type ohmic contact fabrication, since it is not a thermally activated process, namely, the electrical performance is relative temperature insensitive, which is attractive in more reliable device operation point of view. In real cases, both TFE and FE conduction are quite common. To predict the potential conduction mechanism at the SiC ohmic contact interface, the characteristic energy E00 of 3C-, 4H- and 6H-SiC as well as Si is calculated [30] for doping values from 1 × 1016 to 1 × 1020 cm−3and plotted in Figure 5. Dielectric constants and electron conductivity effective mass are shown in Table 1. The specific boundaries between three mechanisms may vary a bit between groups; the one used in Figure 5 is proposed by Schroder [31]. As can be seen, to enable FE tunnelling, a doping level above 1 × 1020 cm−3 is required for all semiconductors studied here.

Figure 5.

Characteristic energy E00 as a function of doping density for n-type Si, 3C-, 4H- and 6H-SiC.

Semiconductor Dielectric constant Electron conductivity effective mass
Si 11.7 0.26
3C-SiC 9.72 0.32
4H-SiC 9.66 0.36
6H-SiC 9.66 0.57

Table 1.

Dielectric constants and electron conductivity effective mass of Si, 3C-, 4H- and 6H-SiC [32].

Until now, the contact local doping level has been considered as a constant, which cannot be true for WBG materials. This is because with a wider band gap, dopants naturally sit in deeper energy levels and may not be thermally ionised at room temperature; it is called ‘freeze-out’ [33]. The partial ionisation of carriers leads to quite different ohmic contact performances from conventional theories. Field emission, for example, in which case the contact resistance used to be temperature independent, now will drop with elevating temperature. This is because with more dopants ionised, the contact local doping increases; thus, the depletion width is reduced [34], in favour of the field emission conduction. On the other hand, partial ionisation also means it is more difficult to achieve lower contact resistance at room temperature. To compensate this, after metal deposition on even very highly doped SiC films, extra annealing step (1000–1200°C) is usually required to form a homogeneous silicide or carbide layer at the contact interface, which further lowers the Schottky barrier height, leading to a lower contact resistance. For N-type ohmic contact, nickel-based alloys are typically used, and resultant silicides are Ni2Si [35], while for P-type, Ti/Al alloys are common, leading to the formation of TiC or Ti3SiC2 [36] at the interface after the contact anneal. The complete story behind the rapid thermal anneal for SiC ohmic contact is still not clear; apart from the silicide reaction, which had been consistently observed and confirmed, local carbon clusters [37, 38] enriched at close to the contact interface, potentially providing more free carriers, were also often discussed and may have played a part, too. Specific contact resistance as low as 1 × 10−6 Ω cm2[9, 39] can be obtained on N-type SiC ohmic contact, and for the more difficult P-type due to deeper acceptor level, a higher value around 1 × 10−4 Ω cm2 is typical [12, 36, 40].


4. SiC/SiO2 MOS interface

Early MOSFETs have a long channel, leading to excessive on-state resistance which is not appropriate for power electronics, thus only applied in low power levels such as microprocessors, microcontrollers and logic circuits. On the other hand, the voltage-control and fast-switching features of MOSFETs are very attractive for power switch applications; consequently many efforts had been put into making power MOSFETs. The first high-voltage structure was developed in the 1970s and called V-MOSFET [41], named after the V-shape grove channel as seen in Figure 6a. This design never got popular due to the difficulty in fabricating a smooth V-shape trench on Si substrates, which was at that time formed by potassium hydroxide-based etching, whereas etching rate varies in different crystal orientations [42]. Also, the pointy trench bottom causes severe electric field crowding and easily leads to device early breakdown. Not long after, a planar structure shown in Figure 6b was invented. Instead of a V-shape grove, the channel was defined by controlling the thermal diffusion of dopants in the P-base and N+ source regions, thus called vertical-diffused (VD) MOSFET. With main features relatively easy to fabricate and quite reliable, VD-MOSFET is the most successful design up to date. To achieve higher forward current density, the cell pitch of VD-MOSFET is usually made as small as possible. However, the narrow JFET region between two P-bases restricts the current flowing between channels and drift region, inducing extra on-resistance [43]. In the late 1980s, U-MOSFET design (Figure 6c) was proposed as a potential solution of getting rid of the JFET region. U-MOSFET is similar to the V-groove design in the sense that both of them use a trench to eliminate the JFET region, reducing the device on-resistance. By the time U-MOSFET was proposed, Si etching technology had been greatly improved that rounded trench corners are possible with reactive ion etching or other techniques [44]. However, the trench MOS interface and oxide reliability issues are not fully solved; consequently, U-MOSFETs still cannot compete with their planar counterparts.

Figure 6.

Schematic structure views of various MOSFET designs.

All three power MOSFET designs introduced above have a vertical structure to maximise current handling ability of discrete devices. For vertical devices, the current rating can be increased by simply enlarging the device active area, such as bigger contacts for diodes or more parallel cells for MOSFETs. In some applications where power devices and control and logic circuits are integrated (e.g. smart power devices, power ICs), the processing and packaging may require all electrodes on the same side of the device, which makes a lateral design necessary, and this is where lateral diffused (LD) MOSFET fits in. As a modification from the long channel design, LDMOSFET usually has a much shorter channel length to minimise the on-resistance. Meanwhile, a long drift region is included for high-voltage purpose as seen in Figure 6d. Unlike vertical designs whose breakdown voltage is constrained by the drift region (epilayer) thickness, LDMOSFET utilises the semiconductor surface to greatly increase the device blocking voltage. Inevitably, the current conducting ability of LDMOSFET has to be greatly compromised. As a result, LDMOSFETs are mostly used for RF power amplifiers, microwave and medium power switching applications.

The adoption of WBG semiconductors enables MOSFETs to be used in power electronics applications with much higher power levels. While the Si/SiO2 interface has been intensively studied and the technology being very mature, the SiC/SiO2 interface is still an active topic, revealing all kinds of possibilities and challenges.

4.1. Degradation of MOS channel mobility

Apart from phonon and coulombic which also troubles the bulk region, for channel region there is an extra surface roughness scattering mechanism. Among all, the Coulombic scattering caused by extra charges at the MOS interface is more process dependent and has been the target of studies. In real life, gate oxides are often with defects acting as carriers’ leakage paths and cause early breakdown. By trapping and discharging carriers during the MOS device operation, these defects (also called states) are the main reason behind the severe Coulombic scattering. Extra charges found in most MOS systems are categorised into four groups, namely, mobile charges, fixed charges, oxide-trapped charges and interface charges. A schematic graph indicating the general location and polarity of various charges are shown in Figure 7.

Figure 7.

Common oxide charges at MOS interface with locations and charge polarity indicated.

Mobile charges are metal ionic impurities (such as Na+) introduced during the device fabrication process and can move freely in the oxide with a gate bias. Since positively charged, they will attract semiconductor electrons to the surface and induce extra band bending, leading to a shift of flat band voltage. Mobile charges are highly uncontrollable and thus must be minimised through clean and careful fabrication process. In contrast to mobile charges, fixed charges refer to those who do not move with gate biases. The origin of fixed charges is believed to be the excessive ions left near the interface after the oxidation process termination [45]. They are usually located in the oxide and close to the MOS interface as shown in Figure 7. Fixed charges can be both positive and negative, and the total amount depends heavily on the oxidation condition. Since fixed charges stay close to the interface, they also affect the semiconductor band bending. As a result, a shift of flat band voltage from the theoretical value is again observed.

Interface charges, as the name suggests, sit at the MOS interface. Energy levels of these traps are in the semiconductor band gap; consequently, they can act as carrier traps communicating (charge/discharge) with the bulk semiconductor during device operation. And since these traps are right at the MOS interface, they scatter the channel carriers much more than other charges. The origins of interface traps vary among different MOS systems. For Si/SiO2 interface, most of the interface traps come from unterminated Si dangling bonds. H2 annealing after the gate oxidation is typically applied to passivate the unterminated Si dangling bonds. Unlike the previous three, oxide-trapped charges are induced by the device operation rather than the fabrication process. The oxide layer, thermally grown or deposited, contains intrinsic defects such as oxygen vacancies [46]. Although these defects are electrically neutral, during the device operation, carriers may be injected into them and make them negatively or positively charged. Depending on the energy level, they may or may not be able to communicate with the semiconductor carriers. For those very close to the MOS interface that are able to be charged and discharged during device operation, they effectively behave as interface traps, otherwise similar to fixed charges.

4.2. SiC/SiO2 interface traps

With all the superior electrical performance and the ability to be thermally oxidised, it is no surprise that there are a lot of interests in making SiC MOS devices. The most commercialised 4H-SiC is naturally mostly studied. The hexagonal lattice of 4H-SiC means there will be several faces available for oxidation. Most of the work has been devoted into the (0001) Si-face, the only one available in commercial wafer form. Following discussions are therefore mainly based on (0001) Si-face. There have been studies suggesting that MOS interface traps for all SiC polytypes are similar [47]; thus, the study on the 4H-SiC/SiO2 interface also provides a great insight for other polytypes. Unfortunately, the 4H-SiC/SiO2 interface turns out to be quite poor, and the electrical performance is not even close to the Si case. The interface trap density (Dit) at an as-grown 4H-SiC/SiO2 interface is typically close to 1013 cm−2 eV−1, which is hundreds of times higher than the Si/SiO2 interface [48]. The channel mobility generally decreases with increasing Dit; thus, the latter is commonly used as an indicator for the MOS interface quality. With decades of study, reasons behind the poor 4H-SiC/SiO2 interface are still not fully understood. In [46], a discussion was made on the potential origins of interface traps, and two sources were identified, first of which is the carbon accumulated at the MOS interface during the SiC oxidation process. The reactions occurring during Si and SiC oxidation processes can be generally expressed by reactions described in Eqs. (1) and (2):

Si s + O 2 g SiO 2 s E1
SiC s + x O 2 g SiO 2 s + CO / CO 2 g E2

Depending on the oxygen pressure, there may be some intermediate reactions [49], but it can be seen that SiC oxidation is accompanied by the release of gaseous carbon, either CO or CO2. However, the increase of oxide thickness after the oxidation process goes for a while makes it more difficult for carbon to escape, and the reaction (Eq. (3)) may occur instead:

SiC s + O 2 g SiO 2 s + C s E3

The theory of carbon failing to escape through thicker oxide naturally leads to the idea that there should be less carbon at the MOS interface with thinner oxide. Indeed, a recent study [50] demonstrated an almost ideal SiC/SiO2 interface with a very thin oxide layer (≈14 nm); the Dit value was below 1011 cm−2 eV−1. However, as mentioned before a certain oxide thickness (≈50 nm for SiC MOS devices) is necessary for a reasonable threshold voltage, which means very thin oxide is not practical in real device fabrications. Thin thermally grown oxide with deposited oxide on top of it may be an option but still not easy, since deposited oxide is known to contain many more defects than thermally grown ones [51].

This leads to the second source of SiC/SiO2 interface traps, namely, oxide defects. Oxide defect-induced traps are essentially the oxide-trapped charges mentioned before. In SiC/SiO2 study they are also known as ‘near-interface traps’ since they do not actually sit at the interface but instead are located in the SiO2 very close to the interface. For Si, energy levels of oxide-trapped states are in the conduction band, thus not electrically active. For SiC, however, whose band gaps are 2–3 times wider, many of the oxide-trapped charges located in the band gap are being electrically active, as has been confirmed by photon-stimulated electron tunnelling [52]. The near-interface traps have time constants much smaller than the carbon clusters, which are also called fast traps while the latter known as slow traps. A schematic representation of the carbon cluster mode is illustrated in Figure 8 with energy levels of the traps specified. Due to the much lower mobility of holes than electrons, SiC MOS devices are almost exclusively based on n-channel design; naturally, the traps scattering the channel carriers most are the ones located close to the conduction band edge. Figure 8 shows that the 4H-SiC conduction band edge is mostly troubled by near-interface traps and π-bonded carbon clusters, with the former more dominant. Both of these traps are accepter-like, namely, negatively charged when being occupied, which can explain the quite positive threshold values often observed for 4H-SiC MOS devices. On the other hand, 3C-SiC is free from near-interface traps attributed to a smaller band gap but is still troubled by π-bonded carbon clusters. These carbon clusters near the 3C-SiC conduction band edge are donor-like, thus positively charged if unoccupied, which means the resultant threshold voltage may be more negative. Dangling bonds still contribute to some of the interface traps here but are only secondary concerns. Consequently, for SiC, H2 annealing is not as effective as it is for Si. Other techniques had to be explored for SiC/SiO2 interface optimisation.

Figure 8.

Schematic representation of the ‘carbon cluster model’ [53].

4.3. SiC/SiO2 interface treatments

The efforts put into improving the SiC/SiO2 interface can be grouped into three directions, namely, post-oxidation annealing (POA), channel counter-doping and high-temperature oxidation.

Nitridation may be the most widely used method to improve the 4H-SiC/SiO2 interfaces. It is usually achieved by annealing thermally grown gate oxides in nitrogenous trace gas environment (NO or N2O), called post-oxidation annealing (POA). It is believed that the N-O bond breaks at high temperature and supplies free oxygen which oxidises 4H-SiC [54]; consequently, nitridation by POA is accompanied by a further growth of the oxide, although not significantly. Gate oxide can also be directly grown in such atmosphere to obtain similar benefits. Previous X-ray photoelectron spectroscopy (XPS) results showed that after NO/N2O POA, there were fixed nitrogen atoms near the interface with a density ≈1 × 1014 cm−2 [55], even after removing all the oxide by a hard HF etching, indicating that nitrogen atoms were strongly bonded to 4H-SiC substrate. There had been evidence showing the nitridation reduced both carbon-related and near-interface traps [56], even though there is still no complete explanation of the theory established. The near-interface traps are probably reduced by the formation of an oxynitride layer between 4H-SiC and gate oxide, which redefines the oxide/semiconductor boundary [57], and the oxide-trapped charges are no longer near the interface. In terms of the carbon clusters, they are probably decomposed by inserted nitrogen atoms, which shift the energy levels of remaining clusters deeper into band gap, namely, further away from the conduction band edge and less effective in terms of scattering channel carriers [58]. Apart from N2O/NO, it was reported that annealing the gate oxide in a phosphorous trace atmosphere (POCl3 [59] or P2O5 [60]) also led to a channel mobility improvement, although it introduced severe threshold voltage instability as a result of SiO2 being converted into phosphor silicate glasses. Reducing the number of interface traps by introducing extra atoms into the interface is called passivation, and regardless of the source (N or P), it is always required that enough foreign atoms diffuse through the gate oxide and reach the interface. Certainly higher annealing temperature and time duration will help with that; however, due to the very low diffusion coefficient of nitrogen in SiC, nitrogen atoms saturate only within a monolayer deeper into the interface [61], and consequently the mobility value does not increase further, and the peak value typically stays around 40 cm2/V s [62]. Phosphorous has a higher saturation density than nitrogen in 4H-SiC, but still, the peak mobility value stays around 80 cm2/V s [63] regardless of further increased annealing time durations.

The limitation of thermal diffusion naturally leads to the idea of incorporating more passivating atoms into the interface by ion implantation, also known as channel counter-doping. 4H-SiC MOSFETs were fabricated on nitrogen-implanted substrates and higher peak channel mobility (≈60 cm2/V s) than unimplanted or even NO/N2O annealed samples was observed [64, 65, 66], before the mobility curve becomes significantly distorted for a dose level of 2.2 × 1014 cm−2. The success of counter-doping technique brings in another possible explanation [66] other than the defect passivation for the improved 4H-SiC/SiO2 interface. With the channel surface being partially compensated by the nitrogen implantation, a depletion region is formed between the thin counter-doped n-type surface and the underlying p-type channel region. The n-type counter-doped surface may be positively charged even without any gate bias due to the p-n junction depletion. In inversion mode, higher carrier mobility can be achieved since these positive charges will cancel part of the negative electric field built in the channel region, reducing the surface roughness scattering. Apart from nitrogen, other elements were also studied for the counter-doping. In [67], a variety of ions including B, N, F, Al, P and Cl were individually implanted into a 4H-SiC substrate, which was then oxidised to make MOS capacitors. It turned out only group V elements (N and P) led to a reduced Dit while the other increased it. A negative shift of flat band voltage is always observed for N or P counter-doped MOSFETs, a natural result of the channel being partially compensated. For devices fabricated with N- or P-based POAs, similar negative shifts were also observed, which suggests that counter-doping may have occurred in POAs through minor thermal diffusion, making it difficult to distinguish the effects from passivation and counter-doping. More recently [68], counter-doping 4H-SiC MOSFET channel using Sb was studied, and a peak field-effect mobility as high as 80 cm2/V s was obtained. The fact that the mobility value dropped to almost zero at 70 K (Sb freezes out) confirmed that the improvement is not achieved by defect passivation, since otherwise the mobility should only be influenced by SiC electrons and the Sb freeze-out will have minimal effect. Further processing the Sb counter-doped sample with NO POA led to an increased channel mobility in all temperatures including 70 K, which suggests that the counter-doping and defect passivation may be two independent mechanisms, yet both increase the channel mobility.

Both previous methods introduce extra foreign element atoms to the SiC/SiO2 system. It will be ideal to have an as-oxidised MOS interface free from excessive interface traps. High-temperature oxidation is considered as a possible solution. It was firstly reported in [69] that Dit decreases with increasing oxidation temperature, which was related to a reduction of SiCxOy near the interface at higher oxidation temperature. More recently [70], a channel mobility of 40 cm2/V s was reported for 4H-SiC MOSFET with gate oxide thermally grown at 1500°C without any further treatment, and the XPS measurement suggests a reduction of carbon near the interface. The mechanism behind high-temperature oxidation is still unclear and needs to be explored more.


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Written By

Fan Li and Mike Jennings

Submitted: 30 November 2017 Reviewed: 07 March 2018 Published: 12 September 2018