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Steven Voldman

Institute of Electrical and Electronics Engineers United States of America

Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for 'Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He received his B.S. in Engineering Science from University of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Engineering Physics (1986) and a Ph.D in electrical engineering (EE) (1991) from University of Vermont under IBM's Resident Study Fellow program. Voldman was a member of the semiconductor development of IBM, and consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC), and Samsung Electronics Corporation. In 2018, he was a International Visiting Scholar in Khon Kaen University (KKU) in Thailand. He is a recipient of 262 issued US patents and has written over 150+ technical papers in the area of ESD, EOS, and CMOS latchup in journals and conference proceedings. Dr. Voldman is an author of ten book series on ESD, EOS and latchup, and a new text titled From Invention and Patent as well as a co-authored text on Radiation effects on semiconductors. He is an author of many book chapters on semiconductor technology.

1books edited

3chapters authored

Latest work with IntechOpen by Steven Voldman

As we enter the nanoelectronics era, electrostatic discharge (ESD) phenomena is an important issue for everything from micro-electronics to nanostructures. This book provides insight into the operation and design of micro-gaps and nanogenerators with chapters on low capacitance ESD design in advanced technologies, electrical breakdown in micro-gaps, nanogenerators from ESD, and theoretical prediction and optimization of triboelectric nanogenerators. The information contained herein will prove useful for for engineers and scientists that have an interest in ESD physics and design.

Electrostatic Discharge

Electrostatic Discharge

Edited by Steven Voldman

Chapters authored

System and Component Failure from Electrical Overstress and Electrostatic Discharge

By Steven H. Voldman

Electrical overstress (EOS) and electrostatic discharge (ESD) have been an issue in devices, circuit and systems for electronics for many decades, as early as the 1970s, and continued to be an issue to today. In this chapter, the issue of EOS and ESD will be discussed. The sources of both EOS and ESD failure history will be discussed. EOS and ESD physical models, failure mechanisms, testing methods and solutions will be shown. The chapter will close with discussion on how to provide both EOS and ESD robust devices, circuits, and systems, design practices, and procedures, as well as EOS and ESD factory control programs. EOS sources also occur from design characteristics of devices, circuits, and systems.

Part of the book: System of System Failures

Electrostatic Discharge Protection and Latch-Up Design and Methodologies for ASIC Development

By Steven H. Voldman

Electrostatic discharge (ESD) has been an issue in devices, circuits, and systems for electronics for many decades, as early as the 1970s, and continued to be an issue until today. In this chapter, the issue of ESD protection design and methods for Application-Specific Integrated Circuits (ASICs) will be discussed. The chapter will discuss ESD design in an ASIC environment. The discussion will address ESD design layout, design rules and practices, and the method of integration of ESD protection into the ASIC design practice. Part of the methodology is the floor planning of an ASIC design, I/O library, integration of ESD into I/O cells, power distribution, and placement of power pads, in both array and peripheral design methodologies. As part of the ASIC I/O design, guard rings and latch-up interactions will be highlighted.

Part of the book: Digital Systems

Electrostatic Discharge, Electrical Overstress, and Latchup in VLSI Microelectronics

By Steven H. Voldman

Electrostatic discharge (ESD), electrical overstress (EOS), and latchup have been an issue in devices, circuit and systems for VLSI microelectronics for many decades and continue to be an issue till today. In this chapter, the issue of ESD, EOS and latchup will be discussed. This chapter will address some of the fundamental reasons decisions that are made for choice of circuits and layout. Many publications do not explain why certain choices are made, and we will address these in this chapter. Physical models, failure mechanisms and design solutions will be highlighted. The chapter will close with discussion on how to provide both EOS and ESD robust devices, circuits, and systems, design practices and procedures. EOS sources also occur from design characteristics of devices, circuits, and systems.

Part of the book: Emerging Micro

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Technical University of Ostrava , Czech Republic

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Jozef Zurek

Air Force Institute of Technology , United States of America

Ryszard Kaleta

Air Force Institute of Technology , United States of America

Datu Buyung Agusdinata

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