Open access peer-reviewed chapter

Optical Proximity Correction (OPC) Under Immersion Lithography

Written By

Ahmed Awad, Atsushi Takahashi and Chikaaki Kodaman

Submitted: 25 August 2017 Reviewed: 24 November 2017 Published: 24 December 2017

DOI: 10.5772/intechopen.72699

From the Edited Volume

Micro/Nanolithography - A Heuristic Aspect on the Enduring Technology

Edited by Jagannathan Thirumalai

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As advanced technology nodes continue scaling down into sub-16 nm regime, optical microlithography becomes more vulnerable to process variations. As a result, overall lithographic yield continuously degrades. Since next-generation lithography (NGL) is still not mature enough, the industry relies heavily on resolution enhancement techniques (RETs), wherein optical proximity correction (OPC) with 193 nm immersion lithography is dominant in the foreseeable future. However, OPC algorithms are getting more aggressive. Consequently, complex mask solutions are outputted. Furthermore, this results in long computation time along with mask data volume explosion. In this chapter, recent state-of-the-art OPC algorithms are discussed. Thereafter, the performance of a recently published fast OPC methodology—to generate highly manufactured mask solutions with acceptable pattern fidelity under process variations—is verified on the public benchmarks.


  • immersion lithography
  • optical proximity correction (OPC)
  • mask
  • edge placement error (EPE)
  • process variability band (PV band)
  • runtime
  • mask manufacturability
  • kernel

1. Introduction

Optical microlithography provides a feasible solution in the foreseeable future for advanced technology nodes patterning with its relatively cheap equipment, if compared with other fabrication techniques. An integrated circuit (IC) design level elements are represented as a set of polygons that are carved onto a pixelated template, called the mask. Mask image is then projected onto a photoresist coating the silicon wafer through an exposure tool. If sufficient light intensity is projected onto the resist, it is chemically exposed. Exposed regions are then etched to form the target circuitry pattern onto the silicon wafer [1, 2].

Complex circuit is made up by repeating lithographic operation for each layer. With the continuous shrinkage of critical dimensions (CDs) of advanced technology nodes following Moore’s law, IC dimensions are being pushed into sub-16 nm according to the International Technology Roadmap for Semiconductors (ITRS) [3]. Thus, light diffraction and interference impact becomes pronounced during circuit printing, which results in wafer image quality degradation. For example, corners are rounded and lines are shortened. Such distortions in the wafer image impact circuit functionality and performance. Besides, it could result in circuit malfunction [4, 5].

To reduce the minimum printable CD, wavelength of the illumination source of the optical system had been steadily reduced till it reached its practical limit at 193 nm due to high instability and strong birefringence of lens materials [6]. Immersion lithography has been introduced to improve the resolution through filling the gap between wafer and projection lens with purified water for higher numerical aperture. However, CD of technology nodes continues scaling down to become small fractions of the wavelength. This makes 193 nm immersion lithography insufficient for modern ICs printing [7].

Resolution enhancement techniques (RETs) aim to improve wafer image quality through manipulating the amplitude and phase of the optical wave to pre-compensate wafer image distortions [8]. Since next-generation lithography (NGL) is still not mature enough, the industry relies heavily on RETs, wherein optical proximity correction (OPC) is dominant, to print sub-16 nm technology nodes in the foreseeable future [9].

In OPC, a mask pattern is iteratively adjusted to obtain an acceptable wafer image quality. However, a lithographic process is susceptible to raw process variations, which result in lithographic yield degradation. Since finding an optimal mask solution with acceptable wafer image quality under all possible process conditions is infeasible, the industry defines a process window including a set of process conditions upon request. The most probable process condition is often defined as nominal process condition under which acceptable wafer image quality is desired with minimizing the variations between different images within the process window [10, 11].

To keep pace with advanced technology nodes, model-based OPC algorithms get increasingly more aggressive. Consequently, complex mask solutions are outputted, which results in mask manufacturability degradation along with explosion in mask data volume [12, 14].

OPC computation time forms another crucial factor. For example, brute force algorithms to find optimal mask solutions are infeasible for industrial cases, wherein, mask data have to be prepared in a matter of hours to cover the huge number of target circuitries [10, 13].

In this chapter, recent state-of-the-art OPC algorithms are discussed. Thereafter, a recently published algorithm in [15, 16] is deeply analyzed and its performance is verified in terms of pattern fidelity under process variations, mask manufacturability, and computation time.

The rest of this chapter is organized as follows: Section 2 briefly discusses recent OPC algorithms and their main shortcomings. Section 3 describes lithographic terminology and mask evaluation metrics. Sections 4 and 5 discuss intensity modeling and the to-be-evaluated OPC methodology, respectively. Experimental results are proposed in Section 6, and Section 7 concludes the chapter.


2. Recent research

Several algorithms have been proposed to minimize edge placement error (around wafer image contours) in model-based OPC. Mask error enhancement factor (MEEF) matrix has been widely adopted to guide edge shifting following EPE changes in each fragment control point [17, 18]. However, such algorithms slowly converge for advanced technology nodes. Source and mask optimization has been proposed in [19] at the cost of long computational time. A fast intensity-based algorithm has been proposed in [20]. However, this algorithm considers only sparse patterns, while recent dense patterns are more challenging. Adaptive fragments refinement has been proposed to improve wafer image quality without significantly considering process variations [21].

Process window OPC algorithms consider both EPE and process variations [22, 23]. However, wafer image has to be simulated under each process condition, which is time-consuming.

Retargeting has been adopted to improve pattern fidelity through modifying the target pattern itself along with the mask at the cost of long computation time [24]. Process variations have been effectively considered through including the intensity slope in the cost function in simultaneous mask and target optimization (SMATO) algorithm [25].

Inverse lithography technology (ILT) has been extensively exploited to find optimal mask solutions based on rigorous mathematical models [26, 27]. However, ILT masks are hard to be manufactured due to ILT pixel-based behaviors.

Sub-resolution assist features (SRAFs) insertion has been widely exploited to increase mask robustness against dose variations [28, 29]. Consideration of multiple process conditions is required upon SRAF insertion/sizing.

To improve mask manufacturability without sacrificing lithographic yield, design aware OPC algorithms include a set of restricted design rules (RDRs) in the OPC recipe. RDRs define the minimum dimensions in mask geometry [30, 31]. Although including RDRs in the OPC preserves acceptable pattern fidelity with less complex masks, long computation time is expected due to the low stability and slow convergence of the algorithm.

To accelerate OPC computation, a fast method has been proposed in [32] to simulate wafer image with less number of kernels. However, using more kernels is required in further iterations. Intensity difference map has been recently proposed in [15] and its performance has been confirmed in [33].

Recently, an effective Process Variation Aware OPC algorithm, namely PV-OPC, has been proposed with good results in terms of pattern fidelity under process variations, computational time, and with considering mask notch rule for higher manufacturability through exploiting variational EPE, and adaptive fragmentation [9]. Furthermore, PV-OPC effectively reduces the number of needed simulations. Mask Optimization Solution with Process Window Aware Inverse Correction (MOSAIC) algorithm has been recently proposed as an ILT algorithm with exploiting variational EPE under each process corner. MOSAIC has two versions: fast and exact [34]. However, complex masks are outputted from this algorithm. A robust approach for process variation OPC has been recently published in [35] at the cost of outputting complex masks.

Recently, a novel intensity-based OPC methodology has been published in [15]. This algorithm outperforms the most recent effective algorithms on the public benchmarks in terms of pattern fidelity under process variations and runtime. Besides, this algorithm has been extended to improve mask manufacturability in [16] with preserving its effectiveness. This algorithm is analyzed in this chapter and its effectiveness is numerically verified through comparing it with other recent algorithms on the most challenging public benchmarks.


3. Lithographic terminology and problem description

A lithographic process is susceptible to raw process variations resulting in lithographic yield degradation. Dose and focus variations are dominant in this context. Thus, a set of dose and focus process conditions that are requested to be considered are defined as a process window Pw.

3.1. Lithographic pattern terminology

Given a region of pixels R wherein a target pattern T is defined such that T ⊂ R. Similarly, a mask pattern M is defined in R such that M ⊂ R.

A pattern consists of a set of nonoverlapped rectilinear polygons where a polygon consists of a set of connected pixels. Let S be a polygon. If a pixel p is contained in S, it is denoted by pS. Furthermore, if p ∈ S ∈ T, it is denoted by pT. The same notation is applied for a pixel pSM, which is simply denoted by pM.

An edge on the boundary of a polygon is either a horizontal or vertical line connecting two corners. Let ET and EM be the set of edges along the boundary of all polygons in T and M, respectively. Let l(e) denote the length of an edge e and D(ei, ej) denote the Manhattan distance between edges ei and ej in a target/mask pattern.

Target pattern: A set of target design rules are defined to be satisfied. This includes: (1) minimum allowable line width, denoted by Lw. (2) Minimum spacing between different polygons, denoted by Ls. Note that, ∀eET; l(e≥ Lw.

A corner on the boundary of a polygon in the target is either positive or negative. A positive corner forms 90° angle outside the polygon, while a negative corner forms 270° angle inside the polygon. Figure 1(a) illustrates a target pattern with both types of corners [15].

Figure 1.

(a) Target pattern T. (b) Mask pattern M [15].

Mask pattern: Mask pattern polygons are classified into three types: core-polygon, serif, and SRAF. Figure 1(b) shows these types. A core-polygon that corresponds to a polygon ST is obtained from S by fragmenting its boundary to segments and shifting them. A segment located on a corner in the target pattern is said to be a corner segment. A serif on a positive corner is a squared feature added outside of the polygon, while, a serif on a negative corner is a square picked from the polygon. An SRAF (scatter bar) is a long bar parallel to an edge of a polygon in the target [15].

A notch is either peak or valley in the polygon geometry, as illustrated in Figure 2(a) [36]. From mask manufacturing perspective, thin notches are forbidden. A jog is the orthogonal edge between two neighboring edges in the mask boundary. Small jogs in an OPC mask typically exist, as shown in Figure 2(b). However, such small features increase shot count during mask writing [12]. Moreover, they increase mask manufacturing process variations, which turns out into pattern fidelity degradation.

Figure 2.

(a) Notch types and width and (b) jogs in the mask boundary.

Mask design rules define a set of constraints to be satisfied in a mask pattern for higher mask manufacturability. In this chapter, the following mask design rules are considered: (1) mask notch rule, which defines the minimum allowable edge length in the mask boundary, denoted by dn. (2) Mask spacing rule, which defines the minimum allowable spacing between patterns in the mask pattern, denoted by ds.

3.2. Lithographic model

A mask M is transformed through an optical and projection system into an aerial image. This image is an intensity map holding a set of light intensities floating onto the resist. The set of exposed pixels within the intensity map forms the image onto the silicon wafer. Let IPc(M) and GPc (M) represent the intensity map and wafer image of mask M under process condition PcPw, respectively, as illustrated in Figure 3.

Figure 3.

Intensity map and wafer image for a given mask pattern.

Sum of coherent systems (SOCS) is often used in OPC to roughly estimate the intensity map [38]. In SOCS model, the optical system is decomposed into a set of coherent kernels working as low pass filters. Each kernel has an eigenfunction, which represents its filtering behavior and eigenvalue and its weight for intensity estimation. For a mask M, intensity map, IPc(M, K), under process condition Pc is defined as given in Eq. (1), where K denotes the set of all kernels in a lithographic system, σkpc and ϕkPc represent the eigenvalue and the eigenfunction for kernels kK under process condition Pc, respectively, and denotes convolution operation.


Once intensity map is obtained, it undergoes resist modeling. Constant threshold resist (CTR) is one of the commonly used resist models, wherein intensity threshold of exposure Ith is predefined. Wafer image GPc (M) is the set of pixels whose intensities are greater than or equal to Ith, as given in Eq. (2), where IPc (M, p) represents the intensity in pixel p by mask M.


3.3. Representative lithographic process conditions

Wafer image gets wider with higher positive dose values. On the other hand, it gets thinner with negative values. Defocus impact causes wafer image to be thinner than its form under nominal focus condition [9]. Thus, for a process window Pw, three representative process conditions are defined as follows (illustrated in Figure 4):

  1. Innermost process condition: Includes the maximum negative dose value and defocus under which innermost intensity map Ii(M), is defined. Innermost wafer image Gi(M) is extracted from Ii(M).

  2. Outermost process condition: Includes the maximum positive dose and in-focus under which maximum intensity map Io(M), is defined. Outermost wafer image Go(M) is extracted from Io(M).

  3. Nominal process condition: Includes average dose and in-focus under which nominal intensity map In(M), is defined. Nominal wafer image Gn(M) is extracted from In(M).

Figure 4.

Representative wafer images: (a) innermost, (b) nominal, (c) outermost.

3.4. Mask evaluation metrics

A mask pattern is evaluated in terms of the pattern fidelity under nominal process condition, robustness against process variations, mask manufacturability, and the computation time required to find that mask solution.

Pattern fidelity evaluation: Edge placement error (EPE) is often used for pattern fidelity evaluation under nominal process condition. EPE is the geometrical distance between a point on the target boundary and its corresponding point onto wafer image contour. Let epe(M, t) denote the EPE for a point tT, as shown in Figure 5. As long as no electric violations occur in the circuit functionality, EPE evaluation can be relaxed. Let EPEmax be the maximum allowable EPE distance [10].

Figure 5.

EPE evaluation [15].

For fast evaluation, EPE is statically measured among a set of tap points defined on the boundary of T, as given in Figure 5. Let A denote the set of defined tap points. For each tA, let t+T be a point whose distance from t is EPEmax pixels, which is on the line that passes t and perpendicular to its edge in the target. Similarly, tT is defined but inside the polygon in T. For a tap point tA, it is said to be not in EPE state if In(M, t) ≥ Ith and In(M; t+< Ith. Otherwise, t is said to be in EPE state. The number of EPE violations for mask M, denoted by #EPEV(M), is the number of tap points in EPE state. Pattern fidelity of a mask M is assumed to be inversely proportional to #EPEV(M) [15].

Process variability evaluation: Process variability (PV) band area is a commonly used metric for process variations. PV band area is the area denoted by XORing wafer images under all process conditions within process window Pw.

Innermost and outermost wafer images are exploited to provide a fast and roughly sufficient estimation for PV band area. For a mask M, PV band area, denoted by PV(M), is the XOR area between Gi(M) and Go(M). The less the PV band area, the more is the mask robustness against process variations. Figure 6 illustrates PV band area for a given mask [17].

Figure 6.

(a) Innermost intensity map, (b) outermost intensity map and (c) PV band area.

Mask manufacturability evaluation: Mask manufacturability is evaluated in terms of satisfying mask notch and spacing design rules. The more the rule violations, the lower is the manufacturability of the mask. Figure 7(a) illustrates examples of design rule violations. Mask notch rule defines the minimum allowable edge length in the mask polygons, denoted by dn. Thus, the number of mask notch rule violations of mask M, denoted by #NotchV(M), is formulated as in Eq. (3):


Two edges in the mask boundary violate mask spacing rule if the Manhattan distance between them is less the minimum allowable spacing distance ds. However, both edges should either belong to two different polygons or belong to the same polygon without overlapping between them, as illustrated in Figure 7(b). Such edges are said to be a comparison pair. Consequently, the number of spacing rule violations, denoted by #SpaceV(M), is given in Eq. (4), where Cp represents the set of comparison pairs in M. Comparison pairs of a mask can be retrieved by bounding techniques [16].


Figure 7.

(a) Design rule violations and (b) comparison pair examples [16].


4. Tap point intensity estimation

The purpose of the proposed intensity modeling in [17] is to roughly estimate the intensity map of a mask using SOCS model within a short time. As lower weight kernel contribution in intensity value is typically small [32], such contribution in intensity value for each pixel does not dramatically change much if a mask pattern is slightly modified. On the other hand, top weight kernel contribution is significantly affected by such mask modifications. Thus, by utilizing lower weight kernel intensity information of some reference mask, the intensity map of a general mask can be estimated using only top weight kernel, followed by proper compensation with exploiting the intensity information of the reference mask.

4.1. Top weight kernel intensity modeling

Let F1(d) and F2(d) be the functions that represent the intensity impact induced by a segment to its own tap point and to the neighbor tap point, respectively, where d represents the shifting distance of that segment from its original position in the target T. The differences of intensity impact to a segment tap point and to neighbor tap point between cases when the shifting distances of that segment are d and d’ are represented by F1(d, d’) and F2(d, d’), respectively. Let B(w) represent the intensity impact induced by a serif feature on a corner to tap point t located on a corresponding corner segment, where w represents the width of the serif. The differences of intensity impact between cases when the widths of the serif are w and w’ are represented by B(w, w’) [15].

With assuming the linearity of Fj as proposed in [15], Fj(d, d’= Fj(d’) − Fj(d) = αj (d’ − d), where αj is a constant (j = 1, 2) obtained by regression. Additionally, it is assumed that B is a quadratic function such that B(w, w’= B(w’) − B(w) = β (w’ − w)2+γ (w’ − w), where β and γ are constants obtained through regression.

Let (s0, s1, …, sm) be a sequence of segments defined along the edge between corner c0 and c1 on the boundary of a polygon in T by fragmentation, and ti be the tap point of si (0 ≥ im). Let d’i and di be the shifting distances from the boundary in the target T for segment si in masks M and Mref, respectively. In addition, let wj and wj be the widths of serif feature on a corner cj in masks M and Mref, respectively (0 ≥ im, 0 ≥ j ≥ 1). Figure 8 depicts the given situation. With exploiting top kernel modeling, the intensity IPc (M, ti) of tap point ti under process condition Pc is given in Eq. (5) for corner segment and in Eq. (6) for non-corner segment, where ∆x = x’- x [17].


Figure 8.

Top weight kernel modeling situation [17].

4.2. Lower weight kernel intensity modeling

Intensity difference map (IDM) is introduced as the mathematical difference between two intensity maps obtained using two sets of kernels [33]. Let Idiff (M, K, K’) be the IDM between intensity maps I(M, K) and I(M, K’), where I(M, K) denotes the intensity map obtained using set of kernels K and K’ K, respectively, as formulated in Eq. (7).


Typically, there is a trade-off between intensity map accuracy and the number of kernels used to obtain that map. However, with relaxed EPE evaluation, a set of top weight kernels in a lithographic system can be sufficient to be used for in intensity estimation, and thus, to guide the OPC response. Let K denotes the set of all kernels and Ksuff K denote the set of top weight kernels roughly sufficient for optimization. Besides, let k0 K denote the top weight kernel [15].

In lower weight kernel modeling, intensity map for a mask M is roughly estimated through using a reference mask Mref (both M and Mref have been derived from the same target) as follows: The IDM of mask Mref under a certain process condition is obtained using Ksuff and {k0}. To estimate the intensity map of mask M, IDM works as a compensative map to the top weight kernel intensity map as given in Eq. (8). This modeling reduces effectively the simulation time since only one convolution operation is required [15].


5. OPC engine framework

Figure 9 illustrates the general framework of the OPC engine proposed in [15, 16]. Before performing the actual OPC algorithm, a preprocessing phase, wherein, the parameters that guide OPC algorithm are found through regression. The input of the OPC algorithm is a target pattern and the output is a mask solution. This algorithm consists of initialization phase, input intensity modeling, mask correction phase, mask evaluation, and post-OPC phase.

Figure 9.

OPC engine framework.

5.1. Initialization phase

This phase aims to accelerate the algorithm convergence through finding an initial mask solution whose pattern is not much deviated from the final mask solution. Initialization phase includes the following:

Layout fragmentation: Edges along the boundary of target T are fragmented into segments. Segment length Lseg is predefined such that Lseg is greater than the minimum allowable notch width dn. If a segment length is less than dn, it is equally concatenated with its neighbors. The center for each segment si on the target is defined as a tap point ti, as illustrated in Figure 10 [15].

Figure 10.

Fragmentation process [15].

Intensity Difference Map (IDM) construction: One extra mask correction step is applied to generate a mask M[0] whose features are printable around target boundaries. With setting Mref = M[0] and K = Ksuff, IDM is constructed and exploited as in Eq. (9) to estimate intensity map of a mask M, where k0 represents the top weight kernel in K [15].


5.2. Input intensity modeling

An OPC algorithm typically tries to make the nominal intensity curve of a given tap point crossing the target boundary at Ith, as depicted in Figure 11(a). The distance from the target boundary to the cross-point of innermost intensity at which Ii = Ith contributes to PV band as well as distance from target boundary to the cross-point of outermost intensity. However, the innermost intensity cross-point to Ith is typically larger from the target boundary than the outermost intensity cross-point.

Figure 11.

(a) Nominal intensity is considered to reach Ith, resulting in PV as PV band area indicator. (b) Adjusted intensity is considered to reach Ith, resulting in PV< P V as PV band reduction [17].

With making the cross-point of nominal intensity with Ith slightly outside the target boundary, PV band area can be reduced (as shown in Figure 11b). This is reasonable because the innermost intensity cross-point to Ith reaches close to the target boundary, which results in lesser PV band, since outermost intensity has already been saturated and its cross-point distance from target boundary is not expected to change significantly.

As an implementation, let Idef (M) denote the intensity map under nominal dose and defocus. In(M) denotes the nominal intensity under nominal dose and best-focus. In [15], the adjusted intensity map is defined, denoted by Iadj(M), as the intensity map obtained by averaging both In(M) and Idef (M), as given in Eq. (10).


5.3. Mask correction phase

Mask correction phase applies a set of OPC steps on the input mask to optimize both EPE and PV band area with satisfying design rules. Adjusted intensity map of the input mask drives segment shifting and corner hammering, while innermost and outermost maps control SRAFs insertion.

Two-segment shifting: Let si and si + 1 be two neighboring segments with positions Pi and Pi + 1, respectively, in mask M (see Figure 12(a)). The purpose is to find the new positions of those segments, denoted by P’i and P’i + 1, such that the estimated intensities of their tap points become Ith. With exploiting top weight kernel model, the objective is to find (Δ Pi, Δ Pi + 1) in Eq. (11) such that Δ Pi = P’i -Pi, Δ Pi + 1 = P’i + 1 -Pi + 1. With solving Eq. (11), the new positions P’i and P’i + 1 are given in Eq. (12). Figure 12(b) illustrates two-segment shifting subroutine [15].


Figure 12.

Two-fragment shifting: (a) current situation and (b) subroutine.

Consider the situation of non-corner segments si-1, si, si + 1 in mask M shown in Figure 13(a). As illustrated in Figure 13(b), Two-fragShift subroutine is applied first to si-1 and si, followed by setting their tap point intensities to Ith. I(ti + 1) change due to si shifting is linearly estimated according to top weight kernel modeling. These data are inputted to Two-fragShift subroutine, which is then applied to si and si + 1 [15].

Figure 13.

Edge non-corner fragments shifting: (a) situation and (b) subroutine [15].

Corner hammering: Let c be a corner wherein corner segments ac and bc meet (in target T). A hammer is formed on c by shifting both ac and bc outside the polygon with distance wc. This shifting amount is equivalent to the serif width as depicted in Figure 14(a). Thus, the purpose is to find the serif width w’c such that the average intensity of both corner segments tap points, denoted by tac and tbc, becomes equivalent to Ith [15]. For a negative corner, both corner segments are shifted inside and a squared serif is picked from T, as shown in Figure 14(b).

Figure 14.

(a) Hammer insertion and (b) negative corner hammering [17].

However, due to the nonlinearity of the hammering problem, several solutions might exist. However, w’c is chosen within the interval [wmin, wmax], which represents the minimum and maximum allowable serif width, where wmin dn to satisfy notch rule and wmax is predefined to neglect oversized serif solutions. This problem is formulated in Eq. (13) [15].


Segment alignment: Alignment aims to ensure satisfying notch rule during segment shifting. Thus, a number of parallel lines to each edge in the target are created with dn spacing between each two consecutive lines. In this way, each segment is aligned to the closest line parallel to it after shifting, as shown in Figure 15 [16].

Figure 15.

Segment alignment [16].

SRAF insertion: With increasing the distance between an SRAF and a tap point t, the difference between outermost intensity and innermost intensity of t does not monotonically decrease. Therefore, global minimal values of this difference within the decaying intervals are SRAF candidate locations to ensure reducing Io(M, t) - Ii(M; t), which turns out into lesser PV band area. SRAF candidate locations are determined during preprocessing stage [15].

5.4. Post-OPC phase

Post-OPC phase aims to improve mask manufacturability through reducing mask data volume and spacing rule violations resolution. This phase consists of the following:

Segment concatenation: Reducing the segment numbers along the mask boundary helps in reducing mask data volume along with reducing the shot-count. This is achieved through two-segment concatenation. However, ad hoc concatenation of neighboring segments badly impacts pattern fidelity.

Let sa and sb be two neighboring segments with Δhab orthogonal distance between them (Figure 16(a)). Let epeprea and epepreb denote the predicted EPE in tap points ta and tb, respectively, after concatenation. Concatenation process is performed as follows [16]:

  • If epeprea < epepreb and epepreaepemax, shift sa to concatenate with sb (Figure 16(b)).

  • if epepreb < epeprea and epeprebepemax, shift sb to concatenate with sa (Figure 16(c)).

  • If the predicted EPE causes violation, no concatenation is performed.

  • If concatenation is done, sa and sb become one segment sab.

Figure 16.

Concatenation process [16]: (a) before concatenation, (b) sa is moving, and (c) sb is moving.

Feature movement: Segment/SRAF extra movement aims to resolve spacing violations in the mask pattern outputted from concatenation process. This is strictly subjected to the constraint that no additional EPE violations occur, as illustrated in Figure 17 [16].

Figure 17.

Spacing violation resolution cases [16]: (a) two parallel features, (b) two orthogonal features, (c) SRAF and segment, and (d) two SRAFs.


6. Experimental results and discussion

6.1. Experimental setup

Simulation environment: Lithosim uses industrial optical models with 193 nm immersion lithography. CTR model is used with intensity threshold of 0:225. Layout patterns are defined in 1024 × 1024 pixels region, where each pixel represents 1 nm × 1 nm. A set of 24 SOCS kernels forms the optical model in Lithosim [11].

OPC algorithm parameters: The proposed OPC algorithm in [16] has been implemented on top of Lithosim. The algorithm was executed on 4 cores 3.6 GHz Linux machine with total memory of 1,986,912 kB. Segment length has been chosen as 20 nm; minimum allowable mask notch has been set practically to 5 nm. The maximum allowable hammer width is 80 nm; maximum allowable SRAF width is 60 nm. The maximum number of iterations has been set to 10.

Testing benchmarks: Testing benchmarks have been provided by IBM for ICCAD 2013 CAD contest. Each benchmark is an M1 layout pattern for 32 nm technology nodes. The CD of those benchmarks ranges from 20 to 80 nm. The number of patterns (polygons) in those benchmarks ranges between 4 and 34 polygons with layout density ranges from 0.3 to 0.46 due to the pitch spacing design rules for realistic industrial cases [11].

Mask evaluation: The score function used in ICCAD 2013 CAD contest is used for evaluation [37]. Given a mask M, the score of M, denoted by φM, is given in Eq. (14), where τ denotes the computation time to find a mask and ζ represents the number of hole shapes in the corrected mask. α, β, and γ are set to 5000, 4, and 10,000 following the contest.


6.2. Comparison with recent algorithms

The proposed algorithm in [16] has been compared with recently published algorithms executed on the same benchmarks. Table 1 shows a comparison between the proposed algorithm and state-of-the-art algorithms including: MOSAIC fast [36], MOSAIC exact [36], and PV-OPC [11].

BenchmarkMOSAIC fastMOSAIC exactPV-OPCProposed algorithm [16]

Table 1.

Comparison with state-of-the-art.

The proposed algorithm in [16] outperforms MOSAIC fast in the overall score and it is 3.76 times faster. MOSAIC fast is effective in terms of PV band area due to its pixel-based behavior in finding the mask solution under each process condition. However, it has lack of estimation accuracy, which turns out into pattern fidelity degradation. MOSAIC exact effectively optimizes both EPE and PV band area since it simulates wafer image under each process condition using all kernels. However, this algorithm slowly converges. While the proposed algorithm in [16] has almost the same cost of MOSAIC exact in terms of EPE and PV band area, it is 22 times faster. PV-OPC is an effective algorithm as it exploits variational EPE under representative process conditions with satisfying mask notch rule. Keep out zone (KOZ) concept is exploited as well to avoid pinching and bridging errors between patterns. Thus, PV-OPC algorithm outperforms [16] in terms of EPE while [16] has less PV band area due to input intensity modeling and SRAFs insertion. Additionally, the proposed algorithm in [16] is 1.65 times faster. Note that PV-OPC does not consider spacing rule violations and mask data volume reduction.

Generally, it seems obvious that the proposed algorithm in [16] outperforms other recent algorithms, specifically in OPC runtime as it is 1.65 times faster than the fastest algorithm among others. Exploiting intensity difference map concept is the main reason, which turns out into minimizing the number of kernels needed for simulation during optimization.

To verify the effectiveness of the proposed OPC algorithm from mask manufacturability perspective, the algorithm published in [35] and the proposed algorithm in [16] have been compared in terms of mask notch and spacing rule violations, in addition to the mask data volume. Table 2 shows this comparison, in which pattern fidelity, process variability, and computation time are included.

BenchmarkAlgorithm published in [35]Proposed algorithm in [16]

Table 2.

Mask manufacturability comparison with state-of-the-art algorithm.

As shown Table 2, the algorithm in [35] effectively tackles pattern fidelity under nominal process condition. However, it has a relatively large PV band area. Algorithm in [16] outperforms the overall score of the algorithm published in [35] by 9%. Additionally, it is 2.5 times faster. Mask notch violations have been totally eliminated due to alignment stage while spacing violations have been reduced by 92% on average due to features movement. Mask data volume has been reduced by around 57.6% on average due to segments concatenation and alignment.

Figure 18 illustrates a target pattern, its generated mask solution using the proposed algorithm in [16], nominal wafer image, and PV band.

Figure 18.

(a) Target pattern, (b) mask solution using [18], (c) nominal wafer image, and (d) PV band.


7. Conclusions

In this chapter, we have discussed the recent state-of-the-art OPC algorithms to tackle mask optimization problem for advanced technology nodes patterning through optical system. Then, we have analyzed the algorithm published in [17, 18] as fast, recent OPC methodology to generate mask solutions. The analyzed algorithm outperforms other state-of-the-art algorithms in terms of EPE and PV band area reduction due to OPC adjustments guided by adjusted intensity in addition to SRAFs insertion/sizing. Computation time reduction is evident due to the fast novel intensity estimation model exploited in the OPC engine. Mask manufacturability has been significantly improved due to the post-OPC stages, wherein EPE prediction models are exploited to preserve acceptable pattern fidelity and robustness against process variations while respecting mask design rule constraints.


  1. 1. Xu M, Arce G. Computational Lithography. Wiley Publisher; 2010
  2. 2. Mack C, Carback R. Modeling the effects of prebake on positive resist processing. Proceedings of Kodak Microelectronics Seminar Interface. 1985. pp. 155-158
  3. 3. International Technology Roadmap for Semiconductors. Technical Report. 2014.
  4. 4. Wong B, Mittal A, Starr G, Zach F, Moroz V, Kahng A. Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for sub-65nm Technology Nodes. Wiley Publisher; 2008
  5. 5. Mack C. Corner rounding and line-end shortening in optical lithography. Proceedings of SPIE. 2000;4226:83-92
  6. 6. Harriott L. Limits of lithography. Proceedings of IEEE. 2002:366-374
  7. 7. Wei Y, Back D. 193 nm Immersion Lithography: Status and Challenges. SPIE Newsroom; 2007
  8. 8. Shibuya M. Resolution Enhancement Techniques for Optical Lithography and Optical Imaging Theory. Optical Review. 1997
  9. 9. Su Y-H, Huang Y-C, Tsai L-C, Chang Y-W, Banerjee S. Fast lithographic mask optimization considering process variation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. 2016
  10. 10. Awad A, Takahashi A, Tanaka S, Kodama C. A fast process variation and pattern fidelity aware mask optimization algorithm. Proceedings of ICCAD. 2014. pp. 238-245
  11. 11. Banerjee S, Li Z, Nassif S. CAD contest in mask optimization and benchmark suite. Proceedings of ICCAD. 2013. pp. 271-274
  12. 12. Word J, Mizuuchi K, Fu S, Brown W, Sahouria E. Mask shot count reduction strategies in the OPC flow. Proceedings of SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV. 2008
  13. 13. Tanaka S, Inoue S, Kotani T, Izuha K, Mori I. Impact of OPC aggressiveness on mask manufacturability. Proceedings of SPIE 5130, Photomask and Next-Generation Lithography Mask Technology. 2003
  14. 14. Cobb N, Zakhor A. Fast sparse aerial image calculation for OPC. Proceedings of SPIE. 1995;2621:534-545
  15. 15. Awad A, Takahashi A, Tanaka S, Kodama C. A fast process variation aware mask optimization algorithm with a novel intensity modeling. IEEE Transactions on Very Large Scale Integration Systems (TVLSI). 2017;25(3):998-1011
  16. 16. Awad A, Takahashi A, Kodama C. A fast mask manufacturability and process variation aware OPC algorithm with exploiting a novel intensity estimation model. IEICE Trans. Fundamentals. 2016;E99-A(12):2363-2374
  17. 17. Cobb N, Granik Y. Model-based OPC using the MEEF matrix. Proceedings of Annual BACUS Symposium on Photomask Technology. 2002. pp. 1281-1292
  18. 18. Lei J, Hong L, Lippincott G, Word J. Model-based OPC using MEEF matrix II. Proceedings of SPIE 9052, Optical Microlithography XXVII. 2014
  19. 19. Fuhner T, Erdmann A. Improved mask and source representations for automatic optimization of lithographic process conditions using a genetic algorithm. Proceedings of SPIE 5754, Optical Microlithography. 2005
  20. 20. Yu P, Pan D. A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. Proceedings of ICCAD. 2007. pp. 854-858
  21. 21. Mukhejree M, Buamm Z, Lavin M, Samuels D, Singh R. Method for adaptive segment refinement optical proximity correction. US Patent 7043712. 2006
  22. 22. Yu P, Shi S, Pan D. Process variation aware optical proximity correction with variational lithography modeling. Proceedings of DAC. 2006. pp. 785-790
  23. 23. Krasnoperova A, Culp J, Graur I, Manseld S, Al-Imam M, Maaty H. Process window OPC for reduced process variability and enhanced yield. Proceedings of SPIE 6154, Optical Microlithography XIX. 2006
  24. 24. Agarwal K, Banerjee S. Design driven patterning optimization for low K1 lithography. Proceedings of IEEE International Conference on IC Design & Technology. 2012. pp. 1-4
  25. 25. Banerjee S, Agarwal K, Orshansky M. SMATO: Simultaneous mask and target optimization for improving lithographic process window. Proceedings of ICCAD. 2010. pp. 100-106
  26. 26. Pang L, Liu Y, Abrams D. Inverse lithography technology (ILT), what is the impact to photomask industry?. Proceedings of SPIE 6283, Photomask and Next-Generation Lithography Mask Technology. 2006
  27. 27. Liu Y, Abrams D, Pang L, Moore A. TIP-OPC: Inverse lithography technology principles in practice: unintuitive patterns. Proceedings of SPIE. 2005;5992:886-893
  28. 28. Mulkherjee M, Manseld S, Leibmann L, Lvov A, Pa-padopoulou E, Lavin M, Zhao Z. The problem of optimal placement of sub-resolution assist features (SRAF). Proceedings of SPIE 5754, Optical Microlithography, 2005
  29. 29. Manseld S, Liebmann L, Molless A, Wong A. Lithographic comparison of assist features design strategies. Proceedings of SPIE. 2000;4346:63-76
  30. 30. Capodieci L, Gupta P, Kahng A, Sylvester D, Yang J. Toward a methodology for manufacturability-driven design rule exploration. Proceedings of DAC. 2004. pp. 311-316
  31. 31. Gupta P, Kahng A, Muddu S, Nakagawa S, Park C-H. Modeling OPC complexity for design for manufacturability. Proceedings of SPIE. 2005;5992:1-9
  32. 32. Gallatin G, Lai K, Mukhejree M, Rosenbluth A. Printability verification by progressive modeling accuracy. US Patent 7512927. 2009
  33. 33. Awad A, Takahashi A, Tanaka S, Kodama C. Intensity difference map (IDM) accuracy analysis for OPC efficiency verification and further enhancement. IPSJ Transactions on System LSI Design Methodology. 2017;10:28-38
  34. 34. Gao J-R, Xu X, Yu B, Pan D. MOSAIC: Mask optimization solution with process window aware inverse correction. Proceedins of DAC. 2014. pp. 1-6
  35. 35. Kuang J, Chow W-K, Young E. A robust approach for process variation aware mask optimization. Proceedings of DATE. 2015. pp. 1591-1594
  36. 36. Acosta C, Salazar D, Morales D. A novel algorithm for notch detection. Proceedings of SPIE. 2013;8701
  37. 37.
  38. 38. Cobb N. Sum of Coherent Systems Decomposition by SVD, Berkeley CA. 1995. pp. 1-7

Written By

Ahmed Awad, Atsushi Takahashi and Chikaaki Kodaman

Submitted: 25 August 2017 Reviewed: 24 November 2017 Published: 24 December 2017