Open access peer-reviewed chapter

Main RF Structures

By Paulo Crepaldi, Luis Ferreira, Robson Moreno, Leonardo Zoccal and Tales Pimenta

Submitted: February 3rd 2011Reviewed: March 8th 2011Published: July 20th 2011

DOI: 10.5772/26000

Downloaded: 1835

1. Introduction

The low noise amplifiers – LNA and the mixers are among the most used structures used in RF integrated circuits. Therefore the goal of this chapter is to present an analysis overview of them as well as the main considerations of their design. Nevertheless, since their interconnections play an important role on performance and noise isolation, this chapter will also describe their AC and DC coupling.

2. Inter-connection

Consider initially a simple common source amplifier stage, with the load impedance ZL, as given in Fig. 1. Consider also the simplified transistor model as shown in Fig. 2.

Figure 1.

Simple common source stage.

Figure 2.

Simplified circuit model of Fig. 1.

The gain of this stage can be easily calculated as below.

Av=VoutVin=gmZLE1

Assume this common source stage drives the gate of the following circuit. This next stage needs proper biasing. Usually the DC bias of one stage does not interfere with the bias of another stage, thus the output of the common source stage and the input of the following stage are separated by a DC block capacitor as indicated in Fig. 3. Usually, the biasing resistor Rbias is large enough to prevent RF or analog signal from flowing into a bias source.

Figure 3.

AC coupling with DC block capacitor.

At high frequency, the effect of the DC block capacitor is negligible, since the DC block capacitor is virtually short. The effect of the large biasing is also negligible since it is connected in parallel with the drain resistor of the first stage. The simplified circuit model is presented in Fig. 4.

Figure 4.

Common-source stage with RC-load.

When no inductor is used, the only available load is RC-load, thus the load amplifier becomes:

ZL=R1+RCsE2

The circuit topology of Fig. 4 is well known and corresponds to a low pass filter configuration. The frequency response of this filter is shown in Fig. 5 and its gain is given by:

Av=gmR1+RCE3

Figure 5.

Frequency response of Fig. 4.

Hence, the DC gain is -gmR and the bandwidth is ω1 = 1/RC. The frequency ω1 is called “uncompensated bandwidth”. After frequency ω1 the gain decreases at the rate of -20dB/dec.

Unfortunately, at low frequency, the effects of DC block capacitor and the bias resistor are more severe, since the equivalent circuit, at low frequency, is a high pass filter.

Therefore, one can expect huge loss of information at very low frequencies for some applications such as Direct-Conversion transceiver, which carries information around DC. Even for DC-free applications, the cutoff frequency should be considered for the high pass filter. Since the 3dB cutoff frequency is defined as 1/RC, one can increase resistance and capacitance. However the capacitor normally occupies more space in integrated circuit than a resistance. Therefore, only the resistance should be increased, only up to few Mega ohms, so that a smaller capacitance can be used.

2.1. DC coupling

As reviewed in previous section, the AC coupling is suitable for RF circuitry, but may present DC blocking problems for baseband analog circuitry. Thus, if information around DC is concerned, one should integrate blocks with DC coupling. The DC coupling consists of combining two blocks so that the DC output voltage level of the previous block is same as the DC input bias voltage of the following block, and thus there is no reason to insert a DC block capacitor between them. The DC coupling is certainly advantageous at low frequency, and since the common-source stage model of Fig. 4 is valid for both low and high frequency, it is also suitable for high frequencies; nevertheless it may restrict the freedom of biasing.

Since the modern integrated technology allows construction of inductors, the designer should know the advantages the inductor can add in the circuit design. This section shows how to enhance the bandwidth using the ‘shunt-peaking’ technique. It consists of adding an inductor in series with the resistor, as shown in Fig. 6.

Figure 6.

Common-source stage with RLC-load.

The load impedance for this case becomes:

ZL=(R+Ls)||1Cs=R+Ls(R+Ls)Cs+1E4

And, substituting this value in (2), one can find that:

Av=gm(R+Ls)(R+Ls)Cs+1=gmR[s(L/R)+1]s2LC+sRC+1E5

Observe that the inductor added a zero, which always increases the bandwidth, and also two poles. These poles can be complex conjugate, and this also can increase bandwidth, yet they introduce peaking, hence the name of the method. On the other side, the difference between the number of finite poles and finite zeros is still one. This means that the asymptotic decrease of gain is the same as in the previous circuit, –20 dB/dec. Thus the inductor allows modifying the gain locally, in the vicinity of the frequency ω1, and the designer should use this possibility to his/her advantage.

Consider the amplitude of the frequency response for this circuit, given as

|Av(jω)|=gmR(ωL/R)2+1(1ω2LC)2+(ωRC)2E6

To facilitate subsequent derivations, it is introduced a factor m, defined as the ratio of the RC and τ = L/R time constants,

m=RCL/R=R2L/C=R2ρ2E7

Here ρ=L/Cis the wave resistance of the load. This allows writing two more useful relationships, namely, τ2m=L2R2R2L/C=LCandτm=LRR2L/C=RC. Using these relationships (5) can be written as:

Av(jω)gmR=(ωτ)2+1(1ω2τ2m)2+(ωτm)2E8

The right side of (7) is considered the normalized gain.

First, the bandwidth will be maximized without any consideration regarding the behavior to the gain in the bandwidth. The frequency where the right side equals 1/2is denoted as ω-3dB. Considering a new parameter defined as x = ω-3dB τ, then one has the equation:

2(x2+1)=(1x2m)2+(xm)2E9
or
x4m2+x2(m2m2)1=0E10

From this equation one can find that:

x2m2=m22+m+1+(m22+m+1)2+m2E11
But:
x2m2=ω3dB2τ2m2=ω3dB2(RC)2=(ω3dBω1)2E12

And maximizing the right side of (10) by proper choice of m one can find the maximum available bandwidth, given as:

f3dB(m)=(m22m2)2+4m2m2+2mE13

Differentiating and equating the derivative of (12) to zero, one can obtain:

(m22m2)(m1)+2m=(m1)(m22m2)2+4m2E14

Squaring both sides of this equation, then:

(m1)(m22m2)=m[(m1)21]E15

And from this equation one finally finds that the required value of m is2.

Substituting this value of m in the right side of (10), then:

(ω3dB/ω1)|max=2+2=1.847E16

Hence the bandwidth is improved nearly two times as shown in Fig. 7. Consider as an example improving the bandwidth from 1 GHz to 1.85 GHz. This is tremendous improvement with the addition of just one inductor.

Unfortunately, however, this choice of m leads to nearly 20% peaking. Indeed, with this choice of m:

|Av(jω)gmR|2=x2+1(1x22)2+(x2)2=y+12y22(21)y+1E17

Where x=ωτ, and y = x2. Differentiating the right side of (16) and equating the derivative to zero, one obtains that the maximal value of the right side occurs at y obtained from the equation:

2y2+4y(221)=0E18

The solution of this equation gives y=0.3836, i.e.x=y=0.6193=(ωτ)|peaking. Therefore:

ωpeaking=0.693τ=0.693mRC=0.6932RC=0.98ω1ω1E19

And the normalized amplitude frequency response has the value of:

|Av(jωpeaking)gmR|2=0.3836+120.383622(21)0.3836+1=(1.1904)2E20

This corresponds to a peaking about 1.5dB, as shown in Fig. 7.

Figure 7.

Frequency enhancement by Fig. 6.

However, there are many applications where the frequency response should be completely free of peaking. Therefore, consider again:

|Av(jω)gmR|2=x2+1(1x2m)2+(xm)2E21

Where x=ω, as it was before, and require that the right side does not have any other maximums, except x = 0. The search of maximum leads to:

2x(12x2m+x2m2+x4m2)=(x2+1)(4xm+2x3m2+2xm2)E22

One of possible solutions of this equation is x = 0. Other solutions can be obtained from the equation:

2x2m+m22m1=0E23

One can see that two other solutions will be at x = 0 as well, if:

m22m1=0E24

This gives:

m=1+2=2.414E25

Direct calculation using (10) shows that this value of m leads to a bandwidth:

ω3dB/ω1=1.707E26

The corresponding amplitude frequency response is shown in Fig. 8.

Figure 8.

Maximally flat frequency response.

For this choice of m, both the first and second derivatives of the right side of (20) equal zero at x = 0. This amplitude frequency response can be considered as maximally flat. For this reason this choice of m is also very frequently used.

In other situations, there may be a specification on the time response of the amplifier, rather than on frequency response. The amplifier must not only amplify uniformly the various spectral components of the signal over as large a bandwidth as practical, but the phase relationships among its Fourier components must be preserved as well. If all frequencies are delayed by an equal amount of time, then this fixed amount of time delay must represent a linearly increasing amount of phase shift as frequency increases. Phase distortion will be minimized if the deviation from this ideal linear phase shift is minimized. Evidently, then, the delay as the function of frequency must be examined. If this delay is the same for all frequencies, there will be no phase distortion. The delay is defined as

TD(ω)=dϕdωE27

Where ϕis the phase shift of the amplifier at frequency ω.

Using (4), then:

Av(jω)gmR=1+jωτ1ω2τ2m+jωτmE28

And from this expression, one can find that:

ϕ(ω)=tan1ωτ+tan1(ωτm1ω2τ2m)E29

It is impossible for this amplifier to provide a constant time delay over an infinite bandwidth. It is reasonable to provide, then, with an approximation to a constant delay over some finite bandwidth. A maximally flat time delay will result the number of derivatives of TD(ω), whose value is zero at DC, is maximized.

This derivation is rather complicated. Ultimately, however, on may derive the following cubic equation for m as:

m33m1=0E30

whose relevant root is:

m=1+(3+52)1/3+(352)1/33.104E31

which is corresponding to a bandwidth improvement factor a little bit less than 1.6.

Since the conditions for maximally flat amplitude frequency response and maximally flat time delay do not coincide, one can compromise. Depending on requirements, there is a range of useful inductance value. A larger L (smaller m) gives the bandwidth extension but poorer phase linearity, whereas a smaller L yields less bandwidth improvement but better phase linearity. All considered cases are summarized in Table 1.

Conditionm=R2C/LNormalized bandwidthNormalized peak frequency response
Maximum bandwidth1.4141.851.19
Maximally flat bandwidth2.4141.7071
Maximally flat time delay3.1041.61
No shunt peaking11

Table 1.

Shunt peaking design summary.

3. Low noise amplifier

Low noise amplifier – LNA is the most critical block in the receiver signal chain, since it determines the overall noise Fig. of the received signal, so that it determines the quality of communication system.

There are several issues on LNA design for UWB applications. First, it must provide wideband impedance matching for both optimal power transfer and noise characteristic. Second, it should be a low power implementation with high power gain. According to the 802.13a specification [1] [2], it is required a power gain of at least 15dB with less than 3dB noise Fig. Since, one of the biggest applications of UWB systems is low-power implementation, the LNA should be able to operate in low supply voltage. The third issue is gain flatness to avoid any signal distortion over such a wide bandwidth.

In terms of wideband impedance matching, the most popular methods are the feedback topology, the distributed impedance matching, the BPF configuration matching network, and the common-gate topology. Nevertheless, each method has advantages and disadvantages, so it is difficult to select one single method for UWB LNA design. For example, feedback topology has good noise and impedance matching performance, but degrades the achievable power gain. The other side, BPF configuration matching is able to achieve high power gain with spurious impedance matching performance in addition to great frequency selection characteristics, while increasing noise Fig. with more passive components used to implement the filter.

This section discussed a unique UWB CMOS LNA, which utilizes both feedback, and BPF configuration method, as presented in [3].

3.1. LNA circuit synthesis

In general, it is very difficult to establish a systematic method for LNA design with satisfying simultaneously low noise factor, impedance matching, and high gain. The major difficulty comes from the fact that the optimal source impedance for optimal noise is different from the matching condition for maximum power delivery. So it is very important to confirm initial design decisions of circuit parameters because two matching conditions are highly related. Also, too simplified circuit model forces trial-and-error strategy for optimizing the circuit. Therefore, accurate circuit evaluation is required to avoid the tedious effort for circuit optimization. Thus, the accurate Miller effect of source degenerative topology with cascode topology, and a methodology to utilize the Miller effect for the input matching network implementation are presented in this section.

The overall LNA schematic, including input and output impedance matching network, is shown in Fig. 9. The LNA looks like a simple conventional narrowband LNA with one gate

Figure 9.

Overall LNA architecture.

inductor. However, the LNA can achieve wideband input matching by using Miller effect as explained later. Also, the UWB LNA architecture does not make use of a source follower for output matching, but has passive output matching network, which consists of bandpass filter and impedance inverting scheme.

3.2. Transistor sizing and bias condition

Since the size of transistors and their bias condition determine power dissipation, it is often recommended to establish them under a certain power budget. However, the size of transistor versus its bias condition should be evaluated carefully, because they are also related to impedance seen by input gate. Thus, the best choice is to determine the size and bias condition to satisfy both impedance matching and noise matching with limited bias current. In fact, there is no much freedom for this choice technically. According to the MOSFET noise analysis [4], the generator admittance for optimal noise performance is known as (31) and (32).

Gopt=αωCgsδ5γ(1|c|2)E32
Bopt=ωCgs(1+α|c|δ5γ)E33

whereα=gm/gd0, the parameters and are given in Chapter 3, and c is defined as the correlation between the drain noise ind and the gate noise ing currents, given as:

c=ing.ind*¯ing2¯.ind2¯E34

For the sake of simplicity, initially the correlation of noise can be ignored, so that c has to be 0. Therefore, (31) and (32) can be simplified as:

Ropt1αωCgs5γδE35
Xopt1ωCgsE36

Furthermore, (35) can be modified to (36) in order to take account of the degenerative inductor at the source-end.

Xopt1ωCgsωLsE37

Note that expressions (34) and (35) represent real and imaginary terms of impedance, while (31) and (32) presents admittance expressions.

Observe from expression (36) that the imaginary term of the optimal noise generator impedance is inversely proportional to the gate-source capacitance. Since the gate-source capacitance is always positive, than noise matching can be achieved with inductive generator impedance. However, increasing Ls will reduce the gain, but at the same time, the inductive term of generator impedance (Lg) can be decreased. According to the above observation, it is clear that optimal noise condition and maximum power transfer are obtained simultaneously whenZopt=Zin_eq*, where Zin_eq is the equivalent input impedance seen by input gate of amplifying transistor given as:

Zin_eq=Rin_eq+jXin_eq=gmLsCgs+j(ωLs1ωCgs)E38

However, it is not easy to make both Zoptand Zin_eq*to have same value. Nevertheless, high gain can be achieved if the inequality shown in (38) is satisfied. Obviously, smaller resistive term of input impedance seen by gate-end leads higher gain.

Rin_eqRoptZsE39

where Zs is the source impedance.

Since the reactance term of Zoptand Zin_eq*are almost always matched according to (36) and (37), inequality (38) will force Zin_eq to be positioned in outer side of Zoptin Smith chart until the frequency exceeds the desired frequency range.

As mentioned already, the bias condition should be achieved under a limited current, thus IDS is a limited value. For the sake of simple procedure, assumed the gm and Cgs are given as (39) and (40), which ignore overlapped channel length Lov, The initial value of Veff is given by (40).

gm=μnCoxWLVeffE40
Cgs=23WLCoxE41
Veff2ZsL23LsμnE42

Note that considers minimum channel length L. Once Veff is obtained, then the minimum value of gm is:

gm2IDSVeff_maxE43

where Veff_max is the maximum effective voltage.

Assume, roughly, thatγ2,δ4andα5, since gds0.2gmin active region, so that (34) can be simplified even more as:

Ropt110ωCgsE44

Finally, the minimum channel width W given in (44), is based on (38), (40)and (43) :

W3210ωZsLCoxE45

Again, minimum channel length is assumed and the results are roughly selected so that they must be optimized later. The obtained Zopt and Zin_eq are shown in Fig. 10 over the frequency range of 100MHz to 20GHz, and one can notice that Zin_eq* is almost matched to Zopt. Zin_eq* remains positioned in outer circle of Zopt in Smith chart up to 6GHz, which is higher than the desired frequency range.

Figure 10.

Zopt, Zin_eq, and Zin_eq*.

The obtained condition so far should be applied to M1 in Fig. 9.

3.3. Miller effect in cascode topology

The Miller effect implies that the effective capacitance is increased by negative voltage gain between input and output. However, since the input impedance of the cascode device M2 is capacitive, the voltage gain is high in low frequency and low in high frequency, which implies the effective Miller capacitance will be high in low frequency and low in high frequency. Therefore, it explains that the Miller effect creates not only a single capacitor, but also an inductor in parallel with the Miller capacitor.

The input impedance ZLoad of the cascode device M2 seen at the source of M2 is described as

ZLoad=Rds2+ZL1+gm2Rds2+sCgs2(Rds2+ZL)E46

where ZL is the output load connected to drain of M2, and this is assumed as pure resistor over the frequency of interest, for simplicity.

The load impedance of the cascode device, therefore, can be expressed as R and C parallel circuit as shown in Fig 11, whose values are:

CLoad=Cgs2E47
RLoad=Rds2+ZL1+gm2Rds2E48

The resistance term of the cascode load is equal to 1/gm2, when Rds2 is infinite. Note that the Rds2 is relatively large for low power design due to the relationRds=1λIDS, where is the depletion length coefficient (channel length modulation), and IDS is the bias DC current, which is small for low power design.

Figure 11.

Input impedance of cascode device M2.

The effective transconductance for source degenerative topology can be obtained as:

Gm=gm11+gm1Lss+Cgs1Lss2E49

Thus, the overall open voltage gain Avo is:

Avo=GmZLoad=gm1(Rds2+ZL)(1+gm1Lss+Cgs1Lss2)(1+gm2Rds2+Cgs2(Rds2+ZL)s)E50

According to the non-flat open voltage gain between gate and drain of M1, the Miller capacitor is not a simple capacitor anymore, but an RLC combination circuit.

The Miller capacitance Cmil is:

Cmil=(1Avo)Cgd1==(1+gm1(Rds2+ZL)(1+gm1Lss+Cgs1Lss2)(1+gm2Rds2+Cgs2(Rds2+ZL)s))Cgd1E51

Finally, the overall Miller impedance caused by the non-flat voltage gain is:

Zmil=1sCmils2Ls(Cgs1gm2+Cgs2gm1)+s(Cgs2+Lsgm1gm2)+gm2s3Cgd1Ls(Cgs1gm2+Cgs2gm1)+s2Cgd1(Cgs2+Lsgm1gm2)+sCgd1(gm1+gm2)E52

Note that non dominant terms are eliminated for the sake of simplicity.

The equivalent impedance given by Miller effect is indicated in Fig. 12, whose values of individual components are:

Cmil1=Cgd1(gm1+α)αE53
Cmil2=Cgd1(gm1+α)gm1E54
Lmil1=Lsgm1(Cgs1α+Cgs2gm1)α(gm1+α)E55
Rmil1=gm1(Cgs2+Lsgm1α)Cgd1(gm1+α)2E56

where =1/RLoad.

Note that the resistive term Rmil1 is related to the quality factor of the inductive term Lmil1, and it is relative small enough to be ignored.

Figure 12.

Equivalent input circuit.

3.4. Modified input impedance by feedback

Now, the input impedance of the inductive degenerative topology including Miller effect must be re-evaluated.

The input impedance of the open circuit is well known as RLC series circuit, given as:

Zino=sLs+1sCgs1+gm1LsCgs1E57

From the feedback system, the modified input impedance of the feedback system, as shown in Fig. 13, is given by:

Zinc=Zino(Zf+Zload)Zino(1+Gm)+ZL+ZfE58

Note that the close loop input impedance includes the Miller effect.

The feedback impedance Zf is (1/sCgd1), which is the gate-to-drain capacitor. By using the effective transconductance and load impedance as obtained above, the overall expression of the input admittance Yinc of the close loop circuit after simplification is:

Yinc=Ymil+11Reff+sCeff+1sLeffE59

where Ymil is 1/Zmil, the admittance of the equivalent Miller circuit, and:

Reff=gm1LsCgs1(1+Cgd1Rds2+2Cgs2Rds2gm1Ls(1+gm2Rds2))E60
Ceff=Cgs1E61
Leff=Ls+βE62
β=(Rds2+ZL)(Cgd1(gm1(Ls+gm2LsRds2)+Cgs2(Rds2+ZL))+Cgs2(2gm1(Ls+gm2LsRds2)+Cgs2(Rds2+ZL)))Cgs1(1+gm2Rds2)2E63

Thus, the actual RLC series circuit is changed by the feedback effect. The feedback effect effectively increases the inductive term Leff and resistive term Reff from the original open circuit input impedance Zino.

Figure 13.

Feedback system with effective transconductance.

For large Rds2, the equivalent circuit can be further simplified as:

Reffgm1LsCgs1(1+Cgd1+2Cgs2gm2)E64
LeffLs+Cgd1Cgs2+Cgs22+Cgd1gm1gm2Ls+2Cgs2gm1gm2LsCgs1gm22E65

Therefore, overall input impedance can be expressed as Fig. 12.

Note that the Cmil1 can be ignored in high frequency and Rmil1 also can be ignored due to its small value, so that the overall circuit can be considered as the combination of parallel LC and series LC circuits. The circuit also can be considered as a part of bandpass filter.

4. Mixer

Mixers are non-linear devices used in systems to translate from one frequency to another. All mixer types work on the principle that a large Local Oscillator – LO drive will cause switching/modulating the incoming RF into an Intermediate Frequency – IF, or in opposite direction.

There are two types of mixer, passive and active. Generally the passive types have better IM3 performance, but present higher conversion losses and hence higher noise Fig.s than active mixers.

Additionally, mixers can also be classified as single balanced mixers and double balanced mixers. Single balanced mixers are much less complex, but have inferior performance in terms of RF to IF and LO to IF rejection, compared to double balanced mixers.

The advantages of double balanced mixers are:

  1. Both LO and input signals are balanced, providing both LO and input rejection at the output.

  2. All ports of the mixer are inherently isolated from each other.

  3. Higher linearity, compared to singly balanced.

  4. Improved suppression of spurious products (all even order products of the LO and/or the input are suppressed).

  5. Higher intercept points.

  6. Less susceptible to supply voltage noise due to differential topology.

The disadvantages are:

  1. Require a higher LO drive level.

  2. Require differential input and LO signal.

  3. Ports are highly sensitive to reactive terminations.

The Gilbert double-balanced mixer configuration is widely used in RFIC applications because of its compact layout and moderately high performance. This section will walk through the design of a CMOS Gilbert mixer focusing on the parameters that influence the linearity of the signal path, the noise, and therefore the spurious-free dynamic range of the mixer. Finally, some techniques to enhance the bandwidth of the Gilbert mixer will be also presented, so to be suitable for UWB applications.

4.1. Design guidelines

Depending on the application, the mixer may be designed with a low Single Side Band – SSB noise Fig., a particular gain or a high linearity. A good starting point is to use the differential LNA and add the switching transistors with the same W/L ratios.

As in the case of LNA design, the linearity of the mixer source can be increased by adding degeneration resistors (or inductors). As an example consider ZS inserted in the sources of M1 and M2 in the circuit of Fig. 14.

There are several parameters to be achieved during the design process, such as device width, biasing, linearity of transconductance amplifier (input circuit), stability, input matching network, gain compression, Inter Modulation Distortion – IMD, noise Fig. and spurious free dynamic range.

Though the design method introduced here emphasizes the distortion-limited (large-signal) performance over noise-limited (small-signal) performance, there are many design choices possible. In Fig. 14, one may have to decide proper bias current and device width W1, and W2. Proper selection of W1 should provide high gm, saturation at low VDS (for low power supply operation) and low noise. Large widths are preferred for noise, but the optimum width for both noise and power constraints can be estimated from the MOS device parameter [1]. Large widths also require large bias currents to obtain high gm. Choosing W1 = W2 is typically the best approach.

The minimum current required to keep all devices in saturation must also be considered. Additionally, once the bias is determined, the linearity of signal path must be verified. The signal path from the transconductance amplifier through the source resistance and inductance is the dominant for the sake of linearization. As the resistance increases the linearity also increases, but the conversion gain also decreases to some degree. Source inductance is used mainly to guarantee stability by forcing a positive real component into the input impedance. This also helps to make the input impedance easier to match.

4.2. Device width and bias current

From Fig. 14, the voltage gain of the mixer with source degeneration is given by:

VoutVin2π(ZLZs+1gm)E66

This equation implies lower conversion gain with larger impedance at the source of M1 and M2, as expected. However, this equation does not provide a clue to determine the device width.

From the analysis of noise optimization, the optimal width can be found as [4]:

Wopt=13ωLCoxRgenE67

where Rgen is the resistance of the source connected to the mixer input, typically 50 Ω, but sometimes determined by LNA output impedance.

For this width, IDS must be large enough to saturate the MOSFET (VDS > Vdsat). At the same time, large VDS is undesirable, specially for low VDD operation. Finally, large VDS will increase hot electron effects at the drain, thereby increasing noise.

Figure 14.

Basic circuit of the Gilbert Cell Double Balanced (DB) Mixer.

4.3. Linearity of signal path

In order to investigate the linearity of the signal path, a transfer characteristic can be simulated by sweeping the input DC voltage. Consider the example given in Fig. 15. Note that the DC input voltage VDin is Vin – Vref.

It is expected that by increasing the resistance Rs, which increases negative feedback, the transfer characteristic would be linearized, by exchanging gain for linearity. In the simulation shown in Fig. 16, it can be seen that the gain (slope) becomes more linear over a wider input voltage range as Rs is increased.

A popular technique in low voltage RFIC design is to substitute resistors by inductors. This has the advantages that the ideal inductor does not add noise to the circuit, and it reduces the supply voltage requirement for the circuit. The effectiveness of this approach is somewhat frequency dependent. At low frequency, the gain degeneration and linearity improvement for reasonable sized inductors is limited, but it becomes more effective at higher frequencies.

Figure 15.

Setup for transfer characteristic simulation.

Figure 16.

DC input voltage sweeping for linearity simulation.

Also, inductors on Si substrates have low Q, on the order of 2 to 3. For a Q of 2.5, for example, a 5 nH inductor at 4GHz would have a series resistance of about 50Ω, thus, in fact both resistance and inductance are being added to the circuit. Therefore, it is valuable to investigate the effect of both inductor and resistor as Zs.

4.4. Input impedance and stability

As explained earlier, the input impedance seen at gate of source degenerative topology with impedance Zs is:

Zin(jω)=1jωCgs+Zs+ωTZsjωE68

where ωT = gm / Cgs.

Expression (67) was derived from a simple small-signal analysis; it neglected Cgd and assumed that the node between the source resistors is at virtual ground. As summarized in Table 2, if the source noise impedance Zs is purely resistive, it is equivalent to an R and two series capacitors. If R is large, the equivalent input series capacitive reactance is large and has a large effect on Zin. The real part is clearly positive.

Similarly, a series inductance L produces a non-frequency dependent positive real part and a series LC resonant network. Only the capacitor produces a negative resistance, a condition desirable for oscillators, not mixers, and with unusual frequency dependence. Therefore, negative input resistance can be avoided eliminating the possibility of using a capacitor.

ZsRe[Zin] + Im[Zin]
RR+(ωTRjω+1jωCgs)
LωTL+(1jωCgs+jωL)
CωTω2C+(1jωCgs+1jωC)

Table 2.

Summary of input impedance according to impedance at source.

Unfortunately, however, there is some parasitic capacitance between source and bulk of the transistors, as indicated in Fig. 17. Therefore, as Rs increases, the shunt CSB effect on the source impedance increases, thus driving the input impedance negatively. If ωTRsCSB > 1, a negative real Zin will show up. For this reason, it may be necessary to add some series inductance to compensate the negative resistance.

Expression (68) describes the resistive input impedance by considering the presence of CSB.

Re{Zin}=Rs(1ωTRsCSB)1ω2Rs2CSB2E69

An extrapolation of iD - vDS intercepts the vDS axis at vDS = − VA, known as Early voltage. For a given process, VA is proportional to L, selected by the designer. Typically, VA is in the range of 5 V/μm to 50 V/μm.

4.5. Output resistance

So far, only inside of Gilbert cell mixer has been discussed. In fact, signal bandwidth at both input and output is another critical problem for UWB mixer. Therefore, input and output bandwidth enhancements are also necessary.

For integrated circuits, there is no restriction of intermediate impedance between blocks. In fact, the shunt-peaking method is widely used for bandwidth enhancement and interconnection between blocks. However, it is sometimes necessary to provide a specific impedance value for both input and output (in many cases 50 Ω), thus the wideband impedance matching methods can be applied. The applicable methods for bandwidth enhancement are:

  1. Shunt-peaking: suitable for conjugate matching with non-standard intermediate impedance.

  2. Wideband matching method: suitable for both conjugate matching and standard impedance matching, but requires more passive components.

  3. Cascode topology: applicable for both previous methods, in addition by reducing RC constant time.

Since cascode topology reduces voltage gain between gate and drain of transconductance amplifier, it reduces the effect of the gate-drain capacitance, the so called Miller effect. However, if cascode topology is applied to reduce Miller effect, one have to consider reduced overhead voltage by voltage drop through drain to source of the cascode device.

Figure 17.

Gilbert cell mixer with source to bulk capacitance.

5. Conclusions

This chapter provided the background foundations for the analysis and design of low noise amplifiers and mixers, along with their interconnections to other structures. Low noise amplifiers and mixers are among the most used structures in RF IC.

The performance of them may be compromised without proper interconnection. This chapter also presented the approaches to implement AC and DC coupling to interconnect structures, by taking into account performance and noise isolation.

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Paulo Crepaldi, Luis Ferreira, Robson Moreno, Leonardo Zoccal and Tales Pimenta (July 20th 2011). Main RF Structures, Current Trends and Challenges in RFID, Cornel Turcu, IntechOpen, DOI: 10.5772/26000. Available from:

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