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Structural Design of CMOS Voltage Regulator for Implantable Devices

Written By

Paulo Crepaldi, Luis Ferreira, Tales Pimenta, Robson Moreno, Leonardo Zoccal and Edgar Charry

Submitted: 21 October 2010 Published: 20 July 2011

DOI: 10.5772/17561

From the Edited Volume

Current Trends and Challenges in RFID

Edited by Cornel Turcu

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1. Introduction

There is a great interest in the development of equipment and devices that can accurately and efficiently monitor biological signals such as blood pressure, heart beat and body temperature, among others. It is highly desirable to have those devices operating in an environment free of wires, where the information can be accessed remotely and processed in real time by external equipments.

When the equipments are connected to communication network they form a telemedicine system by which the patients can be monitored remotely (biotelemetry), even over the internet, thus indicating the portability of these instruments (Miyazaki, 2003; Puers, 2005; Scanlon et al, 1996).

Microelectronics has become a powerful tool when used in this scenario. In recent years, integrated circuits are being fabricated with large densities and endowed with intelligence. The reliability of those systems has been increasing and the costs are lowering. The interaction between medicine and technology, as it is the case of microelectronics and biosensor materials, allows the development of diagnosing devices capable of monitoring pathogens and deceases. The design of sensors, signal conditioners and processing units aims to find solutions in which the whole system can be placed directly in the patient or, more desirable, implanted. It becomes a Lab-on-Chip and Point-of-Care device (Colomer-Farrarons, 2009). Since the implanted device becomes part of a biological data acquisition system it must meet few requirements such as reduced size, low power consumption and the possibility of being powered by an RF link, then it operates as a passive RFID tag (Landt, 2005).

The low power restriction is extremely important for the patient safety, by avoiding heating due to the increase of current density in the tissues surrounding the implant that could cause tissue damage. The power restrictions mean also limited power of RF transmitter that can, as well, to induce dangerous electromagnetic fields – EMF.

The focus in this chapter is to discuss the implementation of a Linear Voltage Regulator – LVR by considering the use of a low cost CMOS process, low-power, low silicon area and simple circuit topology.

The LVR is an ASIC structure whose electrical characteristics depend on the specific load conditions. Therefore, the idea is to discuss few structural solutions.


2. Implanted Device - Smart Biological Sensors

A typical CMOS front-end architecture of an in-vivo Biomedical Implanted Device – BID is shown in Figure 1. The system consists, basically, of the sensitive biological element, the transducer or detector element, the associate electronics and signal processors, and the RF link to establish a communication with the manager unit. The combination of the implanted device, the local wireless link and a communication network forms the Wireless Biosensor Network – WBSN (Guennoun, 2008).

Figure 1.

Typical Implanted Biomedical Device acting as a RFID Tag.

Linear systems based on semiconductor devices demand a stable power supply voltage for proper operation. Fluctuations on the input line voltage, load current fluctuations and temperature variations may cause the circuit to deviate from its optimum operation bias point and even loose its linearity. Therefore, the power supply system must experience minimum impacts on the linearity due to those variations. Nevertheless, the impact of temperature variations in implantable devices is minimized since the body temperature is kept stable at approximately 37° C (Mackowiak, 1992).

The LVR is part of the power conditioning block that is responsible to supply a stable voltage to the sensors/transducers and its associated electronics.

Unlike the general voltage regulator application, an implantable device does not suffer a large range, but it is more limited. This condition minimizes the impact of load regulation specification.

The tag operation frequency is one of the most important considerations when designing a solution to suit the requirements. The operation frequency has enormous effect on price, performance, range and suitability for RFID projects. The general bands used to broadly classify the RFID tag families are low, high, and ultra high.

The low frequency range (typically between 125 kHz and 134 kHz) is most commonly used for access control, animal tracking and assets tracking. It offers low cost.

The high frequency range (typically 13.56MHz) is used for medium data rate transfer and reading range of up to 1.5 meters, usually for passive tagging. This frequency has also the advantage of not being susceptible to interference from the presence of water or metals. Since the user of an implantable monitoring system is exposed to a RF source near the skin, few safety considerations must be taken into account. The main biohazards and risks due to the RF exposure is mainly the heating from the electromagnetic field distribution on biological tissues (Osepchuk, J.M. & Petersen R. C., 2001). This frequency provides a good tradeoff between power level and human tissue penetration (Sauer, 2005; Vaillantcourt, 1997).

The ultra high band (typically between 850MHz and 950MHz) offers the largest reading ranges, of up to approximately 3 meters for passive tags and 100 meters for active tags. Relatively high reading speeds can be achieved at that band.


3. The topology of a voltage regulator

Classic topologies used in voltage regulators can be classified as linear or switched. Switched regulators present complex circuitry, mainly due to control unit, thus frequently requiring larger power consumption and larger silicon area. Furthermore they provide larger noise at the output due to the switched operation (Rincon-Mora & Allen, 1997).

Low dropout – LDO voltage regulators is one of the most popular power converters used in power management and is more suitable for implanted systems (Rincon-Mora, 1998, 2000). The basic topology of an LDO is presented in Figure 2.

Figure 2.

Basic LDO topology.

The pass element can be implemented using bipolar or MOS transistors. Since a MOS transistor is controlled by its gate voltage, it offers the advantage of smaller power consumption and consequently higher efficiency for the voltage regulator. The MOS transistor can be either N or P type. The NMOS transistor requires a gate voltage higher than the source voltage, and therefore it may be necessary a charge pump to increase the voltage level. The proper choice for low voltage systems, such as implantable devices, it is the use of a PMOS LDO, as indicated in Figure 3 (Kugelstadt, 1999; Simpson, 1997). A NMOS LDO without charge pump is reported in (Ahmadi & Jullien, 2009) using native transistors (zero threshold) and an internal capacitor to improve the stability, but two external capacitors are required.

Figure 3.

PMOS based LDO.

Figure 4.

Classic PMOS LDO with discrete frequency compensation scheme.

The closed loop system output voltage can be found to be:


The use of an LDO circuit requires the stability analysis since it forms a closed loop system. The frequency response is degraded by the presence of two poles besides the dominant pole that can lead to an unstable condition. It is necessary to add a zero between these two poles to achieve a frequency compensation. The insertion of this zero is normally implemented by adding a discrete electrolytic capacitor (Ccomp) at the output node that also contributes with an additional resistance Resr, as represented in Figure 4. Additionally, Rota is the output resistance of the transconductance amplifier, Cgpass is the gate capacitance of the PMOS pass transistor and Rds is the channel resistance of the PMOS pass transistor.

The frequencies of these poles and zero are given by (Rogers, 1999):


Equation (1) shows that the dominant pole frequency depends on the drain-source resistance, which in turn depends on the drain current. As a consequence, the dominant pole can change its position according to the load. To overcome this situation, the zero must follow the pole. It is common to establish not just a single value for Resr but a range of values as a function of load current.

Figure 5.

Frequency response of a PMOS LDO regulator with external compensation capacitor PMOS based LDO.

Figure 5 presents the frequency response of a PMOS LDO. Unfortunately, the use of an external capacitor, such as an electrolytic capacitor, is prohibitive for an implantable device. Thus, the literature provides many contributions to solve the LDO stability problem. Few approaches maintain the external capacitor and modify the internal feedback loop by using buffers (Stanescu, 2003) and Miller compensation capacitor (Huang et al, 2006). Other approaches insert and internal zero, discarding the compensation capacitor, by using controlled sources and even Miller compensation (Huang et al, 2006).

Load Conditions: IL = 500μA, CL = 5pF

Table 1.

Table 1. LVR target values for an implanted blood pressure monitoring system.

A lower value of 200mV was adopted to provide a wider range of output values, as stated by eq. (1) ** A safe value for the RF link power transfer is 10mW/cm2 (Lazzi, 2005). The LVR power dissipation should be taken as just 10% of it, corresponding to 1mW, which represents twice as much as required by the load (0.5mW). Reported voltage regulators for implanted devices list a power dissipation range that can be as high as tents of mW (Zheng & Ma, 2010).

Figure 6.

LVR architecture.

The solution proposed here is the introduction of a source follower (MNFOL) stage in between the input voltage and the LDO block, and the removal of the compensation capacitor Ccomp, as shown in Figure 6. The source follower maintains the PMOS pass element in the triode region, which leads to an unconditionally stable system, as it will be described later.

The introduction of the extra source follower represents a disadvantage since it introduces extra power consumption and requires additional silicon area. The overall efficiency is also affected, nevertheless the advantages overpasses de disadvantages, mainly for implanted devices.

Table 1 shows the target values for a project example. The load is an implanted physiological signal system that is used to monitor the blood pressure.


4. Frequency response analysis

The frequency analysis of the LVR can be evaluated by finding initially the open loop gain (Aβ) Figure 7. The originally closed loop is broken at a particular point, and the loop gain is given by:


Figure 7.

Feedback broken to analyze the open loop gain.

In Figure 8 the OTA and the pass transistor (MPPASS) are replaced by the small signal model.

Figure 8.

Small signal equivalent circuit of the LVR

The total load resistance is minimized by the low value of rds, therefore the drain-gate voltage gain of MPPASS is:


The output voltage is:


Considering that rid is much larger than R2, then vr is:


By combing (7) and (8), the loop gain is:


It can be observed from Equation (9) that the feedback gain β is R2/(R1+R2). It is compatible with Equation (1) that states the relationship between VOUT and VIN is given by the factor 1/β.

The poles p1 and p2 are:


Pole p2 is the dominant one since rota is in the range of MΩ and can be at least 105 times larger than rds, which is the range of tens of Ohms. So the frequency stability of the regulator is a function of the OTA design, the geometric aspect ratio of MPPASS and the load. As an ASIC application, the load current (IL), resistance (RL) and capacitance (CL) can be stated as constants without impacting in the pole frequencies. The OTA output capacitance CO can be neglected since the PMOS pass transistor has a larger geometric aspect and, consequently, larger Cgs and Cgd.

Equation (9) shows that at low frequencies (DC), the gain A is given by:


Considering typically gm in the range of 10-3 [V/A], tens of Ohm to rds and 106 Ohm for rota, than the gain is greater than 40 [dB]. The dominant pole will have a frequency in the range of tens of Hz and the unit frequency gain in the range of hundreds of KHZ.


5. The sampler circuit

Figure 9.

Sampler Circuit for the LVR.

Figure 9 presents the sampler circuit. In order to implement the whole circuit in a single CMOS chip, R1 is realized as a MOS diode (transistor MN2) and R2 is implemented through an interesting topology, a grounded MOS resistor (Dejhan, 2004). The use of the source follower transistor MNAUX guarantees that the grounded MOS resistor is isolated from VIN, thus avoiding a significant transference of ripple voltage to the output voltage. MNAUX also imposes a smaller effective voltage to the MOS resistor, thus reducing the sampler current.

The power supply voltage of the sampling circuit (PMOS array) is reduced by approximately 1V, thus settling VRES to 1.2V. This is important to reduce the ground current and to maximize the LVR efficiency and improving the overall power dissipation. The relationship R1/R2 is optimized by the adjustments of the aspect ratio of transistor MN1 and MN2.

The sampler circuit current IRES is designed to be ≈1% of the maximum current load (≈ 5μA). The voltage at point A is virtually VREF, due to the OTA virtual short circuit. Therefore, the R1 equivalent resistance is given as:


The aspect ratio of MN1 was adjusted in order to set IRES as close as to the target value of 5μA. So, R1 (transistor MN2) will be adjusted as a 160KΩ resistor.

The additional capacitances introduced by the grounded MOS resistor and MN2 are smaller enough so that can be discarded in the previous frequency response analyses. All those transistors have small source and drain areas leading to capacitances in the range of fF. The eventual poles will be far away from the dominant one and the unit frequency gain.


6. The voltage references

On designing any system that requires a voltage reference, the temperature and power supply sensitivity must be taken into account.

Classical voltage references are based on the bandgap voltages, where two distinct voltages with opposite thermal coefficients (PTAT and CTAT) are summed to obtain an overall near zero coefficient. Besides, their bias circuits must be robust to guarantee a low sensitivity to the power line fluctuations. The bandgap voltage is about 1.12V for silicon at room temperature (Tzanateas, 1979).

Nevertheless, the evolution of fabrication process is pushing down the supply voltages. For instance, it is about 1.2V for a CMOS 0.13μm process. So there is a demand for new voltage references topologies to produce values bellow the classical bandgap value of 1.2V.

A literature revision shows the trends into this challenge (Koushaeian & Skafidas, 2010). However, these contributions show one or more of these aspect: complex circuits topologies with an elevated number of components, the need of special components that are not ready available from the CMOS common process, the need of trimming procedures, use of external components and use of MOS transistors that are not operating in classical modes. An alternative mode is the weak inversion in which the MOS transistor behavior approaches the bipolar ones.

6.1. Current mirror core

The core to produce the voltages references are the self biased current mirror illustrated in Figure 9. The use of a parasitic vertical PNP bipolar transistor Q1 in a CMOS digital technology is justified since it presents known VBE voltage and temperature behavior. The temperature does not represent the main impact factor since the whole system will be implanted.

Equations (12) and (13) are the starting point to establish the values of the currents IE and ID. The currents values are set to approximately 5μA (1% of maximum load current) in order to improve the LVR overall efficiency.


where KP is the MOS transconductance given in [μA2/V], δ is a dimensionless fitting parameter for short channel devices, (W/L) is the geometric aspect ratio, Vth0 is MOS the threshold voltage given in [V], ICS is the bipolar saturation current given in [nA] and UT the thermal voltage that is about 26.7 [mV] at 37ºC.

Figure 10.

Self biased current mirror.

Figure 11.

Simulated results for the mirror currents @ T=37º.

There is no closed solution for both equations and it is necessary to develop an interactive simulation process to reach the optimum result for Id, which is equal to Ie. The target value for these simulation is the geometric aspect ratio of the MOS transistors, since it is used a vertical PNP bipolar with a 100μm2 emitter area. To minimize the short channel effects, the channel length was fixed to 1μm for MN1 and 2μm for MP1 and MP2 to improve the mirroring matching. The PMOS geometric aspects are also optimized by simulation.

Figure 11 shows the simulated currents for an input voltage variation of ±10% around to the ideal value of 2.2V. The temperature was fixed in 37 ºC.

The relative error between the mirror currents, at the ideal operating point of VIN=2.2V, can be calculated as:


It is important to evaluate the power supply dependence of those currents. The sensitivity is an adequate parameter to measure it and is given by (Gray & Meyer, 1993):


The derivative term can be found directly from the circuit topology to be:


where λn is the channel length modulation coefficient that is obtained by simulation and Vth0(N) is the NMOS threshold voltage. Substituting (17) in (16) leads to:


An alternative way to evaluate the current sensitivity is by using Figure 11. The following equation offers a derivative approximation. It considers the variation of Id due to variations on VIN:


Table 2 resumes the calculated and simulated results for the current sensitivity.

Consequently, for ±10%variation in VIN around the quiescent value, the mirror currents will change approximately ±3%. Simulations results also point out that for the voltage references circuits discussed next, than Veb voltage will play an important rule and suffers a 1.8 [mV] variation for the entire VIN range, representing a deviation of ±0.13% from the 676 [mV] quiescent value. It indicates a power line rejection rate – PSRR better than 45 [dB] at low frequencies.

Body Temperature: 37ºC
VINQ=2.2 [V]VINQ=2.2 [V]
IdQ=5 [μA]IdQ=4.4 [μA]
-λn=0.096 [V-1]
Veb=680 [mV]Veb=676 [mV]
-Vth0(N)=523 [mV]*
SVINIdEq. (19) = 0.316SVINIdEq. (20) = 0.331

Table 2.

Table 2. Id sensitivity: calculated and simulated values

The threshold voltage value was indicated by a CMOS process.

6.2. The start up circuit

As a self biased circuit, the current mirror core needs a start up circuit to ensure the correct operating point. It is implemented by the circuit shown in Figure 12.

Figure 12.

The start up circuit added into the self biased current mirror.

CSTART and C1 are small capacitors (0.5pF) and MSTART is a PMOS transistor, similar to those used in the current mirror. When the circuit is energized, assuming that the capacitors are discharged, the Vsg of MSTART is greater than its threshold voltage. This will cause a transitory current to flow into Q1 leading the system to desired operating point. At same time, CSTART is charged toward VIN reducing the Vsg of MSTART and, consequently, turning it off. Figure 13 shows a simulating that validates the described action. The transitory current spends only 20 [ns] that is very low for a biomedical application.

Figure 13.

The Start Up transient current.

6.3. VREF voltage reference

The topology presented in Figure 14 is used to generate the VREF voltage reference. The target value for this reference is 200 [mV] as discussed previously. The current Id is mirrored to the composite transistor (Ferreira & Pimenta, 2006) formed by MNREF1 and MNREF2. The gate bias comes from Q1 collector and represents only a capacitive charge for the current mirror core since the gate currents are virtually zero. This capacitive effect contributes to improve the Veb PSRR.

It is important to observe that the composite transistor exhibits different modes of operation for each transistor. MNREF2 has a nominal Vgs2 voltage of 676 [mV] leading to strong inversion operation since Vth0(N) is approximately 523 [mV]. However, voltage Vgs1 of transistor MNREF1 is subtracted by 200 [mV] (the target output voltage). Thus, the effective value of Vgs1 is 476 [mV], leading it to operate in weak inversion.

The adopted geometric aspect of MNREF2 is similar to current mirror transistor MN1, W=2μm and L=1μm. It is necessary to evaluate the ideal geometric aspect of MNREF1 to guarantee the reference voltage of 200 [mV].

By equating the drain current of both NMOS transistors of the composite topology, then:


where IX is the weak inversion characteristic current and n the weak inversion coefficient. In the strong inversion, the term (1+λnVREF) can be approximate to unity. Note that the MNREF1 threshold voltage is presented as Vth(N) since it suffers from body effect.

Solving the equality for VREF:


Equation (22) shows that VREF can be adjusted by the geometric aspect of MNREF2 considering that all other parameters are assumed constant under the corporal temperature.

Using interactive simulation, with VIN=2.2V, the optimized geometric aspect ratio is 173. To improve the reference PSRR, the channel length of this transistor is doubled to 2 [μm].

Figure 14.

The topology used to generate de voltage reference VREF

6.4. VREF sensitivity

Using a similar concept discussed in section 4.1, the VREF sensitivity, related to the input voltage VIN, can be expressed as:


The derivate term can be evaluated directly from the circuit topology as:


Combining equation (23) and (24) and using the known values, the VREF sensitivity is 0.0415. Thus, for a ±10% variation in the input voltage VIN, VREF suffers just ±0.415%. Figure 15 shows the simulation result of those variations. As can be observed, the nominal values for VREF and VIN are, respectively, 200 [mV] and 2.2 [V]. Using this simulation to evaluate the sensitivity, results in:

SVINVREF=2,2200.103ΔVREFΔVIN=111,6.103440.103 0.04[]E25

Those results lead to a PSRR better than 40 [dB] at low frequencies.

Figure 15.

Simulation of VREF variations due to VIN

6.5. VBIAS voltage reference

Figure 16.

Three stacked bipolar transistors used to generate VBIAS voltage reference.

The circuit used to generate the VBIAS is illustrated in Figure 16. The use of three stacked bipolar transistors generate a voltage of ≈ 2 [V], i. e. 3 times the quiescent value of Veb (676 [mV]). The bias currents for Q2, Q3 and Q4 are mirrored from the current mirror core with unity gain.

6.6. VBIAS sensitivity

The VBIAS sensitivity can be derived from the circuit topology. It is interesting to evaluate, at first, the Veb for Q1 transistor. The final result for VBIAS will be three times larger. These formulations are:


For the know values, the VBIAS sensitivity is calculated as ≈0.012, leading to a variation of ±1.2% for a variation of ±10% at the input voltage line VIN.

6.7. PMOS pass transistor and NMOS follower geometric aspect ratios

Figure 17.

Circuit used to optimize the MNFOLL geometric aspect ratio.

Figure 17 shows the main current and voltages values used to estimate MPPASS and MNFOLL geometric aspects.

For MPPASS transistor, two considerations are important. First, its geometric aspect must be larger enough to support the total nominal load current plus the sampler current. Second, its operation must be kept in the triode region to guarantee a low rds value. In the triode region, the resistance is given as:


The aspect ratio (W/L) design parameter should be raised to lower the drain-source resistance. Figure 17 also shows a suggested 50 [mV] (VDROP) in order to keep the low dropout concept in the LDO circuitry. The VROP voltage corresponds to Vsd voltage in Equation (28).

By replacing MNFOLL transistor by a 5.05 [μA] current source, interactive simulations lead to a MPPASS geometric aspect of 2500/1. In order to evaluate the aspect ratio of MNFOLL it must be noticed first that MNFOLL suffers from body effect and its threshold voltage is corrected by using:


By using this result in the drain current equation, the MNFOLL geometric aspect is given as:


6.8. PMOS pass transistor and NMOS follower capacitances

Those two transistors (MNFOLL and MPPASS) have a large geometric aspect ratio leading to relative large gate capacitances. The PMOS pass transistor gate capacitance is important since it is responsible to determine the OTA dominant pole.

The NMOS and PMOS SiO2 thickness (TOX) can be used to obtain the gate capacitances per unit area as:


As the PMOS pass transistor operates in the triode region, the gate to source and gate to drain capacitances are:


7. The Operational Transconductance Amplifier (OTA)

Figure 18.

Operational Transconductance Amplifier (OTA).

There are some features that must be taken into account in order to design the OTA:

  1. To validate the closed loop properties, the OTA must have an open loop gain larger than 1000 (60 [dB]);

  2. Since the OTA is powered by the input voltage VIN, it must exhibit a good power supply rejection ratio. A target value of 40 [db] is used as a reference;

  3. The OTA must have a low offset voltage. The offset voltage has a direct impact in equation (1) and can deviate from the nominal output voltage. A target value of 5 [mV] was adopted. It is very important to observe the matching on the OTA stage to minimize the systematic offset and the use of layout technique to minimize the random offset;

  4. The total quiescent bias current must be kept as low as possible to improve the OTA overall efficiency. A target value of 3 [μA] was adopted, representing less than 1% of load current. As the OTA has three currents branches, it is assigned a current of 1 [μA] to each one;

  5. The dominant pole discussed in the previous sections is a function of the OTA output resistance;

  6. The OTA frequency response must lead to a stable system over the entire band. A margin phase of 70 degrees is a target value.

  7. The OTA does not need fast responses due the physiological application. The slew rate and settling time targets are, respectively, 0.1 [V/μs] and 10 [μs].

One recommended topology is the folded cascade. It offers high output resistance and, as in this particular case, the dominant pole is fixed by the capacitive load. This is important to reduce the silicon area and extra power consumption by using additional compensation circuits.

It is used the self biased Operational Transconductance Amplifier – OTA topology (Mandal & Visvanathan, 1997). It provides additional reduction of silicon area and power consumption by using other biasing circuits. The OTA circuit is depicted in Figure 18.

As can be observed, the OTA has a rail-to-rail input stage. It is not absolutely necessary in this project, but it is interesting to have the possibility to generating output voltages near the rail lines VIN and Ground. The OTA can be suitable for other applications that require different input voltage values.

The OTA open loop gain is:


where gmN and gmP are the NMOS and PMOS input differential pair transconductance, respectively. In the case of general purpose application, it should be used an additional circuitry to compensate their transconductances since they exhibits different values depending on the region of operation.

In this project, the gm variations, that can be as large as 100%, do not have a significant impact on the LVR stability. The dominant pole is far away enough from the other poles by several orders of magnitude.

7.1. OTA transistors geometric aspect

Figure 19 shows the lower half cascode from Figure 18 and the quiescent output voltage of 1.1 [V].

That voltage is considered split equally between the two NMOS transistor pairs. Observe that it is necessary to consider the total NMOS tail current IN for MN6,7. Using Equation 14:


Figure 20 shows the PMOS and NMOS differential voltage considerations.

Figure 19.

Lower half used to evaluate the geometric aspect ratios.

Figure 20.

NMOS and PMOS differential input pairs.

For transistors MN1,2 it is necessary to consider the threshold voltage correction since they suffer from body effect and operate in weak inversion.


Therefore, by using the current formulation, then:


NMOS transistors MN4,5 operate similarly to MN1,2. The only difference is they carry half of tail current. Thus, the geometric aspect of these transistors is divided by 2 (37). All PMOS transistors have their geometric aspect ratios adjusted by interactive simulations. Table 3 resumes OTA aspect ratios where the channel length and width are expressed in [μm].

Corporal Temperature: 37ºC
(W/L)MN1 = (W/L)MN274/1
(W/L)MP1 = (W/L)MP2158/1
(W/L)MN3 = (W/L)MN6 = (W/L)MN714/1
(W/L)MN4 = (W/L)MN532/1
(W/L)MP3 = (W/L)MP4 = (W/L)MP5158/1
(W/L)MP6 = (W/L)MP7272/1

Table 3.

OTA geometric aspect ratios, in [μm]

7.2. OTA simulations results

Figure 21.

OTA common mode range indicating a rail-to rail operation.

The following figures show the most relevant OTA parameters simulations. The common mode range – CMR is depicted in Figure 21. The OTA is buffer connected and the input signal is linear over the entire range, thus characterizing a rail-to-rail operation. The OTA analog ground is 1.1 [V] and the simulation shows that the systematic offset is minimum, thus representing a good matching between the OTA stages.

Figure 22 shows a configuration to analyze the OTA frequency response. The auxiliary capacitor and inductor (CAUX, Laux) guarantees a closed loop for DC signal and an open loop for AC signal. Thus the OTA will be properly biased since the DC path configures a buffer connection.

Figure 22.

Buffer configuration used to simulate the OTA frequency response.

Figure 23.

OTA Frequency response.

The load capacitance CL is represented by the PMOS pass transistor gate capacitance, evaluated according to Equation (32). The dominant pole (P2) is located at ≈130 [HZ] and the unit frequency gain (fU) is located at ≈640 [KHZ]. The phase margin (ΦF) is ≈66 . Figure 22 show these results.

On a buffer configuration, the OTA is excited by a square wave to obtain the transient parameters. Figure 23 shows the resultant simulation considering a fluctuation of approximately ±10% around the 1.1 [V] analog ground. That simulation can be used to obtain the falling and raising slew rates (SR) and the settling time.

Figure 24.

OTA transient response.

Table 4 resumes the main parameters obtained from the interactive simulations.

Corporal Temperature: 37ºC
Input Voltage Supply: 2.2 [V]
IDD [μA]3,5
PD @ IDD [μW]7,7
CMRVSS+100 [mV]
VDD – 100 [mV]
OTA dominant pole [HZ]130
fUG [MHz]0,64
ΦM [0]66,6
TSET @ 0,1% [μS]
raise and fall
SR+ e SR- [V/μS]0,2
PSRR @ 100HZ [dB]-81
PSRR @ 10MHZ [dB]-26,5

Table 4.

OTA main parameters.


8. Layout considerations

Even by using the most advanced microfabrication techniques, it is not possible to guarantee that all the devices implemented in the same chip will have the same electrical characteristics. The aspect ratio of two similar devices can be controlled to a precision of approximately ±1% and, in the many cases, it can be better than ±0.1%. Therefore, the layout project of an integrated circuit, mainly analog application fields, must take mismatches into account (Shyu, 1984).

The layout, as a backend step, plays an important rule to fabricate matched devices in the integrated circuit. It is not possible to cancel the mismatch completely; nevertheless there are ways to minimize it.

The objective of component matching is to reduce the error introduced by the deviations in the fabrication process; therefore it is necessary to use layout techniques.

The mismatch can be classified as systematic and random (Ramos, 2007). The main sources of systematic mismatch are the process polarization (difference between the designed dimensions and actual dimensions), contact resistances, non-uniform current flow, interaction between diffusions, temperature gradient and stress gradient.

As an example, the silicon presents stress gradients, meaning that is a piezoresistive material and presents variation in its characteristic resistance due to mechanical stress. This gradient can be represented by isobaric lines along the die that show the different levels of intensity. It is minimum in the central region and maximum along the four corners. Figure 24 shows an example of those isobaric lines.

Figure 25.

Example of isobaric lines.

Consequently, it is recommended that components to be matched are placed near to each other to minimize the mechanical stress. The mechanical stress difference between two matched components is proportional to the stress gradient and their distance. For calculations purposes, the location of the component is determined as the average contribution of each section of the component as a whole. The resultant location is called centroid of the component. It is important that any symmetric axis crosses the centroid of the device or component. Some examples of centroid configurations are depicted in Figure 25.

Figure 26.

Examples of centroid layout configurations.

The effects of mechanical stress in integrated resistors are quantified in terms of piezoresistivity, position of the centroids and stress gradients. These effects can be minimized by the proper choice of a low piezoresistivity material or by the resistor orientation in the wafer according to the minimum stress gradients. Other recommendation is the reduction of the distance between the centroids.

The temperature gradients can be analyzed in the same way as the stress gradients. Temperature gradients are obtained by isothermal lines and are separated from each other by a predefined temperature difference (ΔT). These temperature gradients are maximum around the perimeter of the component, and gradually, decrease towards the center.

The temperature effects are minimized in a similar way as the stress gradient: by using low linear temperature coefficient, by using minimal lines of the temperature gradient and by reducing the distance between the centroids.

Mainly for analog integrated circuits, the layout of two matched components is usually implemented by dividing each component into identical sections, placed symmetrically in a matrix array.

The common centroid layout, along with matched components placed in a matrix array in identical and symmetrical sections, is essential to reduce or even eliminate the systematic mismatching. Since the distance between the centroids is null, the mismatching caused by mechanical and temperature stress will be null. As an example, transistors on differential pair are placed in a cross coupled pattern.

In order to properly generate centroid layout, some rules must be observed (Hastings 2001):

  1. Coincidence: Matched devices must have a common centroids or as close as possible;

  2. Symmetry: The component matrix must be symmetrical in both X and Y axis. Ideally, the symmetry must be a consequence of the components placement and not the symmetry of each one individually;

  3. Dispersion: The matrix must offer the greatest dispersion level, in other words, each component must be placed with high possible symmetry along the matrix array;

  4. Compression: The matrix should be as compact as possible, ideally close to a square shape.

The random mismatch is different on each device and it is caused by microcospical irregularities in the materials or fabrication process. It can be reduced using the proper geometric aspect of the matched components. This geometric aspect is based in physical and statistical models that are characterized by the fabrication process Patrick & McAndrew, 2003).

Physically, the microscopic irregularities results from the material granularity (ex. polysilicon), photolithography errors, doping injections, thickness and permittivity of the gate oxide, etc. The effect of those errors may decreased as the components geometric aspect increase, since these parameters reach averaged values for large widths and areas.

Two parameters are considered in order to model the random mismatch: the process and the electrical parameters. Process parameters are physically independent and control the device electrical characteristics. In the case of a MOS transistor, the process and electrical parameters that have must be taken into account to matching purposes are listed in Table 5.

Process ParametersElectrical Parameters
Flat band voltageDrain current
MobilityGate-Source voltage
Substrate Doping ConcentrationTransconductance
Chanel length variationOutput resistance
Chanel width variation
Short channel effect
Narrow channel effect
Gate oxide thickness
Source/Drain sheet resistance

Table 5.

Process and electrical parameters for component matching.

A CMOS process allows also the fabrication of bipolar transistors. Those transistors are also subject to matching rules. A lateral bipolar transistor does not have a good matching when compared with a vertical one. The poor matching of the lateral transistors are due to the surface effects and impossibility using large emitter areas.

Some rules for bipolar transistor matching are:

  1. Identical geometric aspects for the emitter and collector since they affect the current flow in lateral transistors;

  2. Minimum emitter area for matched transistors, otherwise there will be a degradation in the current gain (β);

  3. Guard ring around the base to ensure that electrostatics charges will not influence the current flow in the neutral base;

  4. Use of multiple collectors for lateral PNP transistors. A moderate match can be reached when the collectors are identical and out of the saturation condition;

  5. The matched transistors should be close to each other in order to minimize the impact of the thermal gradient.

  6. The matched transistors should be placed in gradients lines of minimum stress;

  7. The transistor must be aligned with the wafer axis;

  8. Place as many metal contacts as possible in the emitter (following the emitter geometry) to reduce the contact resistance and to distribute the current flow uniformly;

  9. Use emitter degeneration. Lateral PNP transistors are often more benefited with emitter degeneration compared to the NPN vertical counterparts due to the Early voltage and the large emitter area. They are commonly used in current mirrors.

The matching over integrated components reflects the overall performance of the entire circuit or system. Depending on the matching accuracy, the circuits may present:

  1. Minimum: In the range of ± 1% (representing 6 to 7 bits of resolution). Used for general use components in an analog circuit, such as current mirrors and biasing circuits;

  2. Moderate: In the range of ± 0.1% (representing 9 to 10 bits of resolution). Used in bandgap references, operational amplifiers and input stage of voltage comparators. This range is the most appropriate for analog designs.

  3. Severe: In the range of ± 0.01% (representing 13 t0 14 bits of resolution). Used in high precision analog to digital converters (ADCs) and digital to analog converters (DACs). Analog designs that use capacitors ratio reach this range easer then those that using resistors ratios.

Figure 26 shows an example of a PNP vertical bipolar transistor layout.

Figure 27.

PNP vertical bipolar transistor example.


9. LVR measurements

The example LVR was diffused in a 0.35μm standard CMOS process. It took an area of approximately 0.25 [mm2].

Figure 27 depicts the testing structure utilized to measure the main LVR parameters.

It is used a commercial operational amplifier (LM318) as a buffer to isolate the chip. The load current can be adjusted by potentiometer P1 and the total load capacitance, considering the all parasitic, was measured as 30 [pF].

Before any LVR measure, the LM318 offset voltage was compensated through the procedure provided by the manufacturer. All the power supply lines are decoupled by 10 [μF] capacitors.

Figure 28.

The test structure to measure the LVR parameters.

VOUT 1[V] @ IL = 0.5mA1.038[V] @ IL = 5[μA]
1.004[V]@ IL = 0.5[mA]
IQ30[μA] 39[μA]
PSRR @ 10MHZ-42.6dB -38dB
EFF related to VIN42.8[%]42.3[%]
TSET @ 0,1%14.87[μs]18.6[μs]
OTA dominant pole130[HZ]126[HZ]

Table 6.

Main LVR simulated and measured parameters.

Figure 28 shows the LVR response to a voltage step input and reveals a BIBO (bounded input – bounded output) system, in other words, the system is unconditionally stable and there is no need of any extra external component.

Table 6 is a comparison between the simulated and measured parameters.

Figure 29.

LVR step response indicating a BIBO system.

The measured values show a good conformity with the simulated ones indicating proper design considerations.


10. Conclusions

We are witnessing the great revolution that has been imposed since the manufacture of the first bipolar transistor in the late 50s of the twentieth century. Electronics solutions are going to microelectronics and microelectronics is evolving to nanoelectronics. All these developments bring with them the yearning of the human being to access more efficient equipment. So, in virtually all branches of activities we will find what is called "High-Tec".

Medicine and its related sciences could not stay apart from this explosion of technology and intelligently sought the partnership with this powerful tool for circuit design.

Some solutions point to implantable systems (which would reduce the use of invasive techniques) that can be taken up on an outpatient basis and connected into a means of communication for a distance evaluation by a health professional.

The main objective of this chapter was the development of a voltage regulator for implantable applications. Some boundary conditions allow classic Figures of Merit, such as the temperature dependence, to be less severe, since the body temperature is kept constant. Another key issue was to search for solutions that avoid the presence of any external component. This is an essential boundary condition since the topology of classical LDO regulators depends on the presence of a capacitor (usually electrolytic and therefore too large for this application) connected in parallel with the load. Other regulators reported in the literature uses complex circuits or circuits that requires large silicon area.

The circuit described is a compromise of additional power dissipation in the source follower stage and unconditional stability. Even with the additional dissipation, the total power of the regulator (about 1.2 [mW]) is within a safe limit.


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Written By

Paulo Crepaldi, Luis Ferreira, Tales Pimenta, Robson Moreno, Leonardo Zoccal and Edgar Charry

Submitted: 21 October 2010 Published: 20 July 2011