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Rf CMOS Background

Written By

Tales Pimenta, Robson Moreno and Leonardo Zoccal

Submitted: 09 November 2010 Published: 20 July 2011

DOI: 10.5772/20663

From the Edited Volume

Current Trends and Challenges in RFID

Edited by Cornel Turcu

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1. Introduction

The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) (or just MOS) is widely used and presents many advantages over the bipolar transistors (BJT) in many applications.

It requires less silicon area and its fabrication process is relatively simpler. It is possible to implement most analog and digital circuits using almost exclusively MOS transistors. All these properties allow packing a large number of devices in a single integrated circuit.

Additionally, and most important, its operation requires less power, making it extremely suitable to RFID circuits.

This chapter aims to provide background on MOS transistors, from its physical operation to modeling, including RF modeling. The basic knowledge is essential to analyze and to design RFID circuits implemented using CMOS transistors. The chapter also presents noise analysis which is essential to low voltage signal, as it is the case of RFID circuits.


2. Physical CMOS operation

Fig. 1 shows the physical structure of the n-channel MOS transistor, or just nMOS transistor. The transistor is fabricated in a p-type silicon substrate. Two heavily doped n-type regions, indicated as n+, are created in the substrate and will act as the source and drain (in terms of structure, source and drain can be interchanged). A thin layer of silicon oxide (SiO2), of thickness tox (typically between 2 and 50 nm), is formed on the surface of the substrate, between the drain and the source regions. The silicon oxide is an excellent electrical isolator. Metal (or polysilicon, which is conductor) is deposited on top of the oxide layer to form the gate electrode. Metal contacts are also made in the source and drain regions, in addition to contact to the bulk, also known as the substrate or body. Therefore, the four contacts were formed: D-drain, S-source, G-gate and B-bulk.

The gate region has a length L and a width W, which are two important design parameters of the MOS transistor. Usually L is in the range of 0.1μm to 3μm while W is in the range of 0.2μm to 100μm.

There is also the p-channel MOS transistor, or just pMOS transistor, in which the dopings are reversed to the nMOS transistor.

2.1. Forming the channel

As can be observed from the Fig. 1, the substrate forms pn junctions with the drain and the source. In normal operation both junctions must be kept reverse-biased, or at least out of the

Figure 1.

Physical structure of an nMOS transistor.

forward condition all the time. Since the drain is biased at a positive voltage, it is only necessary to connect the bulk to the ground in order to keep both junctions cut off.

With no bias applied to the gate, there are two back-to-back diodes between drain and source, and consequently, there is no current. This is true since each pn junction forms a diode. In fact, the resistance between drain and source under this circumstance is in the range of 1012Ω.

When a positive voltage is applied between gate and source - vGS, holes (which are positively charged) are repelled from the surface of the substrate. As the voltage increases, the surface becomes completely depleted of charge. The voltage at which this occurs is known as threshold voltage – Vt.

If vGS is further increased, electrons (which are negative charges) accumulate near the surface, under the gate, and an n region is created, thus forming a channel between drain and source, as indicated in Fig. 2. The channel was formed by inverting the substrate surface from p type to n type. Fig. 2 also shows the depletion region that forms around the channel and the two junctions.

Figure 2.

nMOS with an induced channel.

The symbols for the nMOS transistor are given in Fig. 3, although other symbols may be found in the literature. The symbol in Fig. 3.a corresponds to the four terminal connection, and the symbol in Fig. 3.b corresponds to the three terminal connection, where source and substrate are shorted.

Figure 3.

Symbols for nMOS transistor; (a) four terminals and (b) three terminals.

2.2. Triode condition

Now, if a very small voltage vDS is applied between drain and source, as indicated in Fig. 4, there will be a current flow through the channel. The current through the channel, named drain current - iD is directly dependent on the voltage vGS and the voltage vGS. If vGS increases, the channel becomes deeper and more current can flow. If vDS is increased, based on Ohm`s Law, there will be more current, since the channel behaves as a resistance. If follows that the transistor is operating as a linear resistance whose value is controlled by vGS. The resistance is very high for vGS ≤ Vt and it decreases as vGS increases.

This condition of operation is known as ohmic, linear or triode.

Figure 4.

Conduction under very small vDS.

2.3. Saturation condition

As vDS increases, the difference vDSvDS becomes smaller at the edge between the gate and the drain diffusion, and therefore the channel becomes shallow. Therefore, the channel assumes a tapered shape, as indicated in Fig. 5. Since the channel becomes smaller at the drain end, its resistance increases, and therefore, the transistor does not operate ideally as a linearly controlled resistor.

Figure 5.

Conduction under 0 < vDS < vGS - Vt.

At the condition vDS = vGS - Vt, the channel ceases to exist at the drain side, as shown in Fig. 6. This situation is known as pinch off. At this point, further increases in vDS moves the end of the channel further away from the drain, as presented in Fig. 7. This condition of operation is referred as saturation, therefore vDS is referred as vDSSAT = vGS - Vt.

Figure 6.

Conduction under vDS = vGS - Vt..

Once the transistor enters the saturation region of operation, the drain current iD becomes independent of the vDS.

Fig. 8 summarizes the conditions of operation of an nMOS transistor. Close to vDS = 0, current iD is directly proportional to vDS, with slope proportional to vGS - Vt. As vDS approaches vDS = vGS - Vt, the curve of bends because the channel resistance increases. After the vDS = vGS - Vt, the current becomes independent of vDS.

Figure 7.

Conduction under vDS > vGS - Vt.

Figure 8.

Operation condition of an nMOS transistor.

2.4. Deriving the iD - vDS relationship

Consider the biasing depicted in Fig. 9. Since the channel potential varies from zero at the source to vDS at the drain, the local voltage difference between gate and the channel varies from vGS to vGSvDS. Therefore, the channel density, or charge per unit length, is given as:


where v(x) is the potential at x and Cox is the capacitance, per unity area, formed by the gate and the channel.

Since, by definition, current is proportional to charge times velocity, and considering the current is the same along the channel, then:


Figure 9.

Biasing of an nMOS.

The minus signal is due to the negative charge of electrons. The velocity of carriers at low fields is the product of mobility (μ) and the electric field (E). Noting that E(x)=dV/dxand representing the electrons mobility by μn, then expression (2) can be rewritten as:


Now integrating along the channel, one obtains:


Thus, the expression for the drain current in the triode region is:


The value of the current for the saturation operation can be obtained by replacing vDS = vGS - Vt into expression (5), as:


As described earlier, the current does not depend on vDS. It can be observed from expressions (5) and (6) that the current is proportional to the ratioW/L, which is know as the aspect ratio. The designer can alter the aspect ratio to obtain the desired i-v characteristic.

Observe that expression (6) was obtained using the value of L, as given in Fig. 9. Nevertheless, when the transistor is saturated, the channel becomes shorter, as shown in Fig. 7. A reduction in the length of the channel, known as channel length modulation, means a variation in the resistance, and therefore a variation in the current iD.

Expression (6) can be modified in order to include the variation in the channel length, represented as L-ΔL, as:


which can be approximated to:


Since ΔL/L is proportional to vDS (the larger vDS the larger will be ΔL), then:


where λ is the parameter of proportionality.

The effect of channel length modulation can be seen in the iD - vDS characteristic of a MOS transistor shown in Fig. 10. The dependence of vDS on iD in the saturation region can be seen is represent by (1+λvDS) in expression (9) and can be observed in Fig. 10.

Figure 10.

Effect of channel modulation on saturation current.

An extrapolation of iD - vDS intercepts the vDS axis at vDS = − VA, known as Early voltage. For a given process, VA is proportional to L, selected by the designer. Typically, VA is in the range of 5 V/μm to 50 V/μm.

2.5. Output resistance

Fig. 10 and expression (9) show that an increase in vDS causes an increase in iD, meaning a resistive behavior. The value of the resistance is given as:


which can be simplified to:


Therefore, a MOS transistor in the saturation region is not totally independent of vDS and presents an output impedance given by (11)

Considering the transistor operating in the triode region, as given by expression (5), if the value of vDS is sufficiently small, vDS2can be neglected, and therefore:


This relationship represents the behavior of the MOS transistor as a linear resistance whose value is controlled by vGS, as given by:


2.6. Transconductance

The large signal behavior of a MOS transistor in the saturation region is given by expression (6). Nevertheless, for a given biasing, the designer may be interested in the small signal behavior of the transistor. For a given small variation in the vGS, around the biasing, there will be a variation in the iD current, given by the transconductance, as:


which results in:


Observe the transconductance depends on the ratio W/L and on the value of vGS, and they can be controlled by the designer. By using expression (6), then expression can be written as:


In this case, the transconductance depends on the ratio W/L and the iD current. That expression can be written also as:


It clearly does not depend on ratio W/L but it depends on both vGS and iD.

2.7. Body effect

In many circuits, the substrate and the source are not at the same potential, as it is possible to stack transistors. In that case, the substrate it is at lower potential than the source, and therefore the source-substrate junction becomes reversed biased. This reverse biasing widens the depletion layer, which in turn reduces the channel depth.

The effect of the bulk-source voltage VSB can be easily represented by a change in the threshold voltage - Vt, as given by:


where Vt0 is the threshold voltage for VSB = 0, ϕfis a physical parameter (usually 2ϕf= 0.6V) and γ is a fabrication-process parameter given by:


where q is the electron charge (1.6 x 1019 C), NA is the doping concentration of the substrate and εs is the permissivity of silicon (1.17ε0 = 1.17 x 8.854 x 10-14 = 1.04 x 10-12 F/cm).

Any signal between substrate and source promotes a drain current component. The substrate acts as a second gate, and in turn will present a corresponding trasnconductance, named body transconductance, given as:


From expressions (6), (17) and (18), then it is possible to state that:


where χ is given by:


And it is in the range of 0.1 to 0.

2.8. Small signal model

Considering the output impedance, the transconductance and the body effect, the small signal model of a nMOS transistor is given by Fig. 11, known as hybrid-π model.

Figure 11.

Hybrid-π model.

If the source and the substrate are at the same potential, then the model can be simplified, as the term gmbvbs goes to zero. The simplified hybrid-π model is shown in Fig. 12.

Figure 12.

Simplified hybrid-π model.

2.9. Summary

Table 1 summarizes the main nMOS equations.

SaturationConditionvDS ≥ vGS - Vt.
i-v characteristiciD12μnCoxWL(vGSVt)2
Output resistancero=1λiD=VAiD
Body transconductancegmb=χgm=γ22ϕf+VSBgm
TriodeConditionvDS < vGS - Vt.
i-v characteristiciD=μnCoxWL[(vGSVt)vDSvDS22]
Output resistancerlinear=vDSiD=[μnCoxWL(vGSVt)]1
Threshold voltageVt=Vt0+γ[2ϕf+VSB2ϕf]

Table 1.

Summary of nMOS equations.

2.10. pMOS transistor

In a pMOS transistor, a p channel is formed on an n substrate. Therefore, its operation is virtually the same as the nMOS transistor, except that all voltages and currents are opposite as in the nMOS transistor. Fig. 13 shows the symbols for the nMOS transistor, although other symbols may be found in the literature. The symbol in Fig. 13.a corresponds to the four terminal connection, and the symbol in Fig. 13.b corresponds to the three terminal connection, where source and substrate are shorted.

Figure 13.

Symbols for pMOS transistor; (a) four terminals and (b) three terminals.


3. RF CMOS model

Unfortunately, the structure and the operation of a MOS transistor present parasitic capacitances that limit its frequency of operation. The parasitic capacitances may result from the capacitor formed between the gate and the channel, between gate and source/drain, and between drain/source and substrate.

3.1. Gate capacitances

The gate, the dielectric and the channel form a capacitor. When the transistor is working in the triode region with a small voltage vDS, the channel will be of uniform depth, as shown in Fig. 4. Therefore, the gate-channel capacitance can be considered equally divided between the source and the drain, and their values are:

Cgs=Cgd=12WLCox(triode region)E23

When the transistor is working in the saturation region, the channel presents a tapered shape and it is pinched off at the drain end, as presented in Fig. 7. It can be seen that the gate to channel capacitance is almost entirely modeled at the source, since the drain does not present a channel. It can be shown that the capacitances are:

Cgs=23WLCox(saturation region)Cgd0E24

If the transistor is cut off, there is no capacitance between gate and channel, since there is no channel for cut off. The entire capacitance is then between the gate and the substrate, therefore:

Cgs=Cgd=0(cut off)Cgb=WLCoxE25

As can be observed from Fig. 1, the gate extends over the drain and the source areas. Therefore, there is an overlapping capacitance between the gate and the drain/source. Denoting the overlapping length by Lov, then the overlap capacitance can be seen to be:


For modern processes, Lov is usually in the range of 5% to 10% of L.

3.2. Junction capacitances

As shown by Fig. 2 there are two reversed biased junctions formed between the substrate and source/drain. Each junction consists of two semiconductors (drain/source and the substrate) and the depletion layer, thus forming a capacitor. The source-substrate capacitance can be found to be:


where V0 is the junction built-in voltage (0.6 V to 0.8 V), VSB is the magnitude of the reversed bias voltage and Csbo is the capacitance at zero reverse bias voltage.

By the same way, the drain-substrate capacitance is given by:


3.3. The high frequency model

The small signal model of the MOS transistor given in Fig. 11 can be update to include the gate and the junction capacitances, as presented in Fig. 14. Although this model represents the transistor for high frequencies, it is very complex for manual analysis.

Figure 14.

Hybrid-π model including the parasitic capacitances.

If the source and the substrate are shorted, the model can be greatly simplified, as shown in Fig. 15.

Figure 15.

Simplified high frequency model for source and substrate shorted.


4. Unity gain frequency

An important Fig. of merit for the MOS transistor is the unit gain frequency that is defined as the frequency in which the short circuit current gain becomes unit. This definition is based in the common source configuration, as shown in Fig. 16.

Figure 16.

Circuit model used to obtain the unit gain frequency.

The current Io in the short circuit is given by:


The approximation is due to the fact that Cgd is very small and can be neglected. Also, from the circuit, Vgs can be expressed as:


Therefore, from expressions (29) and (30):


Since the magnitude of IoIi should be 1, as per definition, and considering physical frequencies (s=jω), then:


Therefore, the unit gain frequency is:


As can be observed, the unit gain frequency is directly proportional to gm and inversely proportional to the internal capacitances. Therefore, in terms of frequency response the transistor should have large gm and small capacitances.


4. RF CMOS noise model

The two most important types of noise in MOS devices are the 1/f noise and the thermal noise.

4.1. Thermal noise

The main source of thermal noise in a MOS transistor is due to the resistive channel in the active region, and has a value of:


where k is the Boltzmann’s constant (about 1.38 x 10-23 J/K), T is the absolute temperature in kelvins and γ is a constant that is approximately 2/3 for long channel transistors and increase to the range 1-2 for short channel devices.

The other source of thermal noise is the gate. Fluctuation in the channel potential couples capacitively into the gate terminal, which in turn translates into a noise gate current. Noise gate current can also be produced by the resistive material of the gate. This total noise gate can be ignored at low frequencies but becomes significant at high frequencies as it is the case of RF circuits. It has been shown the gate noise may be expressed as:


where δ is approximately 4/3 for long channel transistors and increase to the range 2-4 for short channel devices, and gg is given by:


Mostly of the time, instead of using a current source at the gate, it is more convenient to consider an equivalent voltage source. The equivalent voltage source of expressions (31) and(32) is given by:


where rg is given by:


4.2. 1/f noise

The 1/f noise, also known as flicker noise or pink noise, arises mainly due to the surface imperfections that can trap and release charges. Since MOS devices are naturally surface devices, they produce much more 1/f than bipolar devices (which are bulk devices). This noise is also generated by defects and impurities that randomly trap and release charges. The trapping times are statistically distributed in such a way that lead to a 1/f noise spectrum.

The 1/f noise can be modeled by a voltage source in series with the gate, of value:


For pMOS devices, β is typically about 10-28C2/m2, but it can be up to 50 times larger for nMOS devices.

As can be observed from expression (53), the 1/f noise is smaller for larger devices. This occurs because the large capacitance smoothes the fluctuation in the channel charge. Therefore, in order to achieve good 1/f performance, larger devices should be used.

The 1/f can also be modeled as a current source at the drain whose value is:


where A is the area of the gate.

4.3. Noise model

The noise model of an nMOS transistor is presented in Fig. 17, where the transistor is considered noiseless. The decision of placing the noise sources as a voltage source at the gate, or as a current source at the drain is just a matter of convenience according to the circuit under analysis. As an example, the values of Fig. 17 could be:


5. Conclusions

The proper understanding of physical operation to modeling of CMOS transistors is essential to the analysis and design of RFID circuits. Among its advantages, the CMOS transistors demands lower power consumption than other transistors.

Noise analysis of CMOS transistors is also fundamental to analysis and design of any circuit, including RFID.


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Written By

Tales Pimenta, Robson Moreno and Leonardo Zoccal

Submitted: 09 November 2010 Published: 20 July 2011