1. Introduction

Microprocessors in modern computer and computing systems can be coupled to various interfaces and the external world through the chip input/output (I/O) modules. Over the years, the performance of modern computer systems has seen intense improvements due to the advancements in semiconductor process. This has allowed the continuous increase in the number of transistors in a single integrated circuit (IC), according to Moore’s Law [1]. Subsequently, the improvement of processor performance in terms of speed and power has also dramatically increased due to the merit of larger transistor budget and the faster transistor switching speed [2]. Moreover, multi-core architecture is a new trend of processor design to further improve processor performance through parallel tasks performed by the cores. The chips of these cores can be placed on a common substrate through MCM (Multi-chip Module) packaging technology [3, 4, 5, 6].There are three main MCM technologies: MCM- C, which uses co-fired multilayer ceramic substrate technology; MCM-D, which uses thin-film deposition technology and MCM-L, which uses lamination technology [7]. Among these main MCM technologies, MCM-L is widely used in microprocessor packaging industries for high volume consumer and low cost products [6]. Therefore, the processor performance can be further boosted with multi-core architecture realized by MCM-L packaging technology.

Unfortunately, the performance improvements in the microprocessors has not lead to comparable improvement in the performance of computer and computing systems [8], which is primarily due to the chip I/Os [3]. This is because microprocessor and application specific integrated circuit (ASIC) vendors provide I/O modules with fixed output driver circuits that are designed to compromise/adapt to various system applications [9]. Each ASIC vendor has a different cost-performance-risk-schedule trade-off for the combination of application, chip supplier, chip assembler, substrate fabricator, module assembler and end user [10]. Hence, depending on the decision of vendors, it becomes challenging for a chip I/O with fixed output driver circuits to achieve optimum performance across a variety of applications [7]. Any signaling mismatches between the processor and the chip I/O would clearly impact the overall system performance, resulting in delays that limit the computer system from achieving higher/expected computing speed [11]. A non-optimal solution is to reduce the application operating speed by reducing the speed of processor to an extent that the receive signal eye opening is just sufficient for data detection and recovery [11]. Although the system requirements still can be achieved with lower processor speed, but the system performance is not at best optimized due to the compromise of speed between the chip I/O and the processor. Also, as the operating frequency of ASIC application continue to increase, signal integrity on data transmission between chip I/Os has become a bottleneck due to several types of noise, including Inter-Symbol Interference (ISI) noise, switching noise, and reflection noise [8, 12, 13, 14]. ISI is caused by frequency dependent attenuation of transmission channel that increases with operating frequencies and degrades noise margins, giving small eye opening and resulting in very low possibility of correct data detection and recovery [15, 16, 17, 18]. Moreover, output drivers in advanced technologies can switch faster due to lower threshold voltage, V_T, but this results a considerable supply current change in a short time (di/dt) and causes switching noise on power supply and output voltage of drivers [19, 20, 21]. Also, reflection noise occurs when the output impedance of output drivers is mismatched with characteristic impedance of transmission channel at high frequencies [22, 23]. Additionally, the trend in scaling down CMOS process technology dramatically deteriorates the channel-length modulation effect and this causes challenges in designing I/O driver circuits that employs current-mode transmission like current-mode drivers. Channel length modulation causes symmetric error between current mirror and current-mode driver, resulting output swing that has large deviations from the desired value [15]. Moreover, the ISI, switching noise, and reflection noise can further deteriorate the output swing deviations, thereby reducing the signal eye opening and causing difficulties for correct data detection [24].

Tradeoffs have been made between electronic signaling and operating frequency to ensure that the computer system can function. However, the system performance is not at best optimized due to the compromise of speed between I/O modules and processor [9]. Thus, configurable input/output (I/O) driver is desired whereby different I/O driver types can be configured from the I/O driver to support multiple signaling types without compromising system performance across a variety of applications [25]. In addition to signal integrity issues at high frequencies due to technology scaling, channel length modulation causes symmetric error between current mirror and current-mode driver, resulting to an output swing that has large deviations from the desired value [15]. These output swing deviations can be further deteriorated by ISI, switching noise and reflection noise, thereby degrading signal integrity and causing difficulties for correct data detection [24]. Also, the general trend in chip size reduction due to transistor technology scaling has led to chip size reduction and the advancement in packaging technology. However, due to the limited I/O pin count in these chip packages and PCBs, designing efficient high-speed and low power chip I/O is important.

Hence, in this chapter, we present the design of a configurable I/O driver circuit that can be configured between voltage-mode and current-mode driver to address electronic signaling mismatch between chips and achieve optimum performance across different processor-intended applications. The configurable I/O driver supports a wide range of data-rate of 0.4–8.0 GHz. Also, in the design, four control schemes, namely, impedance control, output swing control, slew rate control and de-emphasis were implemented in the configurable I/O driver to address ISI, output switching noise, reflections and output swing variation. Thus, improving signal integrity at high data-rates. Clear eye openings with improved jitter performance were obtained at high data-rates. This work is conducted in a 45 nm CMOS technology.

2. Chip I/O design overview

This section discusses the overview of several types of output driver, their operation, pros, and cons. In addition, several design techniques to improve driver circuit performance are discussed, including differential signaling; slew rate control on output; output impedance control; and de-emphasis technique to compensation the ISI impacts.

2.1 Output circuit driver

An output driver encodes a symbol into a current or voltage form for transmission over a line. An output driver can also be referred to as a transmitter. In this chapter, the term “output driver” and “transmitter” is used interchangeably. A good transmitter has output impedance optimized for selected transmission mode. Voltage-mode driver and current-mode driver are two fundamental output driver circuits that will be discussed in this section.

2.1.1 Voltage-mode drivers

A voltage-mode transmitter has very small output impedance due to its implementation using large size transistor that operates in the linear region [20]. The simplest circuit of voltage-mode driver is a push-pull driver implemented in a digital CMOS inverter. Figure 1a shows the architecture of push-pull driver that was very popular in the early 1980s due to simple implementation and low power consumption [8]. When the gate voltage VIN is low, the NMOS is turned-off, while PMOS is turned-on to pull the output voltage up to VDD and vice versa. Figure 1b depicts the I–V characteristic of a NMOS when the gate voltage of push-pull driver is high. However, the non-linear I–V characteristic in combination with small output impedance of voltage-mode driver are mismatched with the characteristic impedance of transmission channel, thus causing it to suffer from signal reflection, especially when the operating frequency is increasing in modern IC applications [22].

Figure 1.
(a) Push-pull driver circuit, (b) non-linear I–V curve of push-pull driver [8], and (c) SST driver circuit with series resistor at output node [15].

Therefore, another voltage-mode driver called Source-Series Terminated (SST) driver in Figure 1c can solve the reflection issues encountered by push-pull driver [15]. The basic structure and operation is the same as that in the push-pull driver, the series resistor, R_S, is connected to the node between pull-up and pull-down transistor. This is an essential supplementary element for an output driver operating in high-speed applications, as the output driver not only transmits data, but can also act as self-terminator to minimize any reflected signals [26]. The series resistor value is often chosen close to transmission channel impedance to minimize signal reflections. However, this requires large transistors so that the resistance value contributed by the transistor is almost negligible and thus, the driver output impedance is primarily dominated by the series resistor, R_S. Moreover, large pre-driver is required to drive the large transistors in the output driver, which adversely impacts the area efficiency. Thus, to overcome these limitations, another type of SST driver of driver circuit is implemented by connecting the series resistor with a smaller resistance, R, in series with the pull-up and pull-down segment (Figure 2a) to improve the linearity of driver without area penalty [20]. This is because, the use of smaller resistance, R, can reduce transistor size and hence, further reduces silicon area occupied when compared to conventional SST driver shown in Figure 1c. However, the series resistor cannot be too small to the point that the driver starts to exhibit non-linear I–V characteristic. This is a tradeoff between driver linearity and driver silicon area. Figure 3b shows the increase of series resistance in pull-down segment (when input of SST driver is logic high) can improve driver linearity. A suitable series resistance R must be selected to give a balance between driver linearity and silicon area.

Figure 2.
(a) Saturated FET driver circuit with resistive load at receiving-end, and (b) differential current-mode driver with terminating load at transmitting-end and receiving-end [8].

Figure 3.
(a) Architecture of SST driver that has series resistor R in pull-down and pull-up segment, and (b) I–V linearity is improved with larger series resistance R [20].

2.1.2 Current-mode drivers

The simplest current-mode driver is a saturated FET driver shown in Figure 2a. From this figure, the impedance looking into the transmitting-end is huge because of the huge impedance from the constant current source implemented by the transistor in saturation region. This circuit is simple as it does not require any pull-up device at the transmitting-end and this feature makes it very suitable in low-cost applications [8]. Moreover, resistive load value, R, can be chosen as Z_O to match the transmission channel so as to minimize signal reflected back to transmitting-end. However, high-speed data transmission often employs both side termination schemes to minimize reflections. This makes the saturated FET driver unsuitable in high-speed application due to unmatched impedance at the transmitting end [26]. Differential current-mode driver can overcome the limitations of saturated FET driver [8]. The circuit of differential current-mode driver with resistive terminator, R, at transmitting-end and receiving-end is depicted in Figure 2b.

The trend in scaling down CMOS process technology dramatically deteriorates the channel-length modulation effect and this causes challenges in designing output driver circuits that employs current-mode transmission, such as the current- mode drivers. Channel length modulation causes symmetric error between current-mirror and current-mode driver, resulting to output swing that has large deviations from the desired value [24]. A non-optimal solution is to supply more current into output driver through the current-mirror to increase the output swing. However, this solution can cause larger power consumption [15]. Thus, current compensation (ICOMP) techniques have been used to overcome the symmetric errors between current mirror and current-mode driver to control output swing at desired value [24].

2.1.3 Configurable drivers

Fixed type of output drivers introduced in previous sub-sections might not be suitable in some circumstances as their advantages cannot be completely utilized to maximize the system performance. A fixed I/O driver is a compromise of various applications when it is used in multiple applications as the fixed features of that I/O driver cannot fit in various applications [9]. Besides, system upgrade that touches upon different signaling types and data rates has established design challenges on I/O drivers. A fixed type I/O driver is unable to support backward compatibility that come across with different signaling types and data rates [13]. For instance, I/O driver designed for Universal Serial Bus (USB) applications may be required to support different operating modes like low-speed, full-speed and high-speed mode that involve different signaling types and data rates [27, 28]. Therefore, configurable drivers are utilized in this situation. Different types of drivers can be integrated into one configurable driver so that the suitable driver type can be selected to fit the applications, as well as to support different signaling types and data rates. A multi-configurable HSTL (High-Speed Transceiver Logic)/LVCMOS (Low Voltage CMOS)/Open-Drain output driver circuit was proposed in Ref. [12] that consists of push-pull and open-drain transistor that are selectively enable or disable, depending on the desired mode of operation in a variety of system configurations. Figure 4a shows the circuit of multi-configurable output driver. Generally, this configurable I/O driver circuit can be switched into two main categories which are push-pull and open-drain mode through the selector transistors.

Figure 4.
(a) A multi-configurable HSTL/LVCMOS/open-drain output driver and multi-configurable driver in (b) push-pull mode, and (c) open-drain mode [12].

In push-pull mode, transistors P2 and N3 are deactivated, resulting in push-pull circuit as shown in Figure 4b. The push-pull circuit consists of pull-down transistor N2, pull-up transistor N1, and series terminator RT. Instead of using PMOS transistor, this circuit uses a NMOS transistor to pull-up the output voltage due to its fast switching speed. However, the transistor N1 can only charge the output voltage up to VDD – V_T, where V_T is the threshold voltage of PMOS. Thus, a PMOS transistor P1 is activated to further pulling-up the output voltage to VDD after a short delay introduced by inverter. In addition, the supply voltage VDD can be changed to different levels to support HSTL and LVCMOS interface when the driver is operated in push-pull mode. Also, in open-drain mode, transistors N1 and P1 are deactivated as shown in Figure 4c. Open-drain transistor N3 is used to transmit data while the transistors P2, N2, and terminator resistor RT are used to absorb the surge energy from the transmission channel when N3 is turned-off. However, the transition time of this multi-configurable I/O driver is not-well controlled and this causes the driver to be vulnerable to output oscillations. Full-swing nature can restrict the driver from operating toward higher data rates. Moreover, non-linear characteristics of output impedance makes this driver susceptible to reflection noise at high-speed.

Consequently, a dual-mode transmitter that is programmed and configured as full-swing voltage-mode transmitter for low speeds or a 400 mV reduced-swing current-mode for high speeds was proposed in Ref. [13]. Figure 5a shows the dual-mode transmitter that comprises of pre-driver and main driver. Pre-driver in Figure 5a decodes the mode control signals and generates necessary signals based on input data TXi for main driver. When the dual-mode transmitter manipulates in voltage transmission mode, transistor M1 and M3 switches in opposite phase with input, while M2 and M4 switches in phase with the input (Figure 5b). Transistor M0 operates in the linear region which serves as the pull-up terminate resistor, R0, whereas resistor R1 and R2 are pull-down terminators, as depicted in Figure 5b.

Figure 5.
(a) Dual-mode transmitter circuit; and dual-mode transmitter operates in (b) voltage-mode, and (c) current-mode [13].

In the current transmission mode shown in Figure 5c, transistors M1 are M2 are switched differentially, while M3 and M4 always operate in linear region which can combine with R1 and R2 to serve as terminate resistors. Transistor M0 operates in saturation mode as a current source biased by Vb. However, this transmitter suffers from the transistor channel-length modulation effect that causes large symmetric error between current mirror and current-mode driver. Moreover, continuous scaling down of CMOS technology has dramatically increases the channel-length modulation effect and this can cause the transmitter output swing to have large deviations from the desired value and result in wrong logic sampled at receiving-end.

2.2 Techniques to improve driver circuit performance

The conventional ways to improve I/O performance include using differential signaling to reduce common-mode noise, controlling output slew rate to reduce switching noise, using on-die termination to absorb signal reflections, controlling output impedance to minimize signal reflections, controlling output swing of current-mode driver to minimize output swing deviations, as well as de-emphasizing data to overcome inter-symbol interference (ISI).

Differential signaling improves the signal-to-noise ratio (SNR) of a driver circuit as it causes the swing of differential signal to be doubled when compared to the swing of a single-ended signal. Moreover, majority of common-mode noise can be rejected through the use of differential signaling in data transmission which further improves the performance of the driver circuit [8, 13].

Simultaneous switching noise (SSN) and ground bounce noise are important considerations in the contemporary output driver circuit design [19, 28]. In general, the purpose of controlling slew rate of output driver is to have a controllable switching rise and fall times from the I/O driver [20]. Some of the several techniques to control the output slew rate include the use of passive delays after pre-driver stages; and the time-split technique. The former slows down the transition time of the I/O drivers and the output slew rate to reduce SSN [8]. However, this techniques may lead to large delay and results to excessive ISI because the pre-driver output will not reach steady state by the end of bit cell and may result to worst jitter [20]. Hence, this concept is not feasible for I/O design at the present-day. The latter is based on the principle of splitting the pull-down and pull-up transistors into parallel segments and sequentially activating each segment in a proper delay, which is considered a very effective technique and is suitable for high speed CMOS drivers to reduce both SSN and reflection noise at the same time [13].

In some high-performance signaling systems, resistive terminations are needed at both transmitter and receiver to absorb traveling waves to prevent unwanted reflections [29]. In these systems, the receiver termination absorbs the forward-traveling signal transmitted by transmitter, while transmitter termination absorbs reflections from transmission channel impedance discontinuities to prevent backward-traveling reflections [8]. In the communication between chips, the receiver termination, RTERM, can be achieved by placing discrete resistors on package or board and this can be called off-chip termination. In addition, instead of placing the necessary termination on the package, the advancement in fabrication process has enabled the termination to be located on the chips or dies and this technology is called on-die termination (ODT), which allows simpler system design and cost effective as the employment of ODT can reduce the number of resistive termination elements and complex wiring on the board [8]. The ODT can be easily implemented by using transistors or combinations of transistors and resistors from CMOS fabrication processes. However, these transistors and resistors are PVT (Process, Voltage, and Temperature) dependent and they must be compensated by on-chip resistance calibration technique.

On-chip resistive termination can be used to absorb traveling waves and prevent unwanted reflections at transmitters, receivers or both sides in high performance systems. Hence it is critical to have the impedance terminator always close to the impedance of transmission channel over all possible temperatures, voltages and processes [30]. As discussed earlier, the SST driver is formed by a transistor connected in series with a resistor. During fabrication, as they go through the myriad stages like photolithography, ion implantation, doping, metallization, and oxides, all contributes to various aspects of the final circuit [8]. For example, an oxide thickness of the devices may result to different I–V characteristics of transistors. Thus, if such device with inconsistent I–V characteristic is used as driver element, large variations in driver strengths will occur and impact the system performance due to un-matched impedance value of driver with the transmission channel [31]. Therefore, it is necessary to calibrate the on-chip terminators by either analog or digital means over all possible ranges of PVT [23, 30]. While the advantages of analog resistance calibration is the fact that the resistance value is continuously adjusted according to PVT variations and it does not generate noise during the calibration process [23], the advantages of the digital calibration scheme are the on-chip DC power reduction, owing to the employment of digital gates [19]. However, the analog technique in Ref. [23] has high DC power dissipation and the impedance of several on-chip drivers cannot be adjusted independently [30].

The output swing of current-mode driver is required to be controlled across PVT variations to provide sufficient eye opening at far-end without consuming excessive power. Thus, the tail current source used to generate the driver output swing needs to be PVT-compensated against the desired reference swing [24]. Hence, the Current Compensation (ICOMP) block is proposed by Ref. [24] to calibrate driver output swing across PVT variations.

Equalization is a circuit technique to compensate for the loss of transmission channel at high speed [29, 32]. Equalization circuits can be integrated with transmitter circuits or receiver circuits. Transmitter equalization is commonly done in high performance systems because transmitter equalization permits the use of simpler far-end receiver as compared to receiver equalization that needs a high resolution ADC (analog-to-digital converter) that creates design challenges [8]. Some transmitter equalization circuits include pre-emphasis and de-emphasis techniques [33]. Pre-emphasis technique emphasizes the high-frequency components of the transmitted signal. The pre-emphasis transmitter increases the amplitude of high-frequency components or transition pulses as compared to the amplitude of high-frequency components in the original signal swing. However, the increase of amplitude of high-frequency components can cause EMI (Electromagnetic Interference) and more severe current spikes [33]. Therefore, de-emphasis technique is developed to minimize EMI and current spikes problems by only de-emphasizing the low-frequency components of a digital signal [30, 31, 32, 33, 34]. More information about de-emphasis types (differential current-mode driver and differential voltage-mode driver) are presented in Ref. [15].

3. Design methodology and circuit implementation

This chapter presents the design and implementation of a configurable I/O driver as a standard cell that can achieve optimum performance across various ASIC applications. The configurable I/O driver can be configured in different modes supporting a variety of intended ASIC applications. The proposed driver is integrated with impedance, output slew rate, de-emphasis and output swing control schemes to address reflection noise, minimize switching noise, compensate ISI noise and control output swing at desired level, respectively.

3.1 Circuit simulation model

The proposed driver performance is verified through simulates with non-ideal characteristics that are commonly used in modern IC packages. These non-ideal characteristics are the package and substrate parasitic that cause I/O ringing [19] and the transmission channel losses at high frequency [32]. The package parasitic and transmission channel are modeled based on [29, 35, 36, 37].

3.2 Performance evaluation methodology

By including the non-ideal characteristic like package parasitic and transmission channel losses into simulation, the performance of the proposed configurable I/O driver is evaluated using eye diagram with a series of random data generated from 27 – 1 PRBS (Pseudo Random Binary Sequencer) [38]. To create eye diagram, the time-domain signal waveform is slicing into segments and overlaying them. Therefore, in this work, the eye jitter must be smaller than 0.30 UI to provide sufficient time to fulfill setup and hold constraint of far-end receiver. Moreover, the maximum height of differential eye must be larger than 200 mV to ensure that the voltage levels meet input high and low limit requirements of the receiver [9]. It is reasonable to restrict the differential eye height and jitter specification as this allows the use of a relatively simpler and more power efficient receiver at far-end.

3.3 System architecture and performance requirements

The configurable I/O driver design in this research is established according to the specifications stated in Table 1 [24, 39].

Specifications	Value
Supply voltage (VCC)	1.0 V ± 5%
Data rates	0.4–8.0 Gbps
Output slew rates	2–4 V / ns
ODT impedance	(50, 75 and 150 Ω) ± 5%
ODT impedance linearity error	± 15% maximum
Output driver impedance	50 Ω ± 5%
Output driver impedance linearity error	± 15% maximum
Output swing (single-ended in current-mode driver)	(400 and 500 mV) ± 5%
Receive eye jitter (peak-to-peak)	0.30 UI maximum
Receive eye height (at middle of differential eye)	200 mV minimum

Table 1.

Specifications of the proposed configurable I/O driver.

The overall architecture of proposed system consists of a configurable I/O driver, a driver controller, two delay lines (Delay Line 1 and Delay Line 2), and a PVT-compensation block that contains R-COMP and I-COMP, as depicted in Figure 6.

The proposed I/O driver in Figure 6 can be configured into different driver modes to support different signaling and achieve optimum performance across different processor-intended applications. In the driving mode, the proposed I/O driver can be configured into single-ended/differential voltage-mode driver (push-pull driver) or differential current-mode driver. In the receiving mode, the proposed I/O driver can be configured as pull-up or pull-down ODT to terminate any reflections from far-end, thereby improving signal integrity for near-end receiver. The proposed I/O driver consists of three driver modules and is designed, based on a modular concept. The driver is subdivided into smaller modules and each module is further decomposed into four driver stages that can be designed independently. Modular design can ease the design process and allow different impedance values to be configured from the I/O driver. Moreover, the pull-up and pull-down segment in each driver stage are PVT-compensated at 600 Ω. This gives an equivalent output impedance of (600 Ω/4 stages) or 150 Ω when all the four stages in a module are activated. Thus, by enabling different number of driver modules in parallel, through the MODULE_EN[2:0] signal, multiple impedance values of 50, 75 or 150 Ω can be obtained. Also, the driver controller in Figure 6 is used to process and prepare the input/output driver. Input and output can be two single-ended data or differential data, depending on mode control signal MODE[1:0].

The output slew rate control scheme is applied in the proposed system in Figure 6. In this control scheme, two delay lines, namely, Delay Line 1 and Delay Line 2, are used to control the output slew rate to reduce switching noise. In addition, when the output driver is operating with high data rate over long transmission channel, the ISI noise starts dominating switching noise and de-emphasis control scheme can be introduced to reduce ISI-induced jitter; thereby reducing sampling errors and improving signal integrity over the transmissions.

The PVT-compensation block in Figure 6 consists of impedance compensation (R-COMP) and current compensation (I-COMP) block implemented based on on-chip impedance and output swing control scheme, respectively. The R-COMP is used to calibrate on-chip impedance within ±5% variation as shown in Table 1, across PVT variations to minimize reflection noise. When the proposed I/O driver is configured as current-mode driver, I-COMP block can be used to calibrate output swing within ±5% variation from targeted swing across PVT variations. All compensation blocks are global blocks and their digital codes can be distributed within the chip.

3.4 Design architecture

This section presents the design details of each block in the overall system block diagram (Figure 6), including configurable I/O driver, driver controller, delay lines and compensation block.

3.4.1 Configurable I/O driver

As described in Section 3.3, the configurable I/O driver is designed based on modular design concept such that it can be divided into smaller driver stages that can be created independently. Figure 7 shows the architecture in a driver stage that consists of pre-driver, mode-controller and main driver. The pre-driver provides suitable VP1, VP2, VN1, VN2 and VSW signal based on the driver control signals generated by driver controller. Main driver consists of two half drivers with a switch M7 between them. Series resistor R1 and R2 are sized to 85% of overall impedance to reduce the linearity error of pull-down and pull-up segment below 15% [22]. This is essential because the I/O driver should act like a self-terminator that can eliminate any reflections in high speed communications [26]. Thus, the impedance of both pull-up and pull-down segment are needed to exhibit linear characteristics (Figure 3) and match transmission channel impedance to terminate any reflections. Also, the operations when the I/O driver is configured into different driver types will be discussed in the following sub-sections.

Figure 7.
Pre-driver and main driver architecture in a driver stage.

3.4.1.1 Single-ended and differential voltage-mode driver

Main driver in Figure 7 can be configured as two single-ended voltage-mode drivers implemented using the push-pull topology. The operation of the two single-ended push-pull drivers is shown in Figure 8a, where D1 and D2 are two independent inputs generated by a pre-driver. In push-pull operation, input transistor M1 and M3 are switched in phase with D1, while input transistor M2 and M4 are switched in phase with D2. Transistor M5 and M6 operate in linear region as the biasing voltage VBIAS is set to VSS. Switch M7 is opened by setting VSW = VCC to ensure proper push-pull operations for the two single-ended push-pull drivers. Figure 8b shows the macro-model of two single-ended push-pull drivers, while Figure 8c is a timing diagram to demonstrate the operation of single-ended push-pull driver. However, the full swing nature of single-ended push-pull driver limits the data rates [13]. Thus, this type of driver is only suitable for some low-speed and low-cost applications where terminators at receiving ends can be removed to reduce system costs.

Figure 8.
Single-ended push-pull driver configured from main driver: (a) transistor implementation, (b) macro-model, and (c) operation in timing diagram.

However, low swing and differential signaling are keys to improve data rates. Low signal swing can reduce current spikes, transition time, while differential signaling can reject common-mode noise along the transmission. Figure 9a shows the transistor implementation of differential push-pull driver. The operation is same as that in the single-ended push-pull driver, except that the two inputs now become differential input (D and DB) generated from the pre-driver. Differential push-pull driver can support two termination schemes at far end, namely, low common mode and high common mode terminations and hence, the signal swing is half of the supply rails and this allows the output driver to operate at higher data rates. The macro-model of differential push-pull driver is shown in Figure 9b. In addition, the operation of differential push-pull driver is also demonstrated in Figure 9c.

Figure 9.
Differential push-pull driver: (a) transistor implementation with far-end termination to ground, (b) macro-model, and (c) operation in timing diagram.

3.4.1.2 Differential current-mode driver

Main driver in Figure 7 can be configured as a differential current-mode driver. Figure 10a shows the transistor implementation of differential current-mode driver.

Figure 10.
Differential current-mode driver with far-end termination resistors: Transistor implementation, (b) macro-model, and (c) operation in timing diagram.

From Figure 10a, pull-down segments serve as transmit terminators with transistor M1 and M2 biased at VCC by the pre-driver. Transistor M5 and M6 are biased to be current sources through current-mirrors while transistor M7 acts as a closed switch. Input transistor M3 and M4 function as switches to alter the direction of current flow from current sources based on the differential inputs (D and DB). Moreover, the operation of current-mode driver can be explained using macro-model and timing diagram in Figure 10b and c, respectively. When D is low, transistor M3 is turned-on while M4 is turned-off. This allows a total current of 2 × I_B flow through M3 to both the pull-down segment and far-end RTT with each carry current amount of I_B to raise the node, OUT, to the desired voltage swing level, V_SWING. To maintain output high level at V_SWING, current I_B can be tuned and calibrated in each driver stage across different PVT corners. By calibrating I_B in each driver stage, one interesting feature is that the output high level can still be maintained at V_SWING, when all the three driver modules are enabled. This is because, every driver stage in the driver modules has identical operating points. Thus, instead of three driver modules, it is sufficient to use only one driver stage in I-COMP and this can significantly reduce power consumption and silicon area footprint.

3.4.1.3 Receive on-die termination (ODT)

When the proposed configurable I/O driver is operating in receiving mode, it can be configured as receive ODT to absorb any reflected signals to improve the signal integrity for near-end receiver. This can be achieved by enabling different number of 150 Ω driver module in parallel through the MODULE_EN[2:0] signal in Figure 6, thereby providing multiple impedance values of 50, 75 or 150 Ω. Thus, the main driver in Figure 7 should be designed such that it can be configured as near-end receive ODT to power supply or ground. Figure 11a shows the transistor implementation of near-end receive ODT.

Figure 11.
Near-end receive ODT configured from main driver: Transistor implementation, (b) macro-model, and (c) operation in timing diagram.

In addition, the marco-model of receive ODT and its operation in time domain is shown in Figure 11b and c, respectively. The advantage of this receive termination-merged driver structure is that it helps in reducing the output pin capacitance, when compared to conventional implementations which have separate structure for the transmit drivers and receive termination [40].

3.4.1.4 Pre-driver and mode control circuit

The main driver in Figure 7 consists of half-driver1 and half-driver2 circuit. Two pre-drivers are required to generate the corresponding inputs for the half-drivers (VP1 and VN1 for half-driver1, VP2 and VN2 for half-driver2). Thus, Figure 12a shows the circuit of pre-driver for a half-driver. By taking input data (PU and PD), driver enable (DRV_EN and DRV_ENB), driver module enable (MODULE_EN and MODULE_ENB) and compensation code (COMP_PU and COMP_PD), the logic gate NAND1 and NOR1 in pre-driver can control the main driver to pull-down/pull-up the output or in tri-state condition. In addition, the mode controller in the pre-driver can generate suitable input data PU and PD based control signal CM/VM for different operation modes i.e. voltage-mode (push-pull driver), current-mode driver or termination, as shown in Figure 12b. The operations of mode controller for different drive types are also summarized in Table 2.

Figure 12.
Pre-driver and mode-controller for a half-driver circuit in Figure 12: (a) logic implementation, and (b) operation sequences in time domain.

Operating Mode	Input	Output
Operating Mode	CM/V M	PU	PD
Push-pull	0	D	D
Current-mode	1	D	VSS (pull-down segment always ON)
ODT to VCC*	0	D = VCC	D = VCC
ODT to VSS*	0	D = VSS	D = VSS

Table 2.

Driver operation mode and output of mode controller circuit.

*

Note: The operation of receive ODT is the same as push-pull driver, except input D is set to power rails.

3.4.2 Driver controller

The functional diagram of driver controller is shown in Figure 13.

Figure 13.
Block diagram of driver controller in logic implementation.

The main function of driver controller is to decode MODE[1:0] to configure the proposed I/O driver into desired operating driver types. In Figure 13, the driver controller consists of de-emphasis block, command decoder block and data controller block. De-emphasis block is employed to generate inverted one bit shifted data IN1n−1¯ and IN2n−1¯ based on IN1[n] and IN2[n] for the de-emphasis driver when the de-emphasis control scheme is activated. Command decoder block is used to decode the MODE[1:0] into three control signals, namely CM/VM¯, OCD/ODT¯ and DIFF/SE¯. The descriptions of these control bits are shown in Table 3.

Control bit	Description
CM/VM¯	Asserted high if current-mode driver is configured. Otherwise, voltage-mode driver is configured.
OCD/ODT¯	Asserted high if proposed design is configured as off-chip driver. Otherwise, the proposed design is configured as receive on-die terminator.
DIFF/SE¯	Asserted high if differential signaling is configured. Otherwise, single-ended signaling is configured.

Table 3.

Description of control bits generated by command decoder.

Also, the logic implementation of the data controller block is also shown in Figure 14. The function of data controller is to generate ordinary data IN1[n] and IN2[n] based on control signal OCD/ODT¯, DIFF/SE¯ and ODT_VCC/ODT_VSS¯ for the proposed I/O driver. When OCD/ODT is asserted high, the proposed I/O driver is in driving mode and IN1[n] and IN2[n] can be generated as differential data or two single-ended data based on DIFF/SE¯ bit. When OCD/ODT¯ is asserted low, the proposed I/O driver is in receiving mode and both the IN1[n] and IN2[n] can be generated as VCC or VSS for receive ODT to power supply or ground based on ODT_VCC/ODT_VSS¯ bit. The operations of data controller are demonstrated as a flow chart in Figure 14.

Figure 14.
Operations of data controller based on control bits in Table 2.

3.4.3 PVT-compensation block

On-chip impedances and output swing (in current-mode driver) are subjected to PVT variations and are required to be calibrated to sustain the driver performance. In this work, the main driver in the driver stage (Figure 7) is designed with multi-leg structure where the pull-up and pull-down segment consists of one static leg and four binary-weighted dynamic legs that can be turned-on or turned-off for impedance and output swing calibration, as depicted in Figure 15a and b. Impedance control and output swing control scheme can be applied by adjusting the dynamic legs of the multi-leg structure in the PVT-compensation block shown in Figure 6 to calibrate driver impedance and output swing, respectively.

Figure 15.
Main driver in Figure 7 designed with multi-leg structure for (a) pull-up segment, and (b) pull-down segment.

3.4.3.1 Impedance control scheme

Impedance control scheme is implemented by R-COMP block in the PVT-compensation block to calibrate the driver output impedance. Digital compensation is chosen due to the merit of DC power reduction with digital logics in R-COMP. In the R-COMP block, the driver impedance of a single driver stage (see Figure 7) is compensated at 600 Ω ± 5% by using a dummy pull-up and pull-down segment shown in Figure 16a and b respectively. Figure 16a shows the architecture of compensation block for pull-up impedance. The output net VOUTP from pull-up segment is connected to an external reference resistor REXT with 600 Ω ± 1%. Each pull-up segment has one static leg and four-bit binary-weighted dynamic legs in parallel. Static leg is always activated to provide impedance that are close to 600 Ω to fasten calibration process, while dynamic legs are adjusted by PUN FSM (Pull-Up Network Finite State Machine) until the total impedance match to 600 Ω. When VOUTP is lower than VREF, this implies pull-up impedance is larger than reference resistor. This delta voltage will cause comparator outputs UDP with logic high for up- down counter (U/D Counter) to count up the COMPP[3:0] so as to increase the dynamic legs in the pull-up segment to rise the VOUTP voltage until it is slightly higher than VREF. Then, the comparator will output UDP with logic low for U/D Counter to count down COMPP[3:0] to decrease the dynamic legs by one and hence, reducing VOUTP. This process will continue and the VOUTP will be alternating about VREF as UDP always toggle due to the quantization error between pull-up impedance and reference resistance. This implies that the COMPP[3:0] will be increased or decreased by one and this toggling code cannot be delivered to I/O driver. Thus, a pattern catcher is used to catch the up-down sequence of the UDP signal. When VOUTP is alternating about VREF and UDP is toggling, the pattern catcher will output a lock signal (LOCKP) to the 4-bit hold-register to make the RCODEP[3:0] = COMPP[3:0] at the output of register so that the compensation code is held constant for the I/O drivers.

Figure 16.
Impedance compensation block (R-COMP) for (a) pull-up segment, and (b) pull-down segment.

Figure 16b shows the architecture of compensation block for pull-down impedance. Once the compensation for the pull-up segment is done, the LOCKP signal will be generated by PUN FSM to kick-off the compensation process for pull-down segment. In addition, the RCODEP[3:0] from PUN FSM will be delivered to the pull-down segment in Figure 16b since this pull-up segment (compensated at 600 Ω) is now becoming reference resistor for the pull-down segment. When the VOUTN is higher than VREF which implies pull-down impedance is larger than 600 Ω, the comparator will output UDN with logic high for U/D Counter to count up the COMPN[3:0] to increase the number of dynamic legs in pull-down segment so as to reduce the VOUTN voltage. This searching process will continue until VOUTN is alternating about VREF and UDN is toggling, the pattern catcher will output a lock signal (LOCKN) to 4-bit hold-register to hold the output at RCODEN[3:0] = COMPN[3:0]. Hence, the pull-up and pull-down calibration codes, RCODEP[3:0] and RCODEN[3:0], respectively, are ready to be distributed to all the I/O drivers in the chip.

3.4.3.2 Output swing control scheme

The proposed configurable I/O driver in current-mode can support output swing V_SWING of 400 and 500 mV. However, actual output swing can vary and deviate from the desired swing level, V_SWING, which can cause sampling error at the far-end receiver. This is mainly due to the variation of the tail current across PVT variations and also the symmetric error between biasing circuit and tail current sources. Output swing control scheme is implemented by the I-COMP block in the PVT-compensation block to calibrate the tail current so that the driver output swing can be maintained at V_SWING ± 5%. In I-COMP, a dummy driver stage is used as a compensation with one of the input transistor, which is turned-off, to allow current from both the tail current sources flow to another input transistor to the two pull-down terminators, as shown in Figure 17. Pull-down terminators are calibrated by pull-down code RCODEN[3:0] from R-COMP block and one of them is a dummy receiver terminator to emulate the situation where the driver is operating with double terminations. VOUT is compared to the reference voltage VREF (can be 400 or 500 mV) and the dynamic legs inside the pull-up segment will be adjusted by ICOMP FSM to increase or decrease the current amount that flow to the pull-down terminators and thus, controlling output swing at VREF. The compensation process is similar to impedance compensation in R-COMP block. When compensation for pull-down segment is done, LOCKN signal will be generated by PDN FSM to kick-off the output swing compensation process for the pull-up segment. If the VOUT is lower than VREF, which implies that there is insufficient current from tail transistors in pull-up segment, then the comparator will output UD with logic high for U/D Counter to count up the COMP[3:0]. This increases the number of dynamic legs in the pull-down segment so as to increase the tail current, as well as the VOUT voltage. This searching process will continue until VOUT is alternating about VREF and UD is toggling, then the pattern catcher will output a lock signal (LOCK) to 4-bit hold-register to hold the calibration code at ICODE[3:0] = COMP[3:0].

Figure 17.
Current compensation I-COMP block.

In this work, the design technique of I-COMP is similar with R-COMP (see Figure 16). The bias voltage VBIAS is constant from global current-mirror circuit and the dynamic legs are adjusted to calibrate the amount of current from tail current source, thereby calibrating output swing at the desired level. Moreover, ICODE[3:0] is a digital code that is insensitive to noises and this ensures the calibration information will not be impacted during delivery to other current-mode drivers for output swing calibration. This is different from technique proposed by Ref. [24] where the bias voltage ISOURCE from IDAC is delivered to local bias generators in all current-mode drivers. This noise-sensitive analog bias voltage, ISOURCE, in combination with different PVT variations in each local bias generator might result in large deviation on the output swing of each current-mode driver. Thus, the advantage of I-COMP in this work is the use of digital calibration technique to avoid the digital calibration codes from being impacted by noises and PVT variations.

3.4.4 Delay line architecture

3.4.4.1 Slew rate control scheme

Output slew rate control scheme is applied in the proposed I/O driver. Digital time domain splitting technique is used since the proposed I/O driver requires a stable control of slew-rate and output impedance. Figure 18a shows a diagram of a driver module designed using time split technique (simplified from Figure 6). The output driver in each driver module is segmented into four driver stages and the switching time of these driver stages is controlled through a delay line that consists of delay cells with Td delay interval. By activating each driver stage in sequence, output transition time can be controlled. The pull-up and pull-down impedance in each driver stage is controlled at four times larger than the desired module impedance Z (150 Ω), hence, the effective output impedance is always constant at 50 Ω when three driver modules are switching together. The output slope depends on interval Td as shown in Figure 18b. Moreover, the driving single-ended output swing can be 500 mV in differential voltage-mode driver and 400 or 500 mV in the current-mode driver. More detailed information about a delay line can be found in Ref. [41].

Figure 18.
Time split technique: (a) simplified diagram of one driver module with delay line, and (b) controlled output slew rate.

As the delay across each delay cell is controlled at 40 ps, the output transition time can be controlled approximately at 160 ps, as depicted in Figure 18b. However, this limits the output driver from operating beyond 4 Gbps because the controlled output rise and fall transition time is occupying large fraction of the one bit-pulse duration, which can cause sampling errors at the far-end receiver. Thus, slew rate control scheme is only applied to applications with data rates below 4 Gbps. For data rate higher than 4 Gbps, the delay cells should be bypassed so that the output transition is no longer restricted by the delay intervals, although this could not help in reducing switching noise. However, as the output driver operates at higher data rates over long transmission channel, ISI noise start dominating switching noise and de-emphasis control scheme should be activated to reduce ISI-induced jitter and thus, improving signal integrity. Figure 19 shows the architecture of delay line (Delay Line 1 and Delay Line 2 in Figure 6) where multiplexers act as bypass circuit. A multiplexer is added at the output of each delay cell and controlled by signal BYPASS. When BYPASS is low, the multiplexers select output of delay cells for driver stages in the configurable I/O drivers. If BYPASS is high, delay cells are bypassed and the multiplexers select IN1 and IN2 for all the driver stages.

Figure 19.
(a) Structure of delay line in Figure 6 with delay bypass circuit, (b) multiplexer circuit using current-starved inverter [39], and (c) macro-model of multiplexer.

Moreover, Figure 19a shows the circuit implementation of multiplexer that is designed based on the topology of current-starved inverter [42] while Figure 19b shows the macro-model of multiplexer. The merit of this topology is to allow faster switching at higher data rates since the current sources in current-starved inverter can quickly charge or discharge voltage in each internal node.

3.4.4.2 De-emphasis control scheme

When the I/O driver operates at higher data rates over long transmission channel, ISI becomes significant and de-emphasis control scheme should be activated to compensate the ISI impacts on signal eye jitter and eye height. Figure 20 shows the generic idea of integrating de-emphasis scheme into the proposed configurable I/O driver. Similar to the basic concept of de-emphasis, the first three driver stages in a driver module can be connected as main tap driver while the last driver stage is connected as de-emphasis tap driver.

Figure 20.
Generic idea of integrating de-emphasis scheme into the proposed I/O driver.

Moreover, in order to drive the main tap driver and de-emphasis tap driver with the corresponding ordinary data (IN1[n] and IN2[n]) and inverted one bit shifted data (IN1n−1¯ and IN2n−1¯), the delay line structure in Figure 19a must be modified accordingly. Figure 21 shows the structure of delay line modified from Figure 19a to support de-emphasis control scheme. A multiplexer, MXEQ, with selector signal, EQ_ON, is added at the output path of multiplexer MX4 for the de-emphasis tap driver. When de-emphasis is required, BYPASS is set to high so that multiplexer MX1, MX2 and MX3 outputs ordinary data IN1[n] and IN2[n] to the main tap drivers, while EQ_ON is also set to high for multiplexer MXEQ to outputs inverted one bit shifted data IN1n−1¯ and IN2n−1¯ to the de-emphasis tap driver. The de-emphasis ratio of the proposed configurable I/O driver can be calculated as −20 log [(3–1)/(3 + 1)] ≈ 6 dB [43]. In addition, the advantage of this de-emphasis driver is that it has a constant de-emphasis of 6 dB that is independent of output impedance. This is because, the de-emphasis ratio is only dependent on the number of instances in the main tap and post-cursor tap driver, while the output impedance is constant by calibrating the driver stage only. This gives a constant de-emphasis across PVT variations as compared to pre-emphasis transmitter proposed by Ref. [43], where the number of instances in the main tap and post-cursor tap driver are not always constant due to the need of output impedance tuning.

Figure 21.
Structure of delay line modified from Figure 19a to support de-emphasis control scheme.

3.5 Layout implementation

The research development moves forward to layout implementation once the proposed I/O driver is successfully designed and simulated. Post-layout simulations are then performed to ensure the layout parasitic do not significantly affect the I/O driver performance. Layout parasitic in configurable I/O driver are more critical when compared to other digital blocks like delay lines, driver controller and FSMs in PVT-compensation block, hence, this work only includes the configurable I/O driver in the layout implementation. Figure 22 demonstrates the layout snapshot of the configurable I/O driver from Figure 6. The configurable I/O driver consists of three driver modules with each module divided into four driver stages. The total layout area is 312 × 196 μm2.

Figure 22.
Layout of configurable I/O driver with three driver modules (Figure 6).

Also, during layout implementations, practical layout techniques like transistor splitting, symmetrical placement and transistor drain-source sharing are implemented into the I/O driver layout. This is because improper layout techniques in I/O driver can cause large layout parasitic that reduces the maximum operating speed of I/O driver. By applying transistor splitting technique, a single large transistor is split into smaller parallel transistors and this effectively reduces the parasitic resistance of transistor gate; thus, improving transistor switching speed for I/O driver. Additionally, differential current-mode driver is high performance analog circuit with matched devices in PMOS differential pair in driver stage (Figure 10a). Thus, it is necessary to place PMOS differential pair symmetrically for symmetric routing and matched parasitic [44]. Moreover, transistor drain-source sharing allows transistors to be placed as rectangle as possible that helps to compact and optimize layout area.

3.6 Test-bench setups

In this work, simulation flows are divided to two parts which are pre- and post-layout simulations. The circuit blocks in Figure 6 are used as top-level test-bench for pre-layout performance verifications. After the configurable I/O driver is designed and simulated successfully, the I/O driver is implemented into layout. Similar to pre-layout simulations, the post-layout simulations also use the circuit in Figure 6 as top-level test-bench, but the parasitic of I/O driver layout (see Figure 22) are extracted and loaded into PRESTO simulator to validate the design of configurable I/O driver especially for high data rate at 8 Gbps.

4. Post-layout results, discussions and challenges

This section discusses the post-layout simulation results in details. Simulation results of the output impedance and the output swing (current-mode driver) will be presented, followed by the discussions of the output slew rate and de-emphasis. Consequently, comparison and discussion between pre- and post-layout simulations will be presented.

4.1 On-chip calibration results

This section presents the on-chip calibration results for R-COMP and I-COMP across PVT variations. These PVT variations include the variation of process between fast, typical and slow corner; variation of supply voltage between 1.0 V ± 5%; and variation of temperature between 0, 50and 110°C.

4.1.1 R-COMP results

It is necessary to ensure that the driver stage impedance matched with a 600 Ω reference resistor to provide output impedance of 150 Ω per driver module. Thus, the proposed chip I/O design can be configured as output driver with output impedance of 50 Ω by enabling three driver modules during transmitting mode or configured as receive-ODT by enabling one, two or three driver modules to provide output impedance of 150, 75 or 50 Ω during receiving mode, respectively. Figure 23a and b shows the impedance range of pull-down and pull-up for one driver stage across PVT variations. Obviously, by controlling the four-bit binary-weighted dynamic legs, it is sufficient to control the driver stage pull-up and pull-down impedance at 600 Ω across PVT variations through the use of appropriate calibration code generated by the R-COMP.

Figure 23.
Driver stage impedance across calibration codes at different PVT corners for (a) pull-up impedance, and (b) pull-down impedance.

It can be noticed that the impedance value in Figure 23 is quantized across the calibration codes. R-COMP can select one of the two possible quantized impedances that are slightly higher or lower than 600 Ω. The difference between the quantized impedance and desired impedance is called impedance error. The percentage of maximum impedance error can be calculated. For instance, at typical condition (process: typical, voltage: 1.0 V and temperature: 50°C), calibration code 7 and code 8, provides pull-up impedance of 620.5 and 590.5 Ω, with percentage impedance error of 3.42 and −1.58% respectively. Moreover, Figure 24 depicts the errors of maximum impedance for pull-up and pull-down impedance of the driver stage. It can be seen that the maximum impedance errors are less than ±5% across PVT variations and this is in agreement with the design requirements stated in Table 1. Besides, driver linearity is one of the design criteria in high speed communications. Ideally, the driver linearity should be 100% which implies that the output impedance is always constant across operating output voltages. Nevertheless, in reality the output impedance diverge from desired value across output voltages owing to non-linear characteristic of the transistor in both the pull-up and pull-down segment.

Figure 24.
Maximum impedance error of driver stage that is calibrated at 600 Ω across PVT variations.

The graph of linearity errors of 600 Ω pull-up and pull-down impedance across operating voltages is shown in Figure 25. It can be noticed that the linearity errors are lower than the specification which is ±15% (see Table 1). Moreover, it can be seen that the pull-up impedance linearity error in Figure 25a is worst at low output voltages. This is because, the PMOS transistor in pull-up segment (see main driver in Section 3.4.1) is operating in non-linear region. This is the same reason for pull-down impedance worst linearity error at higher output voltages (Figure 25b) since the NMOS transistor in pull-down segment is not operating in linear region. In fact, linearity error can be reduced by increasing the series resistance against the transistor impedance in pull-up and pull-down segment in main driver in Figure 7. However, this requires larger transistor size that gives smaller transistor impedance to balance the increase of series resistance in order to keep output impedance at constant.

Figure 25.
Linearity errors of 600 Ω across output voltages at different PVT corners for (a) pull-up impedance, and (b) pull-down impedance.

Moreover, larger transistor size can contribute to higher output pad capacitance that limits the driver data rates. Therefore, this is a compromise between linearity error and pad capacitance. Low linearity error across operating voltages helps to fully absorb any reflection from far-end but it also contributes to high pad capacitance that will slow down the slope of output and limit data transfer rates [45].

4.1.2 I-COMP results

When the proposed driver is configured as a current-mode driver, the output swing can be calibrated at desired level across different PVT corners. The impedance of the pull-down terminator of the current-mode driver is calibrated at 50 Ω (with three driver modules) through the calibration codes generated from R-COMP. Figure 26a and b shows the range of single-ended output swing of the current-mode driver over the calibration codes. Undoubtedly, by controlling the four-bit binary-weighted dynamic legs in the pull-up segment, the tail can be adjusted and calibrated at 400 and 500 mV with suitable calibration codes provided by I-COMP. It is critical to calibrate output swing at a fixed level throughout various corners to ensure the signal eye height is always sufficient for far-end receiver detection to avoid data sampling errors [24].

Figure 26.
Output swing of current-mode driver can be calibrated by calibration codes for (a) 400, and (b) 500 mV.

Similar to output impedance discussed in the previous sub-section, it can be noticed that the output swing of current-mode driver is quantized across calibration codes (Figure 26) due to the discrete change of dynamic legs number. There are two possible quantized output swings which are slightly higher and lower than desired output swing. Thus, the difference between the quantized output swing and desired output swing can be called output swing error. The maximum output swing errors of less than ±5% across PVT variations were obtained and this fulfills the design requirement stated in Table 1.

4.1.3 Calibration results

On-chip impedance and output swing (in current-mode driver) are calibrated by adjusting the 4 bit-dynamic legs in the pull-up and pull-down segment of a driver stage. The impedance of pull-up segment is first calibrated, followed by impedance calibration of pull-down segment and output swing calibration (for current-mode driver). Figure 27 shows the calibration sequences in R-COMP and I-COMP block for worst condition (slow transistor skew, 0.95 V supply voltage and 110°C temperature). The reference voltage, VREF, is half of the supply voltage i.e. 0.475 V. The waveform labels correspond to the voltage nodes in Figures 16 and 17. The driver pull-up impedance will be first calibrated by R-COMP (see Figure 16a). At t = 0 in Figure 27a, the VOUTP is lower than VREF which implies pull-up impedance is larger than reference resistor. This delta voltage will cause the comparator to output a high signal for U/D counter to increase the number of dynamic legs in the pull-up segment to rise the VOUTP voltage. When VOUTP is approaching and alternating about VREF, the PUN FSM will assert a lock signal LOCKP to hold the pull-up codes in the register at t = 70 ns, as shown in Figure 27d, to indicate that the pull-up impedance calibration process is completed by PUN FSM. In addition, this LOCKP signal also will kick-off the pull-down impedance calibration block with the pull-up segment and this becomes the reference impedance (see Figure 16b). At t = 70 ns in Figure 27b, VOUTN is higher than VREF and the dynamic legs in pull-down segment will be activated through the codes from U/D counter to lower the VOUTN. This search process will continue until VOUTN is alternating about VREF and the PDN FSM issues a lock signal LOCKN at t = 130 ns in Figure 27d as indication of calibration completed and to hold the pull-down codes in register. Once the pull-down impedance is calibrated with LOCKN signal asserted at t = 130 ns as shown in Figure 27d, the LOCKN will kick-off output swing calibration in I-COMP block (see Figure 17). Therefore, in Figure 27c, it can be noticed that the driver output VOUT becomes lower than output swing reference VREFi (e.g. 400 mV) after I-COMP block activated at t = 130 ns. This implies the current from pull-up segment is insufficient and the delta voltage will cause FSM in I-COMP to increase more dynamic legs to provide more current to raise up the VOUT approaching VREFi. When VOUT is alternating about VREFi, a lock signal LOCK is generated by FSM to store the codes into register at t = 220 ns, as shown in Figure 27d. This indicates that the calibration process is completed and all the codes that are held in register can be distributed to all the output drivers.

Figure 27.
Calibration process: (a) VOUTP in pull-up impedance calibration, (b) VOUTN in pull-down impedance calibration, (c) VOUT in output swing calibration, and (d) locks signal for pull-up, pull-down impedance and output swing.

4.2 Output slew rate results

As discussed in Section 3.3 and 3.4.4.1, the delay cells in a delay line 1 and delay line 2 shall be designed to provide interval Td that is controlled at 40 ps across PVT variations to guarantee a controllable output slew rate at 2–4 V/ns. This can be achieved by controlling the 4-bit binary delay code DCODE[3:0] in the delay cell to control the delay across each delay cell at 40 ps. Figure 28a shows that the delay range across a delay cell can be controlled at 40 ps through the delay calibration code DCODE[3:0]. Similar to impedance and output swing, the change of delay is discrete across the calibration code and this causes the quantization error to alternate between 40 ps. The difference between quantized delay and desired delay is the delay error.

Figure 28.
(a) Delay range of a delay cell with 4-bit dynamic transistor, and (b) percentage of maximum delay error from 40 ps across PVT variations.

The percentages of maximum delay error are less than ±5% which shows the delays across each delay cell are well-controlled at 40 ps so that the output slew rates are controllable within 2–4 V/ns, as discussed in the following sub-sections.

4.2.1 Output slew rate of voltage-mode driver

By setting the appropriate delay calibration code to delay cells, the slew rates of configurable I/O driver are controlled at 2–4 V/ns for voltage-mode and current- mode driver configuration. Figure 29a shows the near-end output waveform of a differential voltage-mode driver (Figure 9a) with 50 Ω driving impedance and 50 Ω far-end terminator to ground, simulated at data rate of 1 Gbps in typical condition. In addition, it can be noticed that the output waveform is a sort of staircase, similar to Figure 18b because each driver stage is activated in sequence to control the output transition time. Moreover, the output swing in Figure 29a is 500 mV. This resulted from voltage divider between near-end driver impedance and far-end terminator. Besides, Figure 29b shows the near-end output slew rates (measured from 20 to 80% of output swing) from 0.4–4.0 Gbps for different PVT corners. Obviously, output slew rates in Figure 29b can be controlled between 3.17–3.72 V/ns which meet the design requirements stated in Table 1. However, slew rate control scheme is bypassed to avoid restricting the output transition times for data rates above 4.0 Gbps (Figure 19a). Moreover, the output slew rate of single-ended driver (Figure 8) configured from the proposed configurable I/O driver is not shown in this sub-section due to the fact that both single-ended and differential voltage-mode driver are having same output slew rate, except that the output signaling is different in the form of single-ended or differential only.

Figure 29.
(a) Near-end output of differential voltage-mode driver, (b) near-end output slew rate of differential voltage-mode driver across PVT corners from 0.4–4.0 Gbps.

Figure 30 shows the comparison between conventional voltage-mode driver without slew rate control and proposed driver with slew rate control simulated with package model. By enabling slew rate control, the proposed driver can reduce the maximum overshoot to 5.6% while the phase margin is improved from 50.1° to 63.8° and thus, giving a more stable and functional system. The reason to measure maximum overshoot at far-end is to ensure that the proposed I/O driver is capable of reducing ringing effect and avoid amplitude distortions that will cause sampling errors in the far-end receivers. Moreover, it can be observed that the slope of far-end output of the proposed driver become smooth in Figure 30 as compared to its step-like near-end output in Figure 29a. This is because a lossy transmission channel has low-pass effect that filters the high-frequency components in the near-end output, thereby giving smoother slope of far-end output.

Figure 30.
Far-end output comparison between conventional voltage-mode driver and the proposed differential voltage-mode driver with slew rate control.

4.2.2 Output slew rate of current-mode driver

Differential current-mode driver in Figure 10 also designed with controllable slew rate at 2–4 V/ns. Figure 31a and b show the near-end output waveforms of a differential current-mode driver with output swing of 400 and 500 mV (controlled by I-COMP block) respectively, simulated at 1 Gbps and typical condition. In addition, Figure 32a and b depict the near-end output slew rates (measured from 20 to 80% of output swing) for 400 and 500 mV output swing respectively, simulated from 0.4–4.0 Gbps for different PVT corners. The output slew rates in Figure 32a and b are controlled at 2.32–2.62 V/ns and 2.85–3.33 V/ns with calculated variation of 12.4 and 16.8%, respectively. Clearly, the output slew rates in Figure 32a and b can meet the targeted slew rate (Table 1). The slew rates in Figure 32a are generally smaller than that in Figure 32b due to smaller output swing since the output slew rate is the rate of change of output swing.

Figure 31.
Near-end output waveform differential current-mode driver with output swing controlled at (a) 400, and (b) 500 mV.

Figure 32.
Near-end output slew rate of differential current-mode driver across PVT corners from 0.4–4.0 Gbps, with output swing of (a) 400, and (b) 500 mV.

Moreover, Figure 33 shows the comparison between conventional current-mode driver without slew rate control and proposed driver in current-mode with slew rate control simulated with package model. In Figure 33a, the 400 mV conventional current-mode driver has ringing with peak value at 476.9 mV on far-end output. Furthermore, the maximum overshoot and phase margin are calculated as 19.2% and 48.9°. Figure 33a, the proposed current-mode driver can reduce the peak ringing to 412.6 mV, while the maximum overshot and phase margin are improved to 3.15% and 67.2°, respectively. Also, in Figure 34b, there is peak ringing of 565.2 mV on the far-end output from a 500 mV conventional current-mode driver with the corresponding maximum overshoot and phase margin computed as 13.0% and 55.2°. The current-mode driver configured from the proposed driver with output swing of 500 mV is capable of reducing the far-end peak ringing and maximum overshoot to 508.2 mV and 1.64% and hence, giving better phase margin at 69.6° as compared to that from conventional current-mode driver. Also, from the results shown in Figure 33a and b, it can be noticed that the smaller output swing and slower slew rate are better in reducing output ringing. However, for data rate above 4.0 Gbps, slew rate control should be bypassed as slower slew rate is limiting driver data rates.

Figure 33.
Far-end output comparison between conventional driver and current-mode driver with slew rate control with output swing of (a) 400, (b) 500 mV.

Figure 34.
Near-end output waveform of two single-ended voltage-mode drivers at OUT1 pin, (b) OUT2 pin.

4.3 Output de-emphasis results

4.3.1 Voltage-mode de-emphasis

The proposed configurable I/O driver can support wide range of data rates from 0.4 to 8 Gbps, as stated by the specifications in Table 1. Single-ended voltage-mode driver (Figure 8) is designed to support data rates from 0.4 up to 4.0 Gbps, while differential voltage-mode driver (Figure 9) can support data rates from up to 8.0 Gbps due to the merit of differential signaling. Figure 34 shows two near-end output waveforms when the proposed configurable I/O driver is configured as two single-ended drivers with 50 Ω driving impedance and 50 Ω far-end terminator, simulated at 4.0 Gbps in typical condition with slew rate control scheme activated.

Moreover, 6 dB de-emphasis control scheme is programmable and can be activated for long transmission channel and higher data rates (e.g. above 4.0 Gbps) since the frequency dependent attenuations of transmission channel become significant and cause ISI problem. Figure 35a and b demonstrate the differential output waveform of voltage-mode driver without and with de-emphasis. The differential voltage-mode driver is simulated at 8 Gbps in typical condition with 50 Ω driving impedance and 50 Ω far-end pull-down terminator.

Figure 35.
Differential output waveform of voltage-mode driver at 8 Gbps (a) without de-emphasis, and (b) with de-emphasis.

4.3.2 Current-mode de-emphasis

Differential current-mode driver (Figure 10) configured from the proposed configurable I/O driver also supports de-emphasis scheme up to 8.0 Gbps. Figure 36a shows the differential output waveform of current-mode driver with single-ended swing calibrated at 400 mV while Figure 36b shows the differential output waveform of current-mode driver with 6 dB de-emphasis at 8 Gbps in typical condition.

Figure 36.
Differential output waveform of 400 mV current-mode driver at 8 Gbps (a) without de-emphasis, and (b) with de-emphasis.

Figure 37a shows the differential output waveform of 500 mV current-mode driver while Figure 37b shows the differential output of 500 mV current-mode driver with 6 dB de-emphasis at 8 Gbps in typical condition.

Figure 37.
Differential output waveform of 500 mV current-mode driver at 8 Gbps (a) without de-emphasis, and (b) with de-emphasis.

4.4 I/O driver de-emphasis performance at high data rates

The ISI is frequency and transmission channel length dependent. Thus, post-layout simulations in this work are focusing on maximum data rate at 8 Gbps. Moreover, two typical short and long transmission channel length in MCM (10 mm and 50 mm) will be used to verify the de-emphasis performance. At short channel, ISI impacts are not significant and the de-emphasis scheme (Section 3.4.4.2) can be bypassed. However, as ISI impacts become dominant at longer channel, de-emphasis scheme can be activated to equalize the channel attenuations, thereby improving far-end signal integrity as discussed in the following sub-sections.

4.4.1 Output driver performance at short transmission channels

When the proposed configurable I/O driver is placed in the package with short transmission channels i.e. 2.5–10 mm, de-emphasis scheme is bypassed since short channel will not lead to high attenuation on outputs. Figure 38 shows the far-end differential eye signal of voltage-mode and current-mode driver in typical condition, simulated at 8 Gbps with 10 mm transmission channel. In Figure 38a, voltage-mode driver has eye jitter and eye height of 0.08 UI and 793.8 mV. Moreover, Figure 38b shows the 500 mV current-mode driver has eye jitter and eye height of 0.06 UI and 850.6 mV, while Figure 38c shows the eye jitter and eye height of 400 mV current-mode driver measured at 0.06 UI and 687.2 mV.

Figure 38.
Far-end differential eye without de-emphasis, simulated for (a) voltage- mode driver, (b) 500 mV current-mode driver, and (c) 400 mV current-mode driver.

It can be seen that all the three drivers have sufficient inner eye opening that are larger than the specifications stated in Table 1, where 500 mV current-mode driver has better eye jitter and height performance.

4.4.2 I/O driver performance at long interconnects

When the proposed configurable I/O driver is operated with longer transmission channel up to 50.0 mm, the de-emphasis control scheme has to be activated to allow adequate eye opening at high data rates. Figure 39a shows the far-end differential eye diagram of voltage-mode driver without applying de-emphasis at 8 Gbps in typical condition. The eye jitter and eye height are 0.50 UI and 226.9 mV respectively. Large eye jitter due to long transmission channel can cause receiver sampling errors.

Figure 39.
Far-end differential eye waveform of voltage-mode driver at 8 Gbps and 50 mm transmission channel, simulated (a) without de-emphasis, and (b) with de-emphasis.

Therefore, de-emphasis scheme should be activated to equalize the attenuations of transmission channel. Figure 39b depicts the far-end differential eye diagram of voltage-mode driver simulated at 8 Gbps with de-emphasis. The eye jitter and eye height are improved to 0.29 UI and 312.8 mV, which are large enough for timing and amplitude budgets of far-end receiver (Table 1).

Figure 40a shows the far-end differential eye diagram of 500 mV current-mode driver at 8 Gbps, typical condition and 50 mm transmission channel without applying de-emphasis. The eye jitter and eye height are 0.47 UI and 316.7 mV which are better than that in voltage-mode driver without de-emphasis (Figure 39a). By applying 6 dB of de-emphasis, the far-end differential eye opening is improved with eye jitter and eye height of 0.26 UI and 367.5 mV respectively, as demonstrated in Figure 40b. Thus, after applying de-emphasis, the eye jitter and eye height are improved to meet the timing and amplitude budgets of far-end receiver, as mentioned in Table 1.

Figure 40.
Far-end differential eye of 500 mV current-mode driver at 8 Gbps and 50 mm transmission channel, simulated (a) without de-emphasis, and (b) with de-emphasis.

Figure 41a shows the far-end differential eye diagram of 400 mV current-mode driver simulated with 8 Gbps and 50 mm transmission channel without de-emphasis. The eye jitter and eye height are 0.46 UI and 254.3 mV. By applying de-emphasis, the far-end differential eye opening is improved with eye jitter and eye height of 0.27 UI and 277.8 mV respectively, as shown in Figure 42b.

Figure 41.
Far-end differential eye of 400 mV current-mode driver at 8 Gbps and 50 mm transmission channel, simulated (a) without de-emphasis, and (b) with de-emphasis.

Figure 42.
(a) Comparison of output transient response between voltage-mode driver and 500 mV current-mode driver, simulated at 8 Gbps in typical condition, and (b) current-mode driver with stable source voltage at VS1 and VS2.

In Figures 39 and 40, it can be noticed that 500 mV current-mode driver has better eye jitter and eye height performance as compared to voltage-mode driver due to the fact that current-mode driver has faster transient response, as shown in Figure 42a. Generally, the output voltage of both the drivers at high data rates depend on the charging and discharging of the capacitance at internal and output nodes. Current-mode driver has stable source voltages VS1 and VS2 where the node capacitance is always charged-up by tail currents to constant voltage level, as shown in Figure 42b. For instance, when output node OUT is driving a logic high (when data D is low), a total current of 2I_b is charging the capacitance at the node between transistor M3 and resistor R1 and output node. This reduces transistor turned-on time as compared to voltage-mode driver where every single node capacitance including output node has to be charged-up along the pull-up branch. Thus, current-mode driver has faster transient response, giving larger eye opening when compared to voltage-mode driver. To avoid sampling errors for the applications that require low jitter, it is suggested to configure the proposed output driver into current-mode driver at the expense of slightly higher power consumption as shown in the graph of average power performance in Figure 43.

Figure 43.
Comparison of average power between voltage-mode driver, 400 and 500 mV current-mode driver, simulated at 8 Gbps and typical condition.

In Figures 40 and 41, the 500 mV current-mode driver has similar eye jitter but higher eye height as compared to 400 mV current-mode driver. The eye jitter is almost identical because both of them has same driving impedance and far-end terminators that matches the transmission channel characteristic impedance. Thus, no additional jitters due to signal reflections for both of the current-mode drivers. However, 500 mV current-mode driver has higher eye height due to its higher output swing. Therefore, for high performance applications that need higher voltage margin or eye height to avoid wrong data logic detection, it is suggested to configure the proposed I/O driver into 500 mV current-mode driver instead as 400 mV current-driver, at the expense of slightly higher power consumption. If voltage margin is not a concern, then the 400 mV current-mode driver should be configured to avoid overhead of power consumption (Figure 43).

4.4.3 ODT performance with 50, 75 and 150 Ω impedance

When receiving data from the far-end driver, the proposed configurable I/O driver can be configured as near-end receive ODT with 50, 75 or 150 Ω by enabling the corresponding number of driver modules, as discussed in Section 3.4.1.3. Figure 44a shows the near-end eye diagram of 50 Ω ODT when it terminates the output transmitted by far-end 8 Gbps I/O driver through 10 mm of transmission channel. The 50 Ω ODT is well-matched to the transmission channel impedance and the simulated jitter and eye height are 0.10 UI and 571.2 mV, respectively.

Figure 44.
Near-end signal eye with ODT value of (a) 50, (b) 75, and (c) 150 Ω, simulated at 8 Gbps and transmission channel length of 10 mm.

Consequently, 75 and 150 Ω ODT can be configured as near-end termination for power saving purposes at the expense of eye jitter, because 75 and 150 Ω ODT are not matched with transmission channel impedance and this causes reflection noise, as shown by the eye diagram in Figure 44b and c. Eye jitter is increased to 0.18 UI and 0.29 UI for 75 and 150 Ω ODT, respectively. However, eye heights are improved to 612.1 and 633.2 mV for 75 and 150 Ω ODT due to the fact that the output swing increases with larger ODT impedance. Nevertheless, in overall, the eye opening is still sufficient for data detection and sampling. In addition, Figure 45 demonstrates the graph of average power consumption for ODT impedance of 50, 75 and 150 Ω, simulated at 8 Gbps. It can be noticed that the average power of near-end ODT is reducing with larger ODT impedance. Hence, 75 and 150 Ω ODT can be configured for low power applications, while 50 Ω ODT should be selected to terminate reflection noises in high performance applications.

Figure 45.
Average power consumption of ODT value of 50, 75, and 150 Ω.

4.5 Performance summary

This section summarizes and compares the simulated signal eye jitter and eye height between pre-layout and post-layout simulations with 50 mm transmission channel. Figure 46a demonstrates the eye jitters measured from pre-layout and post-layout for differential voltage-mode and current-mode driver with de-emphasis, simulated with data rate of 8 Gbps and 50 mm transmission channel in typical condition. Also, Figure 46b depicts the pre-layout and post-layout simulated eye height (8 Gbps and typical condition) for voltage-mode and current-mode drivers. Thus, the eye jitter and eye height show good agreement between pre- and post-layout since the variations between them are less than 4%.

Figure 46.
Pre-layout and post-layout simulations of voltage-mode and current-mode drivers on (a) eye jitters, and (b) eye heights.

Table 4 shows the performance summary of the proposed configurable output driver. Different impedance value i.e. 50, 75 or 150 Ω can be selected for near-end ODT. Overall, the output slew rates of differential voltage-mode driver and current-mode driver can be controlled within targeted value at 2–4 V/ns. Moreover, after applying de-emphasis on the differential outputs at 8 Gbps, it can be found that the current-mode driver has better eye jitter and eye height performance when compared to voltage-mode driver. Although current-mode driver has better eye opening at 8 Gbps, but its average power consumption is slightly higher than that in the voltage-mode driver. This shows the performance trade-off between signal eye opening and power consumption. Current-mode driver can be configured for high performance signaling system due to its advantage of reducing ISI impacts at the cost of slightly higher power consumption. On the other hand, voltage-mode driver is suggested for low power system due to the merit of lower power consumption as compared to current- mode driver.

		Specifications in Table 3	Voltage- Mode	Current-Mode (500 mV)	Current-Mode (400 mV)
Process technology		—	45 nm CMOS
Silicon area (three driver modules)			312 × 196 μm²
Operating speed			0.4–8 Gbps
Operating VCC			1.0 V ± 5%
Worst impedance error (%)		± 5 Max.	4.76
Worst impedance linerity error (%)		± 15 Max.	14.80
Worst output swing error (%)		± 5 Max.	—	−0.96	1.49
Output slew rate (V/ns)		2.0–4.0	3.17–3.72	2.85–3.33	2.33–2.62
Typical average power (mW)	50 Ω ODT	—	5.40
	75 Ω ODT		4.98
	150 Ω ODT		4.05
	50 Ω Driver		25.64	29.36	26.03
Driver without de-emphasis (at 8 Gbps, 50 mm of TL)	Eye jitter (UI)	0.30 Max.	0.50	0.47	0.46
Driver without de-emphasis (at 8 Gbps, 50 mm of TL)	Eye height (mV)	200.0 Min.	226.90	316.70	254.30
Driver with de-emphasis (at 8 Gbps, 50 mm of TL)	Eye jitter (UI)	0.30 Max.	0.29	0.26	0.27
Driver with de-emphasis (at 8 Gbps, 50 mm of TL)	Eye height (mV)	200.00 Min.	312.80	367.50	277.80
Signal eye improvement with 6 dB de-emphasis	Eye jitter (%)	—	42.32	44.68	41.30
	Eye height (%)	—	37.86	16.04	9.24

Table 4.

Performance summary of configurable I/O driver at 8 Gbps.

4.6 Performance comparison with other works

The performance comparison between the proposed configurable I/O driver and other output driver results from literatures is shown in Table 5.

		This work			References
		Voltage-mode driver	Current-mode driver		[39]	[46]
Process technology		45 nm CMOS			65 nm CMOS	90 nm CMOS
Supply voltage (V)		1.0			1.0	1.2
Driver mode		Multi-mode			Single mode	Single mode
Data rate (Gbps)		0.4–8.0			10.0	2.0–6.0
Output swing (mV) output		500	500	400	400	100–400
Swing control		None	Yes	Yes	Yes	None
Output swing variation (%)		None	−0.96	1.49	8.20	—
Slew rate (V / ns)		3.17–3.72	2.85–3.33	2.33–2.62	3.11–3.77	—
Slew rate variation (%)		17.35	16.84	12.45	21.2	—
Driver de-emphasis		Yes	Yes	Yes	None	Yes
Without	Eye jitter (UI)	0.50	0.47	0.46	—	0.41
De-emphasis	Eye height (mV)	226.9	316.7	254.3	—	87.0
With	Eye jitter (UI)	0.29	0.26	0.27	—	0.28
De-emphasis	Eye height (mV)	312.8	367.5	277.8	—	146.0
Eye opening	Eye jitter (%)	42.32	44.68	41.3	—	31.71
Improvement	Eye height (%)	37.86	16.04	9.24	—	67.82

Table 5.

Performance comparison with other published works.

From Table 5, the 500 and 400 mV current-mode driver configured from the proposed configurable I/O driver have better output swing control with variation of −0.96 and 1.49% respectively, as compared to 8.2% swing variation in the output driver presented by Ref. [39]. Moreover, by controlling the output swing at almost constant level, the output slew rate is automatically controlled between 3.11–3.77 V/ns with variation of 21.2% as summarized in Table 5 [39]. Yet, the slew rate control scheme in this work allows the slew rates of the configurable I/O driver to become less sensitive to PVT variations. The slew rate of voltage-mode driver, 500 mV current-mode driver and 400 mV current-mode driver has smaller PVT variation at 17.35, 16.84 and 12.45% respectively.

From Table 5, the transmitter in Ref. [46] has better capability of improving 67.8% of eye height when compared to the drivers from proposed configurable I/O driver even though the eye height of each driver is larger than 200 mV. In addition, it can be noticed that the eye jitters of voltage-mode driver, 500 mV current-mode driver and 400 mV current-mode driver without de-emphasis are larger than 0.41 UI in Ref. [46] due to the use of different transmission channel length. However, the configurable I/O driver can reduce 42.3, 44.7 and 41.3% of eye jitter for the corresponding voltage-mode driver, 500 mV current-mode driver and 400 mV current-mode driver, respectively, when compared to 31.7% in Ref. [46]. This shows that the proposed configurable I/O driver with de-emphasis control scheme has better capability in eye jitter reduction at high data rates.

5. Conclusion

In this work, we have demonstrated the fundamentals, methodologies, and challenges of chip I/O design with the design of a configurable I/O driver supporting wide range of data rates from 0.4 to 8.0 Gbps. The proposed configurable I/O driver can be configured between two single-ended voltage-mode drivers, a differential voltage-mode driver and a differential current-mode driver to address electronic signaling mismatches between chips, thereby achieving maximum performance across a variety of processor-intended applications. Moreover, four control schemes, namely, impedance control, output swing control, slew rate control and de-emphasis control scheme are embedded into configurable I/O driver design to improve signal integrity especially at high data rates. Through the impedance control scheme, output impedance is calibrated at 50 Ω for driver as well as 50, 75 and 150 Ω for ODT, with worst impedance error at 4.76%. The output swing of current-mode driver can be controlled by output swing control scheme at 400 and 500 mV with worst output swing errors of −0.96 and 1.49% respectively. Besides, the slew rate control scheme can slow down the slew rate of configurable I/O driver to 2–4 V/ns to address switching noises. The output slew rate of voltage-mode driver, 400 mV current-mode driver and 500 mV current- mode driver can be controlled at 3.17–3.72 V/ns, 2.33–2.62 V/ns and 2.85–3.33 V/ns, respectively. With de-emphasis control scheme, the voltage-mode driver, 500 mV current-mode driver and 400 mV current-mode driver are capable of reducing far-end eye jitter by about 42.3, 44.7 and 41.3%. The 500 mV current-mode driver has relatively larger far-end eye opening, but it consumed extra 12.7% of average power as compared to voltage-driver. Thus, with the four digital schemes mentioned above that forms the auxiliary control, the proposed configurable I/O driver is capable of supporting multiple signaling types while improving signal integrity at high frequency data transmissions, thereby enhancing chip-to-chip performance to boost the performance of electronic devices like computers and mobile phones for better consumer experiences.

G. Díaz González

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