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Power Reduction Using Efficient Way of Tri-State Buffer Connection

Written By

Maan Hameed

Submitted: December 2nd, 2021Reviewed: January 12th, 2022Published: April 17th, 2022

DOI: 10.5772/intechopen.102643

IntechOpen
New Advances in SemiconductorsEdited by Alberto Adriano Cavalheiro

From the Edited Volume

New Advances in Semiconductors [Working Title]

Dr. Alberto Adriano Cavalheiro

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Abstract

Clock gating is a very important technique for decreasing wasted power in digital design. One of the approaches to obtain dissipated power is an intention by the way of masking the clock pulse that is going to the unused part of the design. In this research, a comparative evaluation of current clock gating techniques on synchronous digital design changed into provided. In the new suggested design, the gated clock technology circuit is a use of tri-state buffer and gated clock. The new submodule was created by the connection of two tri-state logic used as switched to control to the design. The new suggested technique was saving more power and area. The suggested sub-module was achieved by using ASIC design methodologies. In order to implement Huffman modules, the architecture of the proposed module has been generated using Verilog HDL language. In addition, it is proved using Modalism-Altera 10.3c (Quartus II 14.1) tools. By using the tri-state technique, dynamic power and total power are decreased. The suggested technique will decrease the hardware complexity.

Keywords

  • tri state buffer
  • VLSI
  • Xilinx
  • glitches
  • hazards

1. Introduction

Incorporated Lap (ICS) terminus, normally indicate to surely chips or microchips, became accompanied with the aid of the want to test these designs. Small weighing device integrating (SSI) design, with tens of digital transistor in the early time of the 60s, and Medium Scale Leaf of size integration (MSI) system of policies, with a large quantity of digital transistor inside the overdue time 1960s, had been comparatively clean to test [1]. Moreover, within the 1970s, massive-scale integration (LSI) innovation, with a big range of transistors, generate some difficulties while experimenting with these designs. In the early time of 80s, a very-large-scale integration (VLSI) sample with a big range of transistors was explained. Enhance the caliber in VLSI designs have done in designs with hundreds of millions of transistors [2]. One of the primary dissipated ethical pressure exponents reduced by the clock gating approach, in calculating electronics ware inside the ordinary machine’s gated clock. Then, decrease by 30–70% of the entire dynamic electricity dissipation. Similarly, lowering the general gadget strength to 15-xx% of grouping somersault fall apart statistics pushed the clock gating approach [3]. A gated clock may be a very crucial way of lowering the clock signal. Essentially, while clocked the common-sense social unit, it is relying upon the sequential parameter that receives the clock signal, one after the other, they may transfer within the subsequent HZ whether its miles demanded or now not. The facts driven clock gating designs figuring out allowing clock indicators are manually brought for every FF as a part of the proposed design methodology [4]. With the aid of the usage of the clock gating method, the fair sports clock sign is and with explicitly predefined allowing sign. Clock gating is appointed at all ground of electrical circuit, good judgment design, block layout, and gate [5]. Sundry ways to pick gain of this approach are defined, with all of them based on unique heuristic application in a looking to increase clock gating opportunities. With the quick ontogeny in gadget of regulations complexity. Laptop-aided layout (cad) tool supporting device stage-ironware-description has often been realized. Additionally, grow gadget output, every contraption wants the body of work of the long mountain variety of computerized synthesis algorithms, from register-switch-degree (RTL) right down to the netlist and gate-level. Sadly, such automation leads to a massive wide variety of unused toggling. Consequently, developing the dissipated clock at flip-flops as defined in this studies chapter [6].

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2. Dynamic energy

Wasted power is created when the system is changing from a natural state to the next state or when switch ON. Changing power of one gate can be explained in the Eq. (1):

PDynamic=CLV2DDfE1

where the parameter (f) represents the clock frequency, the parameter (CL) represents the switching capacitance, while the parameter (VDD) represents the voltage source. Finally, decreasing the dynamic power consumption can be calculated by the way of decreasing one of the parameters in the Eq. (1) [7].

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3. Reducing of dynamic power

Leakage power is the lowest amount of power dissipation in digital design, growing significantly every year with modern techniques. Dynamic power is the largest amount of power dissipation in the digital design, and still control all the power dissipated in the system. Therefore, the efficient techniques to drop off the dissipated dynamic power contain the size of the transistor, gated clock, multiple provision potential interconnect optimization, and dynamic control of supply voltage. Incorporating the above methods in the system of nanoscale system, the dynamic power consumption can be decreased significantly [8].

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4. Clock gating

Clock gating is the efficient method used to decrease the power consumption in a synchronous system. In an ideal digital design like the general target microprocessor, part of the design is active only at any specific time. Therefore, by switching off the idle part of the design, the unused power dissipation can be saved. The most important approach to realize this goal by cutting a clock signal that goes to the unnecessary part of the design. This way stops unused clocking of the inputs to the idle system module [9].

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5. Proposed technique

In this text, we will talk about the new device that will keep much area and power as proved in Ref. [10]. The brand-new signal named gated clock is shown inside the next determine later by means of including tri-nation connection and device of the logic gate is employed that is generated by way of the gathering of double-gated (and, or, and) with bubbled input sign sequent. On this conception, maintain baron in each case that even the truthful recreation designing is activated. The ascendance gadget clock is off, in summation when the specified design is clock off, and then additionally controlling twist’s clock is off. This method appearing can maintain lots of energy by way of averting unused switching at the clock net. This clock gating is on at posedge and rancid at negedge stated clock electricity and dynamic power is maintaining on the jail time period of negedge clock. In the traditional state, the design works by applying a CLK signal controlled by enable signal (E-N).

Clear to understand the working of design in the original state from RTL, viewer for Huffman with PMC as shown in Figures 1 and 2.

Figure 1.

RTL viewer for Huffman with PMC.

Figure 2.

Power management control (PMC) design.

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6. Tri-state logic

This section explains the way of low power Huffman design using a tri-state buffer. By using tri-state buffer, significantly reduced the wasted power. Basically, tri-state logic is used as a switch and controlled by enable signal, named as Enable Signal (EN) as shown in Figure 3. In tri-state buffer, if en = 1, that led to appear the input data at the output of the tri-state buffer. In other word, encoder on and decoder off. But if en = 0, then opposite the process encoder off and decoder on. Also, input value would not appear at the output. Clearly, the process details are shown in Figure 4. In this work, tri-state buffer property is used to decrease the power dissipation of Huffman [11]. It performs various processes during the execution in modules block. At one particular time, one method was performed [12]. Even as, all different approaches (which are not select), consumes clock baron at the same time. This can leash dynamic power dissipation.

Figure 3.

Clock gating techniques.

Figure 4.

Tri-state connection.

The problem is overcome with the usage of the tri-country buffer. Therefore, at the time one technique can carry out via Huffman, whilst all different operations are in tri-state high impedance z nation. In this example, it’s miles feasible to put in force circuit with the assist of tri-kingdom good judgment. That results in carrying out the most effective one operation at one plus time, that is selection enter for selected the target method [6]. Moreover, the other operations are remaining in a high impedance Z state. In other word, these operations cannot access to output or connect to the output. The path of passing clock signals in different cases is presented in Figures 5 and 6, respectively. The way of execution using tri-state logic is shown in Figure 4. Where the implementation processes with tri-state as the way of the clock signal. If en = 1, then the clock signal will be appearing at the decoder output. But when the en signal is set to 0 as shown in Figure 4, clock input will be an appearance at the encoder output because an inverter makes en input 0 to input 1. So, it deeds as an out-of-doors circuited route [13]. This could make sure that Huffman modules cognitive manner, handiest one module is chosen at a time and carried out, while the relaxation of cognitive procedure are in tri-nation [14]. Figure 5 shows Power Management Control (PMC) validation. While the full Huffman waveform validations is presented in Figure 6.

Figure 5.

Power management control (PMC) validation.

Figure 6.

Huffman waveform validations.

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7. Validations and behavioral simulation

Quartus II 14.1 (Sixty-Four-Bit) web version is used to enforce Huffman. Furthermore, Modelsim-Altera 10.3c (Quartus II 14.1) is used to carry out behavioral simulation and validation [4]. Validation software is used for the behavioral simulation and tested the Huffman layout with exceptional values of entering and in all conditions. Huffman layout is behaving according to the specs. Figures 5 and 6 show the behavior of the waveform simulation of Huffman with the new tri-state logic design, in addition to the behavioral of tri-state design. Clear to observe that, how the new circuit switches had one process ON and the other process OFF. Figure 6 shows the validation of the input and output signals for Huffman with tri-state logic technique [15].

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8. Resource utilization

In Figure 7, the resource utilization summary is shown. In this chapter, tri-state logic is used to control Huffman design. In this technique, encoder and decoder Huffman operations are implemented. Moreover, logic operations are achieved too. This will lead to less resource usage. After the compilation, synthesis is executed. Quartus II 14.1 (64-bit) internet version illustrated RTL schematic of Huffman. The RTL schematic is received, the device usage of the layout with tri-kingdom good judgment is proven under.

Figure 7.

Flow summary results of Huffman.

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9. Conclusion

Last of all, in this research the new suggested design will preserve more area and power. The most important aspect of this newspaper writer is to expand a new clock signal approach and improve the performance of the virtual design. The boom in dynamic essential multi-millionaire consumption makes the employer unreliable so that you could ascendency the dynamic transfer strength numerous techniques are studied to reduce it. A new tri-nation-based totally clock technique is proposed to reduce energy dissipation. Comparative analysis shows that the proposed approach affects the dynamic strength. All the analyses are done on Huffman design with process variation parameters. As concluded from the simulation waveform summarized in the figure above, the suggested technique deals with tri-state as a switch, not register. That’s means switch used to pass the signal only. This fulfilled the purpose of this wok, reduction in power consumption. Finally, the performance evaluation of the various modules is carried out using Modalism-Altera 10.3c (Quartus II 14.1), which is used to perform behavioral simulation and validation, the circuits designed using tri-state logic showed a reduced power. As a future work, a reversible divider can also be designed and included in this design.

References

  1. 1.George L, Bangde P. Design and implementation of low power consumption 32-bit ALU using FPGA. International Journal for Research in Emerging Science and Technology. 2014;1(5):64-68
  2. 2.Kathuria JA, Ayoub M, Khan M, Noor A. A review of clock gating technique. MIT International Journal of Electronics and Communication Engineering. 2011;1(2):106-114
  3. 3.Paul BC, Agarwal A, Roy K. Low power design techniques for scaled technologies. Integration, the VLSI Journal. 2006;39(2):64-89
  4. 4.Mohammed MH, Khmag A, Rokhani FZ, Ramli AB. VLSI implementation of Huffman design using FPGA with a comprehensive analysis of power restrictions. International Journal of Advanced Research in Computer Science and Software Engineering. 2015;5(6):49-54
  5. 5.Chaudhary H, Goyal N, Sah N. Dynamic power reduction using clock gating: A review. IJECT International Journal of Electronics & Communication Technology. 2015;6(1):22-26
  6. 6.Dokic B. A review on energy efficient CMOS digital logic. ETASR—Engineering Technology & Applied Science Research. 2013;3(6):552-561
  7. 7.Kawa J. Low power and power management for CMOS—An EDA perspective. IEEE Transactions on Electron Devices. 2008;55(1):186-196
  8. 8.Raghavan N, Akella V, Bakshi S. Automatic insertion of gated clocks at register transfer level. In: International Conference on VLSI Design. 1999. pp. 48-54
  9. 9.Soni DK, Hiradhar A. A review on existing clock gating. International Journal of Computer Science and Mobile Computing. 2015;4(3):371-382
  10. 10.Hameed M, Mogheer HS, Razak I. Low power text compression for Huffman coding using Altera FPGA with power management controller. In: 2018 1st International Scientific Conference of Engineering Sciences IEEE—3rd Scientific Conference of Engineering Science (ISCES). 2018
  11. 11.Hameed M, Khmag A, Rokhani FZ, Ramli AB. CMOS technology using clock gating techniques with tri-state buffer. Walailak Journal of Science and Technology. 2017;14(4)
  12. 12.Hameed M, Rokhani FZ, Ramli AB. Low power approach for implementation of Huffman coding for high data compression. International Journal of Advances in Electronics and Computer Science. 2015;2(12)
  13. 13.Karakehayov Z. Model-driven clock frequency scaling for control-dominated embedded systems. International Journal of Computing. 2014;7(2):100-107
  14. 14.Hameed M, Khmag A, Rokhani FZ, Ramli AB. A new lossless method of Huffman coding for text data compression and decompression process with FPGA implementation. Journal of Engineering and Applied Sciences. 2016;11(3):402-406
  15. 15.Hameed M, Mogheer HS, Mansour A. Power reduction using high speed with saving mode clock gating technique. In: Paper Presented at the 2nd International Scientific Conference of Engineering Sciences (ISCES 2020). IOP Conference Series Materials Science and Engineering. Vol. 1076. Iraq: University of Diyala; 2021. p. 012055. DOI:10.1088/1757-899X/1076/1/012055

Written By

Maan Hameed

Submitted: December 2nd, 2021Reviewed: January 12th, 2022Published: April 17th, 2022