Open access peer-reviewed chapter

Transconductor

Written By

Ko-Chi Kuo

Published: April 1st, 2010

DOI: 10.5772/8634

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1. Introduction

The transconductor is a versatile building block employed in many analog and mixed-signal circuit applications, such as continuous-time filters, delta-sigma modulators, variable gain-amplifier or data converter. The transconductor is to perform voltage-to-current conversion. Linearity is one of most critical requirements in designing transconductor. Especially in designing delta-sigma modulators for high resolution Analog/Digital converters, it needs high linearity transconductors to accomplish the required signal-to-(noise+distortions) ratio. The tuning ability of transconductor is also mandated to adjust center frequency and quality factor in filter applications.

The portable electronic equipments are the trend in comsumer markets. Therefore, the low power consumption and low supply voltage becomes the major challenge in designing CMOS VLSI circuitry. However, designing for low-voltage and highly linear transconductor, it requires to consider many factors. The first factor is the linear input range. The range of linear input is justified by the constant transconductance, Gm. Since the distortion of transconductor is determined by the ratio of output currents versus input voltage. The second factor is the control voltage of transconductor. This voltage can greatly impact the value of transconductance, linear range, and power consumption. For example, when the control voltage increases, the transconductance also increase but the linear input range of transconductor is reduced and power consumption is increased. Hence it is critical in designing transconducotr operated at low supply voltage. The third factor is the symmetry of the two differential outputs. If the transconductance of the positive and negative output is Gm+=IO+/Viand Gm−=IO−/Vi, then how close Gm+and Gm−should be is a critical issue, where IO+is the positive output current, IO−is the negative output current, and Viis the input differential voltage. This factor is the major cause of common-mode distortion of transconductor which occurs at outputs.

In general, the design of differential transconductor can be classified into triode-mode and saturation-mode methods depending on operation regions of input transistors. Triode-mode transconductor has a better linearity as well as single-ended performance. On the other hand, saturation-mode transconductor has better speed performance. However, it only exhibits moderate linearity performance. Furthermore, the single-ended transconductor of saturation-mode suffers from significant degradation of linearity. Several circuit design techniques for improving the linearity of transconductors have been reported in literatures. The linearization methods include: source degeneration using resistors or MOS transistors [Krummenacher & Joeh, 1988; Leuciuc & Zhang, 2002; Leuciuc, 2003; Furth & Andreou, 1995], crossing-coupling of multiple differential pairs [Nedungadi & Viswanathan, 1984; Seevinck & Wassenaar, 1987] class-AB configuration [Laguna et al., 2004; Elwan et al., 2000; Galan et al., 2002], adaptive biasing [Degrauwe et al., 1982; Ismail & Soliman, 2000; Sengupta, 2005], constant drain-source voltages [Kim et al., 2004; Fayed & Ismail, 2005; Mahattanakul & Toumazou, 1998; Zeki, 1999; Torralba et al., 2002; Lee et al., 1994; Likittanapong et al., 1998], pseudo differential stages [Gharbiya & Syrzycki, 2002], and shift level biasing [Wang & Guggenbuhl, 1990].

Source degeneration using resistors or MOS transistors is the simplest method to linearize transconductor. However, it requires a large resistor to achieve a wide linear input range. In addition, MOS used as resistor exhibits considerable varitions affected by process and temperture and results in the linearity degradation. Crossing-coupling with multiple differential pairs is designed only for the balanced input signals. The Class-AB configuration can achieve low power consumption. On the other hand, the linearity is the worst due to the inherited Class-AB structure. The adaptive biasing method generates a tail current which is proportional to the square of input differential voltage to compensate the distortion caused by input devices. However, the complication of square circuitry makes this technique hard to implement. The constant drain-source voltage of input devices is a simple structure. It can achieve a better linearity with tuning ability. However, it needs to maintain VDSof input devices in low voltage and triode region. Therefore, this technique is difficult to implement in low supply voltage. Hence, a new transconductor using constant drain-source voltage in low voltage application is proposed to achieve low-voltage, highly linear, and large tuning range abilities.

In section 2, basic operatrion and disadvantage of the linerization techniques are described. The proposed new transconductor is presented in section 3. The simulation results and conclusion are given in section 4 and 5.

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2. Linearization techniques

In this section, reviews of common linearization techniques reported in literatures are presented. The first one is the transconductor using constant drain-source voltage. The second one is using regulated cascode to replace the auxiliary amplifier. The third one is transconductor with source degeneration by using resistors and MOS transistors. The last one is the linear MOS transconductor with a adaptive biasing scheme. Besides introducing their theories and analyses, the advantages and disadvantages of these linearization techniques are also discussed.

2.1. Transconductor using constant drain-source voltage

The idea of transconductors using constant drain-source voltages is to keep the input devices in triode region such that the output current is linearized. The schematic of this method is shown in Figure 1. Considering that transistors M1, M2 operate at triode region, M3, M4 are biased at saturation region, channel length modulation, body effect, and other second-order effects are ignored, the drain current of M1 and M2 is given by

ID=β[(VGSVT)VDSVDS22]E1

where β =μnCOX(W/L), VGSis the gate-to-source voltage, VTis the threshold voltage, and VDSis the drain-to-source voltage. If the two amplifiers in Figure 1 are ideal amplifiers, then

VDS1=VDS2=VCE2

Figure 1.

Transconductor using constant drain-source voltage

The transfer characteristic of this transconductor is given by

Iout1=β[(VGS1VT)VDS1VDS122]=β[(VGS1VT)VCVC22]Iout2=β[(VGS2VT)VDS2VDS222]=β[(VGS2VT)VCVC22]Iout=Iout1Iout2=βVC(Vin1Vin2)E3

The transconductance value is

Gm=βVCE4

In fact, it is difficult to design an ideal amplifier implemented in this circuits. However, it can force VDS1=VDS2 =VDSby using two auxiliary amplifiers controlled with the same VCto keep VDSat the constant value. Therefore, the transfer characteristic of this transconductor is changed as follows:

Iout1=β[(VGS1VT)VDS1VDS122]=β[(VGS1VT)VDSVDS22]E5
Iout2=β[(VGS2VT)VDS2VDS222]=β[(VGS2VT)VDSVDS22]Iout=Iout1Iout2=βVDS(Vin1Vin2)E6

where VGS1= Vin1 and VGS2= Vin2.

Therefore, the new transconductance value is

Gm=βVDSE7

The linearity of this transconductor is moderated. It is also easy to implement in circuit. However, VDSof the input devices must be small enough to keep transistors in triode region. The following condition has to be satisfied:

VDSVGSVTE8

On the other hand, the auxiliary amplifiers need to design carefully to reduce the overhead of extra area and power.

2.2. Transconductor using regulated cascode to replace auxiliary amplifier

In Figure 2(a) regulating amplifier keeps VDSof M1 at a constant value determined by VC. It is less than the overdrive voltage of M1. The voltage can be controlled from VCso as to place M3 in current-voltage feedback, thereby increasing output impedance. The concept is to drive the gate of M3 by an amplifier that forces VDS1to be equal to VC. Therefore, the voltage variations at the drain of M3 affect VDS1to a lesser extent because amplifiers “regulate” this voltage. With the smaller variations at VDS1the current through M1 and hence output current remains more constant, yielding a higher output impedance [Razavi, 2001]

RoutAgm3rO3rO1E9

Figure 2.

a)Basic triode transconductor structure (b) Simple RGC triode transconductor

It is one of solutions using regulated cascode to replace the auxiliary amplifier in order to overcome restrictions on Figure 1. The circuit in Figure 2(b) proposed in [Mahattanakul & Toumazou, 1998] uses a single transistor, M5, to replace the amplifier in Figure 2(a). This circuit called regulated cascode which is abbreviated to RGC. The RGC uses M5 to achieve the gain boosting by increasing the output impedance without adding more cascode devices. VDS1is calculated by follows: Assuming M5 is in saturation region in Figure 2(b). It can be shown that

IC=12β5(VGS5VT)2VGS5=VDS1VC=2ICβ5+VT5VDS1=VC+2ICβ5+VT5E10

From (6)Gm=β1VDS1=β1(VC+2ICβ5+VT5). Thus, Gmcan be tuned by using a controllable voltage source VCor current source IC. However, it is preferable in practice to use a controllable voltage source VCfor lowering power consumption since VDS1only varies as a square root function of IC.

Simple RGC transconductor using a single transistor to achieve gain boosting can reduce area and power wasted by the auxiliaryamplifiers. However, it still has some disadvantages. First, it will cause an excessively high supply-voltage requirement and also produce an additional parasitic pole at the source of transistors. Therefore, it can not apply to the low-supply voltage design. Second, the tuning range ofVDS1is restricted. The smallest value of VDS1is2ICβ5+VTwhen VC= 0. In other words, VDS1can not be set to zero. Owing to the restriction of (7), VDSis as low as possible and the best value is zero. Third, VTdependent Gmmay be a disadvantage due to the substrate noise and VTmismatch problems [Lee et al., 1994].

In Figure 3, another RGC transconductor that can apply to the low-voltages applications is proposed in [Likittanapong et al., 1998]. The circuit overcomes the disadvantages mentioned above is to utilize PMOS transistor that can operate in saturation region as gain boosting. The use of this PMOS gain boosting in the feedback path can result in a circuit with a wide transconductance tuning range even at the low supply voltage. In [Likittanapong et al., 1998], it mentions that at the maximum input voltage, M3 may be forced to enter triode region, especially if the dimension of M2 is not properly selected, resulting in a lower dynamic range. Besides, β2may be chosen to be larger for a very low distortion transconductor. It means that the tradeoff between linearity and bandwidth of transconductor is controlled by β2Therefore, β2should be selected to compromise these two characteristics for a given application.

VDS1is calculated by follows. Assuming M3 is in saturation region in Figure 3.

IC=12β3(VGS3VT3)2VGS3=VCVDS1=2ICβ3+VT3VDS1=VC(2ICβ3+VT3)E11

From (6)Gm=β1VDS1=β1[VC(2ICβ3+VT3)]It shows that VDS1can be set to zero whenVC=2ICβ3+VT3Therefore, this transconductor has a wider tuning range compared to that of RGC transconductor and is capable of working in low-supply voltage (3V). However, this transconductor still has some drawbacks. The major drawback is the tuning ability. For example, it is difficult to controlVC=2ICβ3+VT3if VDS1is set to zero. The minor drawback is that VTdepends on the Gm. It also may cause substrate noise and VTmismatch problems [Lee et al., 1994].

Figure 3.

RGC transconductor with PMOS gain stage

2.3. Transconductor using source degeneration

A simple differential transconductor is shown in Figure 4(a). Assuming that M1 and M2 are in saturation and perfectly matched, the drain current is given by

ID=β2(VGSVT)2E12

The transfer characteristic using (5) is given by

Iout=Iout1Iout2=2βISSVi1βVi28ISS=2βISSVi1Vi24(VGSVT)E13

where Vi= (V in1 −V in2)

If VGSis large enough, the higher linearity can be achieved. Unfortunately, it can not be used in the low-voltage application and the linear input range is limited. Simplest techniques to linearize the transfer characteristic of MOS transconductor is the one with source degeneration using resistors as shows in Figure 4(b). The circuit is described by

ViRIout=VGS1VGS2E14

A transfer characteristic derived from (13) is given by

Iout=2βISS(ViRIout)1β(ViRIout)28ISSE15

The transconductance Gmis

Gmgm1+gmRE16

where gmis the transconductance of transistor M1 and M2.

We should notice that in (14), the nonlinear term depends on Vi − RIoutrather than Vi. Higher linearity can be achieved whenR >> 1/gm. The disadvantage of this transconductor is that large resistor value is needed in order to maintain a wider linear input range. Owing toGm1/R, the higher transconductance is limited by the smaller resistor. Hence, there is a tradeoff between wide linear input range and higher transconductance which is mainly determined by a resistor.

Figure 4.

a) Simple differential MOS transconductor (b) MOS transconductor with resistive source degeneration

Another method to linearize the transfer characteristic of MOS transconductor is using source degeneration to replace the degeneration resistor with two MOS transistors operating in triode region. The circuit is shown in Figure 5. Notice that the gates of transistor M3 and M4 connect to the differential input voltage rather than to a bias voltage. To see that M3 and M4 are generally in triode region, we look at the case of the equal input signals (Vin1=Vin2), resulting in

Vx=Vy=Vin1VGS1E17

Therefore, the drain-source voltages of M3 and M4 are zero. However, VDSof M3 and M4 equal those of M1 and M2. Owing to (7), M3 and M4 are indeed in triode region. Assuming M3, M4 are operating in triode region, the small-signal drain-source resistance of M3, M4 is given by

rds3=rds4=1β3(VGS1VT)E18

It must be noted that in this circuit the effect of varying VDSof M1 and M2 can not be ignored since the drain currents are not fixed to a constant value. The small-signal source resistance of M1, M2 is given by

rs1=rs2=1gm1=1β1(VGS1VT1)E19

Using small-signal T model, the small-signal output current, io1, is equal to

io1=Vin1Vin2rs1+rs2+(rds3||rds4)io1=2β1β3β1+4β3(VGS1VT1)(Vin1Vin2)E20

Assuming M1 is in saturation region, the drain current of M1 is given by

ISS=12β1(VGS1VT1)2(VGS1VT1)=2ISSβ1E21

Using (20) substitutes for (19), that leads to

io1=2β1β3β1+4β32ISSβ1(Vin1Vin2)E22

The transconductanceGmis

Gm=2β1β3β1+4β32ISSβ1E23

Linearity can be enhanced (assuming rds3>> rs1) compared to that of a simple differential pair because transistors operated in triode region exhibits higher linearity than the source resistances of transistors operated in saturation region. When the input signal is increased, the small-signal resistance in one of two triode transistors in parallel, M3 or M4, is reduced. Meanwhile, the reduced resistance results in the lower linearity and the larger transconductance. As discussed in [Krummenacher & Joeh, 1988], if the proper size ratio ofβ13is chosen, the balance between higher linearity and stable transconductance can be achieved. How to choose the optimum size ratio of β13for the best linearity performance becomes slightly dependent on the quiescent overdrive voltage, VGS−VT.The size ratio of β13=6.7 is used to achieve the best linearity performance.

According to (22), the transconductance can be tuned by changing ISSand size ratio of β13. Nevertheless, the nonlinearity error is up to 1% for Iout /ISS< 80%. It is required to have a better linearity so as to achieve a THD of -60 dB or less in some filtering applications [Kuo & Leuciuc, 2001].

Figure 5.

Transconductor with source degeneration using MOS transistors

2.4. Transconductor using adaptive biasing

The transconductor using adaptive biasing is shown in Figure 6. All transistors are assumed to be operated in saturation region, neglecting channel lengh modulation effect. First, transistor M3 is absent, and output current as a function of two input voltages Vin1and Vin2is obtained as

I1=β2(VGS1VT)2I2=β2(VGS2VT)2Iout=I1I2=βISS(Vin1Vin2)1β(Vin1Vin2)24ISSE24

where ISSis a tail current and equals IB.

An adaptive biasing technique is using a tail current containing an input dependent quadratic component to cancel the nonlinear term in (23). Consequently, the circuit in Figure 6 changes the tail current by adding transistor M3. The tail current will be changed by

ISS=IB+ICE25
IC=β4(Vin1Vin2)2E26

where IBis tail current of differential pair and ICis the compensating tail current that cancel nonlinear term.

Therefore, the transfer characteristic is changed by

Iout=βISS(Vin1Vin2)E27

Figure 6.

Transconductor with adaptive biasing

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3. New transconductor

The conventional structure which uses the constant drain source-voltage such as RGC with NMOS or PMOS can not operate at 1.8V or below. The main reason is that auxiliary amplifier under the low supply voltage can’t provide enough gain to keep the constant drain-source voltage. Therefore, we propose a triode transconductor which uses new structure to replace the auxiliary amplifier. Figure 7 shows the proposed triode transconductor structure.

MOS M5, M7, M9 and M11 are made up a two-stage amplifier to replace the auxiliary amplifier. The two-stage amplifier is implemented using M9 with the active loads M11 formed the first stage and M5 with the active load M7 formed the second stage. The first and second stages exhibit gains equal to

A1=gm9(gm91||rO11)E28
A2=gm5(rO5||rO7)E29

Figure 7.

Proposed triode transconductor

Therefore, the overall gain is

Av=A1*A2=gm9(gm91||rO11)gm5(rO5||rO7)E30

The proposed transconductor is shown in Figure 8.

Figure 8.

The proposed transconductor

Considering that the large gain is achieved and is able to keep transistors M1 and M2 in triode region, the drain current of M1 and M2 is given by

Iout1=β1[(VGS1VT1)VDS1VDS122]E31
Iout2=β2[(VGS2VT2)VDS2VDS222]E32

The transfer characteristic is given by

Iout=Iout1Iout2=β1VDS1(Vin1Vin2)E33

whereβ1 = β2, VT1=VT2, and VDS1=VDS2. Assuming that current I9 flows from M11 through M9 and MOS M9 is in saturation region, VDS1can be found in (33)

VGS3+VDS1=VDS7VCVT7=VDS7VGS3+VDS1=VCVT7VDS1=VCVT7VGS3E34

According to (32)

Iout=β1VDS1(Vin1Vin2)=β1(VCVT7VGS3)(Vin1Vin2)E35

The transconductance Gm is

Gm=β1(VCVT7VGS3)E36

From (35), the transconductance can be tuned by control voltage VCTo keep M1 and M2 in triode region, the relation (36) needs to be satisfied.

VDS1VGS1VT1E37

Using (33) to substitute (36)

VCVT7VGS3VGS1VT1=VCVGS1+VGS3(VT1VT7)E38

The proposed transconductor is suitable for low supply voltage and we choose 1.8V to achieve a wide linear range. Moreover, M9 is needed to obtain a negative feedback to keep the drain-source voltage of M1, VDS1, constant. This new structure can provide enough gain to keep VDS1 constant at 1.8V supply voltage. It has a low control voltage VC between 0.69V~0.72V and the large transconductance tuning range depending on applications. Besides, it has a simple structure so as to save area.

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4. Simulation results

The circuits in Figure 8 have been designed by using TSMC CMOS 0.18μm process with a single 1.8V supply voltage and simulated by Hspice. Figure 9. shows the curve of input voltage transferring to the output current at VC= 0.7V. The slope of the curve is linear when the input voltage varies from −1V to 1V. The slope in Figure 9. is equal to the transconductance in Figure 10. In order to verify the performance of the proposed transconductor, we define transconductance error (Equation 39) as the linearity of the transconductance’s output current. The transconductance error is less than 1% among ±0.9V input voltage, so the input linear range is up to 1.8V.

TE(%)=Gm(Vid)Gm(0)Gm(0)*100E39

Figure 9.

V-I transfer characteristic

Figure 10.

The simulated transconductance at VC=0.7V

In Figure 11. it shows the drain-source voltage of the input transistors M1 and M2, VDS1 and VDS2, changes with the input voltage. Within ±1V input voltage, VDS1 and VDS2 are very small. According to equation (40), VDS1 and VDS2 are too small such that transistors M1 and M2 can be set in triode region. Once the input voltage exceeds ±1V, VDS1 and VDS2 will increase rapidly. It results in that transistors M1 and M2 enter in saturation region. In other words, when M1 and M2 entering saturation region the proposed transconductor can not maintain the high linearity.

VDSVGSVTE40

When VC is set between 0.69V and 0.72V, the linear input range is up to 2.6V and the transconductance error is less than 1%. The smallest transconductance is 3.4μs and linear input range is 1.2V when VCis 0.720V. The highest transconductance is 542μs and linear input range is 1.4V when VCis 0.690V. Table 1 shows the linear input range and the transconductance tuned by different VC. Therefore, the proposed transconductor achieve a large tuning range.

Figure 11.

The drain-source voltage of input transistor M1 and M2

V C (V)Linear input range (V)Transconductance (µS)
0.6901. 4542
0.6951.8434
0.7001.8326
0.7052.2219
0.7102.4122
0.7152.642
0.7201.23.4

Table 1.

VCversus Linear input range

In Figure 12., the simulated THD as a function of the input frequency and input signal amplitude is plotted. The best THD is achieved at the low input voltage and the low frequency. When VCis 0.7V, the linearity of the proposed transconductor is less than −60dB for 0.7Vpp at 100KHz.

Figure 12.

Simulated THD for different input frequencies

Figure 13. shows the linearity of transconductor in three linearization techniques. The transconductor using source degeneration with resistor is shown in Figure 4(b), and the transconductance in Figure 13(a) is tuned by different resistors. The transconductor using source degeneration with MOS transistors is shown in Figure 5, and the transconductance in Figure 13(b) is tuned by the different size ratio of β1/β3. The transconductor using adaptive biasing is shown in Figure 6, and the transconductance in Figure 13(c) is tuned by the different compensating tail current, IC. Figure 14. Shows the simulation result of the proposed technique and other techniques. Figure 14(a) is the full plot of the different linearization techniques. From Figure 14(b) it can be easily seen that the linearity achieved by the newly proposed technique is better than all other implementations.

Figure 13.

Simulated transconductance of three linear transconductors (a) Source degeneration using resistor (b)Source degeneration using MOS transistors (c)Adaptive biasing

Figure 14.

Simulated transconductance for four linearization techniques (a) Full plot (b) Detail

The simulated THD of the output differential current versus the input signal amplitude for the four linearized transconductors is plotted in Figure 15. The proposed transconductor achieves THD less than −61dB for the 0.7Vpp input voltage, 11dB better than the one using source degeneration using resistor, 24dB better than the one using source degeneration using MOS, and 31dB better than the one using adaptive biasing, at the same input range.

Table 2. shows the power consumption of the four linearized transconductors at the same transconductance. Power consumption changes with the different transconductances. Therefore, the same transconductance is chosen to be compared in each configuration. Table 3. shows different power consumption at the different transconductance of the proposed transconductor.

Figure 15.

Simulated THD at 1MHz for the four linearized transconductors

Source degeneration using MOSSource degeneration using resistorAdaptive biasingProposed
Power (mW)1.3 11.191.381. 58

Table 2.

The power consumption of four linearized transconductors

V C (V)Power (mW)G m (µA/V)
0.6901.759542
0.6951.7 14434
0.7001.5 86326
0.7051.4 42219
0.7101.2 63122
0.7150. 9 5442
0.7200.7333.4

Table 3.

The power consumption at different transconductances

Table 4. shows the comparison of performance with other transconductors at the low supply voltage (under 2V). The transconductor in [Fayed & Ismail 2005] also uses constant drain-source voltage. It modifies the basic structure of constant drain source voltage and uses the moderate amplifier. The proposed transconductor modifies the auxiliary amplifiers to obtain high gain under low supply voltage.

The layout including proposed transconductor, Common Mode Feedback, and bandgap is shown in Figure 16. The proposed transconductor uses STC pure 1.8V linear I/O library in 0.18μm CMOS process. The chip area is 0.516mm2.

[Galan et. al 2002][Leuciuc & Chang 2002][Laguna et. al 2004][Sengupta 2005][Fayed & Ismail 2005]Proposed
Process0.8µm0.25µm0.8µm0.18µm0.18µm0.18µm
Power supply2V1.8V1.5V1.8V1.8V±10%1.8V
THD-40dB @10MHz-80dB, 0.8Vpp, @2.5MHz-33dB, 0.2Vpp, @5MHz-65dB, 1Vpp, @1MHz-50dB, 0.9Vpp, @50KHz- 60 dB, 0.7Vpp, @1 00KH z
G m (µA/V)0.6~207200~60067~1557705~1103.4 ~ 542
Linear input range0.6Vpp1.4Vpp0.6Vpp1Vpp1.8Vpp2.4 Vpp
Year20022002200420052005200 9

Table 4.

Comparison table

Figure 16.

The layout of proposed transconductor

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5. Conclusion

The proposed low-voltage, highly linear, and tunable triode transconductor achieves the wide linear input range up to 2.4V. The total harmonic distortion is −60dB with a 0.7Vpp input voltage. The design uses TSMC 0.18μm CMOS technology and supply voltage is 1.8V. Moreover, it exhibits a large Gm tuning range from 3.4μS to 542μS and also keeps a wide linear input range. Finally, the performance comparison with other linear techniques shows that the proposed technique achieves better linearity, wider tuning range, and wider linear input range.

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Acknowledgments

This work was supported in part by the National Science Council, Taiwan, ROC, under the grants: NSC 97-2221-E-110-078.

References

  1. 1. DegrauweM. G.RijmenantsJ.VittozE. A.1982Adaptive biasing CMOS amplifiers,IEEE Journal of Solid-State Circuits,173(June 1982)522528,0018-9200
  2. 2. ElwanH.GaoW.SadkowskiR.IsmailM.2000A low voltage CMOS class AB operational transconductance amplifier,Electronics Letters,3617(Aug. 2000)14391440,0013-5194
  3. 3. FayedA. A.IsmailM.2005A low-voltage, highly linear voltage-controlled transconductor,IEEE Transactions on Circuits and Systems : I Express Briefs,5212(Dec. 2005)831835,1549-7747
  4. 4. FurthK. M.AndreouA. G.1995Linearised differential transconcutors in subthres-hold CMOS,Electronics Letters,317(March 1995)15761581,0013-5194
  5. 5. GalanA.CarvajalR. G.MunozF.TorralbaA.Ramirez-AnguloJ.2002Design of linear CMOS transconduct- ance elements,IEEE Proceedings of International Sympoisum of Circuits and Systems,2912,0-78037-448-7Scottsdale, Arizona, U.S.A, May 2002, Institute of Electrical and Electronics Engineers, Piscataway
  6. 6. GharbiyaA.SyrzyckiM.2002Highly linear, tunable, pseudo differential transconductor circuit for the design of Gm-C filters,IEEE Proceeding of Canadian Conference on Electrical and Compiter Engineering,1521526,0-78037-448-7Manitoba, Canada, May 2002, Institute of Electrical and Electronics Engineers, Piscataway
  7. 7. IsmailA. M.SolimanA. M.2000Novel CMOS wide-linear-range transconductance amplifier,IEEE Transactions on Circuits and Systems,478(Aug. 2000)12481253,0098-4094
  8. 8. KimY.ParkJ.ParkM.YuH.2004A 1.8V triode-type transconductor and its application to a 10MHz 3rd-order chebyshev low pass filter,IEEE Proceedings of the IEEE 2004 Custom Integrated Circuits Conference,5356,0-78038-495-4Florida, U.S.A, Oct. 2004, Institute of Electrical and Electronics Engineers, Piscataway
  9. 9. KuoK. C.LeuciucA.2001A linear MOS transconductor using source degeneration and adaptive biasing,IEEE Transactions on Circuits and Systems,4810(Oct. 2001)937943,0098-4094
  10. 10. KrummenacherF.JoehlN.2004A 4-MHz CMOS continuous-time filter with on-chip automatic tuning,IEEE Journal of Solid-State Circuits,236(Jun 2004)750758,0018-9200
  11. 11. LagunaM.De la Cruz-BlasC.TorralbaA.R.G. Carvajal R. G.; Lopez-Martin A. & Carlosena A.2004A novel low-voltage low-power class-AB linear transconductor,IEEE Proceedings of International Sympoisum of Circuits and Systems,1725728,078038251Vancouver, British Columbia, Canada, May 2004, Institute of Electrical and Electronics Engineers, Piscataway
  12. 12. LeeS. O.ParkS. B.LeeK. R.1994New CMOS triode transconductor,Electronics Letters,3012(June 1994)946948,0013-5194
  13. 13. LeuciucA.ZhangY.2002A highly linear low-voltage MOS transconductor,IEEE Proceedings of International Sympoisum of Circuits and Systems,3735738,0-78037-448-7Scottsdale, Arizona, U.S.A, May 2002, Institute of Electrical and Electronics Engineers, Piscataway
  14. 14. LeuciucA.2003A wide linear range low-voltage transconductor,IEEEProceedings of International Sympoisum of Circuits and Systems,1161164,0-78037-761-3Thailand, May 2003, Institute of Electrical and Electronics Engineers, Piscataway
  15. 15. LikittanapongP.WorapishetA.ToumazouC.1998Tunable low-distortion BiICMOS transconductance amplifiers,Electronics Letters,3412(June 1998)12241225,0013-5194
  16. 16. MahattanakulJ.ToumazouC.1998Tunable low-distortion BiICMOS transconductance amplifiers,Electronics Letters,342(Jan. 1998)175176,0013-5194
  17. 17. NedungadiA.ViswanathanT. R.1984Design of linear CMOS transconductance elements,IEEE Transactions on Circuits and Systems,3110(Oct. 1984)891894,0098-4094
  18. 18. RazaviB.2001Design of Analog CMOS Integrated Circuits,McGraw-Hill,0-07118-839-8York
  19. 19. SeevinckE.WassenaarR. F.1987A versatile CMOS linear transconductor/Square-Law function circuit,IEEE Journal of Solid-State Circuits,226(June 1987)366377,0018-9200
  20. 20. SenguptaS.2005Adaptive biased inear transconductor,IEEE Transactions on Circuits and Systems : I Regular Papers,5211(Nov. 2005)23692375.1549-8328
  21. 21. TorralbaA.Martinez-HerediaJ. M.CarvajalR. G.Ramirez-AnguloJ.2002Low-voltage transconductor with high linearity and large bandwidth,Electronics Letters,3825(Dec. 2002)16161617,0013-5194
  22. 22. WangA.GuggenbuhlW.1990A voltage-controllable linear MOS transconductor using bias offset technique,IEEE Journal of Solid-State Circuits,252(Feb. 1990)315317,0018-9200
  23. 23. ZekiA.1999Low-voltage CMOS triode transconductor with wide-range and linear tunability,Electronics Letters,3520(Sept. 1999)16851686,0013-5194

Written By

Ko-Chi Kuo

Published: April 1st, 2010