1. Introduction
The transconductor is a versatile building block employed in many analog and mixed-signal circuit applications, such as continuous-time filters, delta-sigma modulators, variable gain-amplifier or data converter. The transconductor is to perform voltage-to-current conversion. Linearity is one of most critical requirements in designing transconductor. Especially in designing delta-sigma modulators for high resolution Analog/Digital converters, it needs high linearity transconductors to accomplish the required signal-to-(noise+distortions) ratio. The tuning ability of transconductor is also mandated to adjust center frequency and quality factor in filter applications.
The portable electronic equipments are the trend in comsumer markets. Therefore, the low power consumption and low supply voltage becomes the major challenge in designing CMOS VLSI circuitry. However, designing for low-voltage and highly linear transconductor, it requires to consider many factors. The first factor is the linear input range. The range of linear input is justified by the constant transconductance,
In general, the design of differential transconductor can be classified into triode-mode and saturation-mode methods depending on operation regions of input transistors. Triode-mode transconductor has a better linearity as well as single-ended performance. On the other hand, saturation-mode transconductor has better speed performance. However, it only exhibits moderate linearity performance. Furthermore, the single-ended transconductor of saturation-mode suffers from significant degradation of linearity. Several circuit design techniques for improving the linearity of transconductors have been reported in literatures. The linearization methods include: source degeneration using resistors or MOS transistors [Krummenacher & Joeh, 1988; Leuciuc & Zhang, 2002; Leuciuc, 2003; Furth & Andreou, 1995], crossing-coupling of multiple differential pairs [Nedungadi & Viswanathan, 1984; Seevinck & Wassenaar, 1987] class-AB configuration [Laguna et al., 2004; Elwan et al., 2000; Galan et al., 2002], adaptive biasing [Degrauwe et al., 1982; Ismail & Soliman, 2000; Sengupta, 2005], constant drain-source voltages [Kim et al., 2004; Fayed & Ismail, 2005; Mahattanakul & Toumazou, 1998; Zeki, 1999; Torralba et al., 2002; Lee et al., 1994; Likittanapong et al., 1998], pseudo differential stages [Gharbiya & Syrzycki, 2002], and shift level biasing [Wang & Guggenbuhl, 1990].
Source degeneration using resistors or MOS transistors is the simplest method to linearize transconductor. However, it requires a large resistor to achieve a wide linear input range. In addition, MOS used as resistor exhibits considerable varitions affected by process and temperture and results in the linearity degradation. Crossing-coupling with multiple differential pairs is designed only for the balanced input signals. The Class-AB configuration can achieve low power consumption. On the other hand, the linearity is the worst due to the inherited Class-AB structure. The adaptive biasing method generates a tail current which is proportional to the square of input differential voltage to compensate the distortion caused by input devices. However, the complication of square circuitry makes this technique hard to implement. The constant drain-source voltage of input devices is a simple structure. It can achieve a better linearity with tuning ability. However, it needs to maintain
In section 2, basic operatrion and disadvantage of the linerization techniques are described. The proposed new transconductor is presented in section 3. The simulation results and conclusion are given in section 4 and 5.
2. Linearization techniques
In this section, reviews of common linearization techniques reported in literatures are presented. The first one is the transconductor using constant drain-source voltage. The second one is using regulated cascode to replace the auxiliary amplifier. The third one is transconductor with source degeneration by using resistors and MOS transistors. The last one is the linear MOS transconductor with a adaptive biasing scheme. Besides introducing their theories and analyses, the advantages and disadvantages of these linearization techniques are also discussed.
2.1. Transconductor using constant drain-source voltage
The idea of transconductors using constant drain-source voltages is to keep the input devices in triode region such that the output current is linearized. The schematic of this method is shown in Figure 1. Considering that transistors M_{1}, M_{2} operate at triode region, M_{3}, M_{4} are biased at saturation region, channel length modulation, body effect, and other second-order effects are ignored, the drain current of M_{1} and M_{2} is given by
where
The transfer characteristic of this transconductor is given by
The transconductance value is
In fact, it is difficult to design an ideal amplifier implemented in this circuits. However, it can force
where V_{GS1}= V_{in1} and V_{GS2}= V_{in2}.
Therefore, the new transconductance value is
The linearity of this transconductor is moderated. It is also easy to implement in circuit. However,
On the other hand, the auxiliary amplifiers need to design carefully to reduce the overhead of extra area and power.
2.2. Transconductor using regulated cascode to replace auxiliary amplifier
In Figure 2(a) regulating amplifier keeps
It is one of solutions using regulated cascode to replace the auxiliary amplifier in order to overcome restrictions on Figure 1. The circuit in Figure 2(b) proposed in [Mahattanakul & Toumazou, 1998] uses a single transistor, M_{5}, to replace the amplifier in Figure 2(a). This circuit called regulated cascode which is abbreviated to RGC. The RGC uses M_{5} to achieve the gain boosting by increasing the output impedance without adding more cascode devices.
From (6)
Simple RGC transconductor using a single transistor to achieve gain boosting can reduce area and power wasted by the auxiliary
In Figure 3, another RGC transconductor that can apply to the low-voltages applications is proposed in [Likittanapong et al., 1998]. The circuit overcomes the disadvantages mentioned above is to utilize PMOS transistor that can operate in saturation region as gain boosting. The use of this PMOS gain boosting in the feedback path can result in a circuit with a wide transconductance tuning range even at the low supply voltage. In [Likittanapong et al., 1998], it mentions that at the maximum input voltage, M_{3} may be forced to enter triode region, especially if the dimension of M_{2} is not properly selected, resulting in a lower dynamic range. Besides,
From (6)
2.3. Transconductor using source degeneration
A simple differential transconductor is shown in Figure 4(a). Assuming that M_{1} and M_{2} are in saturation and perfectly matched, the drain current is given by
The transfer characteristic using (5) is given by
where V
If
A transfer characteristic derived from (13) is given by
The transconductance
where
We should notice that in (14), the nonlinear term depends on
Another method to linearize the transfer characteristic of MOS transconductor is using source degeneration to replace the degeneration resistor with two MOS transistors operating in triode region. The circuit is shown in Figure 5. Notice that the gates of transistor M_{3} and M_{4} connect to the differential input voltage rather than to a bias voltage. To see that M_{3} and M_{4} are generally in triode region, we look at the case of the equal input signals (
Therefore, the drain-source voltages of M_{3} and M_{4} are zero. However,
It must be noted that in this circuit the effect of varying
Using small-signal T model, the small-signal output current,
Assuming M_{1} is in saturation region, the drain current of M_{1} is given by
Using (20) substitutes for (19), that leads to
The transconductance
Linearity can be enhanced (assuming
According to (22), the transconductance can be tuned by changing
2.4. Transconductor using adaptive biasing
The transconductor using adaptive biasing is shown in Figure 6. All transistors are assumed to be operated in saturation region, neglecting channel lengh modulation effect. First, transistor M_{3} is absent, and output current as a function of two input voltages
where
An adaptive biasing technique is using a tail current containing an input dependent quadratic component to cancel the nonlinear term in (23). Consequently, the circuit in Figure 6 changes the tail current by adding transistor M_{3}. The tail current will be changed by
where
Therefore, the transfer characteristic is changed by
3. New transconductor
The conventional structure which uses the constant drain source-voltage such as RGC with NMOS or PMOS can not operate at 1.8V or below. The main reason is that auxiliary amplifier under the low supply voltage can’t provide enough gain to keep the constant drain-source voltage. Therefore, we propose a triode transconductor which uses new structure to replace the auxiliary amplifier. Figure 7 shows the proposed triode transconductor structure.
MOS M_{5}, M_{7}, M_{9} and M_{11} are made up a two-stage amplifier to replace the auxiliary amplifier. The two-stage amplifier is implemented using M_{9} with the active loads M_{11} formed the first stage and M_{5} with the active load M_{7} formed the second stage. The first and second stages exhibit gains equal to
Therefore, the overall gain is
The proposed transconductor is shown in Figure 8.
Considering that the large gain is achieved and is able to keep transistors M_{1} and M_{2} in triode region, the drain current of M_{1} and M_{2} is given by
The transfer characteristic is given by
where
According to (32)
The transconductance G_{m} is
From (35), the transconductance can be tuned by control voltage
Using (33) to substitute (36)
The proposed transconductor is suitable for low supply voltage and we choose 1.8V to achieve a wide linear range. Moreover, M_{9} is needed to obtain a negative feedback to keep the drain-source voltage of M_{1}, V_{DS1}, constant. This new structure can provide enough gain to keep V_{DS1} constant at 1.8V supply voltage. It has a low control voltage V_{C} between 0.69V~0.72V and the large transconductance tuning range depending on applications. Besides, it has a simple structure so as to save area.
4. Simulation results
The circuits in Figure 8 have been designed by using TSMC CMOS 0.18μm process with a single 1.8V supply voltage and simulated by Hspice. Figure 9. shows the curve of input voltage transferring to the output current at
In Figure 11. it shows the drain-source voltage of the input transistors M_{1} and M_{2}, V_{DS1} and V_{DS2}, changes with the input voltage. Within ±1V input voltage, V_{DS1} and V_{DS2} are very small. According to equation (40), V_{DS1} and V_{DS2} are too small such that transistors M_{1} and M_{2} can be set in triode region. Once the input voltage exceeds ±1V, V_{DS1} and V_{DS2} will increase rapidly. It results in that transistors M_{1} and M_{2} enter in saturation region. In other words, when M_{1} and M_{2} entering saturation region the proposed transconductor can not maintain the high linearity.
When V_{C} is set between 0.69V and 0.72V, the linear input range is up to 2.6V and the transconductance error is less than 1%. The smallest transconductance is 3.4μs and linear input range is 1.2V when
V _{C } (V) | Linear input range (V) | Transconductance (µS) |
0.690 | 1. 4 | 542 |
0.695 | 1.8 | 434 |
0.700 | 1.8 | 326 |
0.705 | 2.2 | 219 |
0.710 | 2.4 | 122 |
0.715 | 2.6 | 42 |
0.720 | 1.2 | 3.4 |
In Figure 12., the simulated THD as a function of the input frequency and input signal amplitude is plotted. The best THD is achieved at the low input voltage and the low frequency. When
Figure 13. shows the linearity of transconductor in three linearization techniques. The transconductor using source degeneration with resistor is shown in Figure 4(b), and the transconductance in Figure 13(a) is tuned by different resistors. The transconductor using source degeneration with MOS transistors is shown in Figure 5, and the transconductance in Figure 13(b) is tuned by the different size ratio of
The simulated THD of the output differential current versus the input signal amplitude for the four linearized transconductors is plotted in Figure 15. The proposed transconductor achieves THD less than −61dB for the 0.7Vpp input voltage, 11dB better than the one using source degeneration using resistor, 24dB better than the one using source degeneration using MOS, and 31dB better than the one using adaptive biasing, at the same input range.
Table 2. shows the power consumption of the four linearized transconductors at the same transconductance. Power consumption changes with the different transconductances. Therefore, the same transconductance is chosen to be compared in each configuration. Table 3. shows different power consumption at the different transconductance of the proposed transconductor.
Source degeneration using MOS | Source degeneration using resistor | Adaptive biasing | Proposed | |
Power (mW) | 1.3 1 | 1.19 | 1.38 | 1. 58 |
V C (V) | Power (mW) | G m (µA/V) |
0.690 | 1.759 | 542 |
0.695 | 1.7 14 | 434 |
0.700 | 1.5 86 | 326 |
0.705 | 1.4 42 | 219 |
0.710 | 1.2 63 | 122 |
0.715 | 0. 9 54 | 42 |
0.720 | 0.733 | 3.4 |
Table 4. shows the comparison of performance with other transconductors at the low supply voltage (under 2V). The transconductor in [Fayed & Ismail 2005] also uses constant drain-source voltage. It modifies the basic structure of constant drain source voltage and uses the moderate amplifier. The proposed transconductor modifies the auxiliary amplifiers to obtain high gain under low supply voltage.
The layout including proposed transconductor, Common Mode Feedback, and bandgap is shown in Figure 16. The proposed transconductor uses STC pure 1.8V linear I/O library in 0.18μm CMOS process. The chip area is 0.516mm^{2}.
[Galan et. al 2002] | [Leuciuc & Chang 2002] | [Laguna et. al 2004] | [Sengupta 2005] | [Fayed & Ismail 2005] | Proposed | |
Process | 0.8µm | 0.25µm | 0.8µm | 0.18µm | 0.18µm | 0.18µm |
Power supply | 2V | 1.8V | 1.5V | 1.8V | 1.8V±10% | 1.8V |
THD | -40dB @10MHz | -80dB, 0.8Vpp, @2.5MHz | -33dB, 0.2Vpp, @5MHz | -65dB, 1Vpp, @1MHz | -50dB, 0.9Vpp, @50KHz | - 60 dB, 0.7Vpp, @1 00KH z |
G m (µA/V) | 0.6~207 | 200~600 | 67~155 | 770 | 5~110 | 3.4 ~ 542 |
Linear input range | 0.6Vpp | 1.4Vpp | 0.6Vpp | 1Vpp | 1.8Vpp | 2.4 Vpp |
Year | 2002 | 2002 | 2004 | 2005 | 2005 | 200 9 |
5. Conclusion
The proposed low-voltage, highly linear, and tunable triode transconductor achieves the wide linear input range up to 2.4V. The total harmonic distortion is −60dB with a 0.7V_{pp} input voltage. The design uses TSMC 0.18μm CMOS technology and supply voltage is 1.8V. Moreover, it exhibits a large G_{m} tuning range from 3.4μS to 542μS and also keeps a wide linear input range. Finally, the performance comparison with other linear techniques shows that the proposed technique achieves better linearity, wider tuning range, and wider linear input range.
Acknowledgments
This work was supported in part by the National Science Council, Taiwan, ROC, under the grants: NSC 97-2221-E-110-078.
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