Comparison of the parameters of the TFTs.
The metal-semiconductor interface in thin-film transistors (TFTs) is one of the bottlenecks on the development of these devices. Although this interface does not play an active role in the transistor operation, a low-quality interface can be responsible for a low performance operation. In a-Si TFTs, a doped film can be used to improve this interface, however, in other TFT technologies, there is no doped film to be used. In this chapter, some alternatives to improve this interface are analysed. Also, the influence of this interface on the electrical stability of these devices is presented.
- thin-film transistors
- contact resistance
- short channel effects
In all electronic devices, an electrical connection to the real world is necessary. In the case of thin-film transistors (TFTs), the quality of this electrical connection may be the difference in having high or low performance devices. The connection is made by source/drain electrodes in contact with the active layer. These metal-semiconductor interfaces have not played an active role in the transistor operation. However, a low-quality interface can be responsible for a low performance operation. Indeed, this research topic is one of the bottlenecks on the development of thin-film transistor technologies.
It is desirable to have the closest to an ideal metal-semiconductor interface or an ohmic contact with very low contact resistance; in other words, source/drain contacts with no barriers for the carrier flow in either positive or negative voltage polarization. Ideally, this occurs when metal and semiconductor work functions are of similar value and there are no interface states. However, having metal-semiconductor contacts without interface states is difficult and matching the semiconductor and metal work functions is nearly impossible. For these reasons, it is important to find alternatives to improve the metal-semiconductor interface in TFTs.
In metal-semiconductor interfaces, one may have several cases: ohmic contacts with low or high contact resistance and non-ohmic contacts with low or high contact resistance. Being this last, the most commonly obtained. The contact resistance can be extracted experimentally by the extrapolation of the width-normalized resistance (RW), obtained from the linear regime of the output characteristics
The problem associated with a high contact resistance is that it induces a potential drop at the drain/source contacts, affecting the electrical performance of the device [1–4]. On short channel TFTs, as the channel length is reduced, the source/drain contact resistance may be higher than the channel resistance, as result the electrical behaviour may be governed by the contact resistance. This may induce several mechanisms: some of them reported the degradation of the transconductance, drop of carrier mobility, impact ionization, among others. Indeed, there is not a value of channel length to determine if short channel effects will be exhibited on the electrical characteristics of the TFT. Reported TFTs exhibited short channel effects at channel lengths
2. Experimental section
The high quality SiO2 film was obtained by spin-coating of SOG (SOG700B Filmtronics) diluted with deionized water and cured at 200°C. The a-SiGe:H active layer was deposited using low frequency (110 kHz) plasma-enhanced chemical vapor deposition (PECVD) at 200°C, pressure of 0.6 Torr and an RF power of 300 W. The a-SiGe:H films were deposited from SiH4 and GeH4 feed gases with H2 dilution. The flow rate of SiH4 (10% H2) and H2 was 45 sccm and 1000 sccm, respectively, and the GeH4 (90% H2) flow rate was 105 sccm. The n+ a-Ge:H film was deposited using low frequency PECVD at 200°C with a pressure of 0.6 Torr and RF power of 300 W, with a GeH4 (90% H2) flow of 250 sccm, H2 flow of 3500 sccm and PH3 (99% H2) flow of 20 sccm. The aluminium was e-gun evaporated.
3. Alternatives for metal-semiconductor interface improvement
The requirements for getting a high-quality metal-semiconductor interface are complex. Typically, in field-effect transistors, a heavily doped interlayer or contact region film is used between the semiconductor and source/drain electrodes in order to improve the metal-semiconductor interface. However, in amorphous semiconductors, the doping efficiency drops at high doping levels. Moreover, in some TFT technologies, there are no doped interlayer films to improve the metal-semiconductor interface. These make even more complex to obtain a high-quality interface.
3.1. Doped regions for source/drain contacts
In the case of hydrogenated amorphous silicon (a-Si:H), Le Comber and Spear  reported that amorphous silicon prepared by plasma-enhanced chemical vapor deposition (PECVD) can effectively be doped by adding small amounts of phosphine (PH3) or diborane (B2H6) to the silane (SiH4) in the discharge gas. As expected, the conductivity increases at low doping levels. However, at higher doping levels, the conductivity decreases presumably due to the generation of defect states.
Figure 2 shows the contact resistance of a-Ge:H films at 200°C as function of the PH3 flow. At low flow of PH3 the contact resistance decreases, but at higher flow it increases. This behaviour agrees with the reported by Le Comber and Spear. Similarly, Figure 3 shows the contact resistance of the p-type a-Ge:H film as a function of the B2H6 flow. At low flow of B2H6, the contact resistance increases but at higher flow it decreases and finally increases again. This behaviour also agrees with the reported by Le Comber and Spear. These interlayer films enhance the tunnelling of carriers through the metal-semiconductor interface, reducing the contact resistance and improving the interface. The n-type a-Ge:H film was successfully used as a contact region film in ambipolar a-SiGe:H TFTs .
3.2. Plasma processes to improve the contact resistance
In this section, the improvement of carrier mobility, on/off-current ratio and threshold voltage using hydrogen plasma at the active layer prior to define the source/drain contacts is presented. Firstly, an over-etching in the active layer before forming the source/drain contacts is performed. This over-etching closes the source/drain contacts to the induced channel layer, as indicate in Figure 4 .
Figure 4a shows the structure of the TFT after the deposition of the gate electrode, gate insulator, active layer and passivation layer. Typically, after this step, the passivation layer is etched to form the source/drain contacts (Figure 4b ). In this case, added to the etching of the passivation layer, an over-etching in the active layer is performed, as indicate in Figure 4c . Moreover, a hydrogen plasma is applied . For comparison, a set of devices without hydrogen plasma was fabricated. Finally, the source/drain contacts are formed (Figure 4d ).
shows the transfer characteristics of the TFTs with and without hydrogen plasma. The TFTs with applied hydrogen plasma exhibit an on/off-current ratio approximately of 106 and an off-current approximately of 300 fA at 0
On the other hand, Figure 6
shows the square root of
It is well known that hydrogen saturates dangling bonds in amorphous films . Thus, the hydrogen plasma reduces the plasma-induced damage in the source/drain regions of the active layer, and as result the contact resistance of the TFT is improved. This can be corroborated with the higher values of carrier mobility and on-current.
show the output characteristics of the TFTs with and without hydrogen plasma. The output characteristics of TFTs without hydrogen plasma exhibit a high contact resistance that appears in the form of current crowding, in the bias range of 0–1V of
3.3. Planarization of the gate electrode in bottom-gate TFTs
Thin-film transistors are successfully employed in active-matrix displays . In this application, the inverted staggered structure is the most used . In an inverted structure, the gate electrode is placed at the bottom of the structure (bottom-gate structure). The advantage of using this inverted structure is that the gate electrode protects the active layer from backplane light. The problem is when the active-matrix displays become larger, the number of address lines must increase and the gate lines must be narrower and longer. To avoid an increase in the resistance of the gate line, which results in delay on the display performance, the gate line must be thicker. Then, the problem with this thicker gate is that the gate insulator tends to be thinner around the corners of the gate, increasing the leakage current and electric stress due to the high electric field at the corner . In order to reduce these effects, the planarization of the gate electrode was proposed by other groups [19, 20].
As far as we know, the only work related to the study of the planarization of the gate electrode is conducted by Chen et al. . They reported a reduction in the contact resistance attributed to the planarization process. However, this improvement in the contact resistance is difficult to understand, since the planarization of the gate electrode improves the insulator-semiconductor interface but not the metal-semiconductor interface. Firstly, the experimental characteristics of planarized and unplanarized TFTs are presented. After that using a physically based simulator (SILVACO), the main interfaces are analysed to understand the origin of this improvement.
The experimental transfer characteristics of unplanarized and planarized TFTs are shown in Figure 9 . The planarized TFT shows a subthreshold slope ~0.45 V/DEC and ~0.49 V/DEC, for n-type and p-type regions, respectively, while on/off-current ratios around 105 were obtained for n-type and p-type regions. On the other hand, the unplanarized TFT shows a subthreshold slope ~1 V/DEC for an n-type region and 1.3 V/DEC for a p-type region, on/off-current ratios ~104 and 103 for n-type and p-type regions, respectively.
The threshold voltage and field-effect mobility were extracted from the transfer characteristics operating in the saturation regime (
shows the output characteristics for planarized and unplanarized TFTs. It is important to mention that the output characteristics show an ambipolar behaviour. A detailed discussion and modelling can be found in Ref. . In the output characteristics of unplanarized TFTs, current crowding appears in the bias range from 0 to 1 V of
The experimental results agree with the reported previously by Chen et al. However, the improvement in contact resistance by the planarization process is unexplained. Using ATHENA, both planarized and unplanarized structures were simulated. Then, using ATLAS, electrical measurements were simulated. The cutline tool within the ATLAS simulator generates one-dimensional profiles from the insulator-semiconductor and metal-semiconductor interfaces. Ideal contacts were considered for source/drain contacts in both unplanarized and planarized simulated TFTs (ohmic contacts without contact resistance).
Figure 11 shows a comparison of the cross-section of planarized and unplanarized TFTs simulated by ATHENA. Applying a positive gate bias of 5 V, the electric field of the planarized and unplanarized gate electrodes was extracted by ATLAS (Figure 12 ). As expected, for the planarized TFT, the electric field is uniform through the insulator-semiconductor interface. However, for the unplanarized TFT, the electric field is not uniform through the insulator-semiconductor interface. There is an increase of the electric field due to the thinner gate insulator. This increase in the electric field causes an accumulation of electrons in the channel close to the corners of the gate, as shows Figure 13 .
The difference of the electron concentration in the channel works as a scattering mechanism, limiting the mobility of the carriers. This can explain the lower extracted field-effect mobility in the unplanarized TFTs. Also, the variations of the electron concentration reflect an increase in the conduction band energy of the active layer close to the source/drain contacts, as show in Figure 14 . This increase in energy acts as a barrier for the electrons, where only electrons with higher energy can pass the barrier. As result, the device contact resistance apparently increases. To corroborate these assumptions, Figure 15 shows the simulated output characteristics of both planarized and unplanarized TFTs. The simulation agrees with the behaviour exhibited in the experimental and simulated results.
4. Influence of metal-semiconductor interface on electrical stability of TFTs
Despite the high potential of TFTs to enable low-cost electronics, these devices have the disadvantage of threshold voltage shift after a prolonged application of gate bias stress. In a-Si TFTs, the threshold voltage shift mechanisms have been studied to estimate the long-term behaviour of TFT circuits. Because of the continuous growing application of novel material-based TFTs in electronics, an updated research for threshold voltage shift mechanisms is needed. The defect state creation in active layer and charge trapping in the gate dielectric is presumably the mechanisms responsible for the threshold voltage shift in TFTs. During the application of gate bias stress (or during normal operation), the charge trapping and defect state creation mechanisms occur simultaneously; therefore, the experimental results of threshold voltage shift do not provide any information about the quantitative effect of each of these mechanisms on the threshold voltage shift of the TFT. In addition, it has been proposed the relaxation of the threshold voltage after the annealing of the defect states in the active layer and the charge back tunnelling of trapped electrons inside the gate insulator [24–26]. However, the experimental published results for the relaxation of threshold voltage do not support the defect state annealing mechanism. While the estimations of charge trapping and de-trapping from gate insulator traps show a good agreement with the experimental threshold voltage relaxation. Therefore, from the threshold voltage shift mechanisms, charge trapping in the gate insulator is reversible [26–30].
On the other hand, the proposed mechanisms responsible for threshold voltage shift are directly related to the insulator-semiconductor interface. However, it has been also reported that quality of the metal-semiconductor interface strongly influences the kinetics of threshold voltage shift and relaxation of TFTs . Based on the results reported for the charge trapping and defect state creation mechanisms of threshold voltage shift, a general conclusion cannot be drawn. The kinetics of the mechanisms strongly depends on the fabrication process of the TFTs. It is important to consider that deposition conditions of the active layer also affect the rate of the creation of the extra defect states in the active layer.
In this section, a comparison of the threshold voltage shift in TFTs with the same insulator-semiconductor interface but different metal-semiconductor interface is presented. The threshold voltage shift is calculated as a function of the stress time at gate bias stress of 20 V and
Table 1 summarises the parameters extracted in both TFTs. Since both TFTs have identical insulator-semiconductor interface, the slight difference in values of subthreshold slope is considered just statistical fluctuation. The values of off-current are of the same order of magnitude. The on/off-current ratio is very similar for both TFTs. However, an important difference in field-effect mobility is found. The mobility for TFTs using SiNx as a passivation layer (hydrogen plasma) was 0.85 cm2/Vs, higher than the 0.68 cm2/Vs for TFTs using SiO2 passivation. This result is related to the metal-semiconductor interface, the higher value of mobility may indicate a lower contact resistance.
|Parameter||TFT SiNx passivation (hydrogen plasma)||TFT SiO2 passivation|
|SS||0.56 V/DEC||0.45 V/DEC|
||2.25 V||1.14 V|
|Field-effect mobility||0.85 cm2/Vs||0.68 cm2/Vs|
|Off-current||~0.3 pA||~0.95 pA|
shows the threshold voltage shift ∆
The higher value of mobility results of a lower contact resistance, however, the higher instability of this TFT related to defect state creation suggests a dependency with the fabrication of the metal-semiconductor interface. Probably due to defects induced by the over-etching process. Also, the SiN
In summary, some alternatives to improve the metal-semiconductor interface are analysed. An over-etching at the source/drain regions of the active layer can improve the TFT electrical performance, since this process gets close the n+ contact layer and the electron induced-channel. Moreover, the plasma-induced damage by the over-etching process is reduced after the application of a hydrogen plasma. On the other hand, the planarized TFTs exhibit better performance due mainly to the improved contact resistance. The simulations show an increase in the conduction band energy in the a-SiGe:H film at the metal-semiconductor interface. This increase acts as a barrier for the electrons, which results in an apparent increase of contact resistance. Finally, the influence of the metal-semiconductor interface in the electrical stability of TFTs is presented. Although the compared TFTs present the same insulator-semiconductor interface, the fabrication of the metal-semiconductor interface plays an important role in the electrical stability of these devices.
This work is partially supported by PRODEP-SEP, CONACyT-255062 and VIEP-BUAP-LULJ-EXC-2017.
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