Open access peer-reviewed chapter

Pulse Density Modulation Applied to Series Resonant Inverter and Ac‐Ac Conversion

Written By

Abdelhalim Sandali and Ahmed Chériti

Submitted: 22 September 2016 Reviewed: 06 March 2017 Published: 21 June 2017

DOI: 10.5772/intechopen.68324

From the Edited Volume

Recent Developments on Power Inverters

Edited by Ali Saghafinia

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The PDM control joins together between the concepts of soft switching and hard switching. Its application to the series resonant inverter cancels the switching losses and uses dc bus without storage capacity. Objectively, the PDM controls led to ac‐ac converters with high efficiency (zero switching loss), small size (no storage capacity) and with the possibility of a self power factor correction. However, the operating analysis of these converters is very complex because the operation is done on two time scales and leaves questions unanswered. The average modeling facilitates the analysis of the operation and leads to establish: (i) an analytical expression of the power factor, (ii) the linearity conditions of the power characteristic, and (iii) a model of ac‐ac series resonant multi‐converter which is independent of the carriers. In the case of ac‐ac series resonant multi‐converter, the coordination of carriers allows to shape the power characteristic. Among the three types of coordination presented, there is an original coordinate that linearizes the power characteristic. The results are validated by simulations carried out in Matlab SimPower systems.


  • pulse density modulation
  • series resonant inverter
  • multi-inverter ac-ac converter
  • power factor correction
  • average modeling

1. Introduction

The soft‐switching, appeared in the early eighties of last century, is a major event in the development of power electronics [1, 2]. Numerous research and conference sessions devoted to it reflect this importance. The soft switching is a conceptual breakthrough that led to technological advances. Indeed, to reduce the size of the reactive components, something that has a positive effect on the weight and size of converters, it is necessary to seek to increase the switching frequency. However, to increase the switching frequency of power semiconductor switches, it is imperative to create the conditions for reducing switching losses. Within the framework of soft switching concept, one considers that the most effective way to achieve this goal is to leave full‐controlled power semiconductor devices to switch depending on their changing voltages and/or currents [35]. The power part of the converter plays an active role in determining the switching instants.

In resonant converters, implementing this concept, there is a shared determination of switching instants between the control part and power part of the converter: if a commutation is caused by the control, complementary commutation is caused by the voltage or current of the switch (ZVS or ZCS). The transmitted power control is done by the frequency modulation.

Pulse density modulation (PDM) control, appeared in the mid‐1990s [6, 7], joins together the concept of soft switching and the traditional concept of hard switching by separating the roles of the control part and power part. The power part is responsible for determining the switching instants. The control part decides the nature of switching cycles (active or inactive). Its application to series resonance inverters has the major advantage to cancel the switching losses and to produce an output power factor near to unity [611]. The integration of these inverters in the ac‐ac conversion makes it possible to save the smoothing filter and to have a sine‐wave absorption at full power [6, 7]. Several recent researches are devoted to the development of PDM control and to the valorization of its applications [811]. The operating analysis presented in these papers focus on the output current. The input current (current drawn from the ac‐supply) analysis is forsaken. This aspect constitutes the poor relation in the scientific literature dedicated to the PDM technique.

Fill this blank, clarify it why, and show how to exploit the benefits and manage the challenges are the objectives of this work. More than a synthesis of previous work, this chapter provides for the first time an average modeling of PDM inverters, an accurate determination of the linear operating conditions and an original linearization technique.

This chapter is organized as follows: in Section 3, we present the principle of PDM control and its integration in ac‐ac converter. Section 4 is devoted to the description of a pulse density modulator. The conventional analysis is the subject of Section 5. The determinations of the input current of the ac‐ac converter and its power factor in the case of single and multi‐inverter configurations are presented. Section 6 is devoted to the average modeling of ac‐ac series resonant converter in single‐ and multi‐inverter configurations. Several cases of coordination of the carriers are discussed in Section 7. Simulation results are given in Section 8, and conclusion is presented in Section 9.


2. Principle

Pulse density modulation (PDM) is a type of control applied to the series resonance inverters. Turn‐on and turn‐off occur at zero crossings of the load current, because the switching frequency is taken equal to resonance frequency of the load. All commutations are lossless and without current gradient, and the input current of inverter is unidirectional. The inverter operation has the following improvements: (i) the switches are completely released from switching stress; (ii) dc bus has no storage capacity; and (iii) reduction of electromagnetic noise. But, as the switching frequency is now fixed, it is impossible to use it to control the power.

To avoid this disadvantage, the control part generates a PDM pattern that determines whether a switching cycle is active or inactive. An active cycle is a normal operating cycle of the single‐phase inverters. An inactive cycle is defined by the simultaneous state‐on of same side switches (e.g., high side) and the simultaneous state‐off of the other side switches (e.g., low side). It puts the output inverter in freewheel and, consequently, interrupts the flow of energy between input and output of the converter. The power control is now done by the PDM pattern duty cycle defined by:


with k is the number of total cycles per PDM pattern period (called PDM pattern length) and n=1, 2, …. or k.

The power control is thus done in a discrete manner with a resolution which depends on the length of the pattern.

Figure 1 shows the considered inverters and the transcription logic circuit of the PDM pattern in the gate control signals of the switches. We propose in Figure 2 an operating model that clearly shows the coexistence of the two concepts (hard and soft switching). The PDM inverter is divided into soft inverter and hard buck. The transmitted power is controlled by the PDM pattern.

Figure 1.

PDM inverter: topology, control and definition.

Figure 2.

Decomposition of the PDM inverter in hard buck and soft inverter.

When the inverter is supplied by a single‐phase diode bridge, the unit forms an ac‐ac converter (LF to HF) (Figure 3). Since the input current of PDM inverter is unidirectional, it is possible to eliminate the smoothing filter (low frequency 2 × 50 or 2 × 60) and keep only a high frequency decoupling capacitor CHF. The latter absorbs the high frequency ripple of the current in the rectifier. The result is a small‐sized ac‐ac converter because it is relieved of the smoothing filter). The current drawn by the ac‐ac converter is a sinusoidal form, but is intersected by zero current phases when inactive cycles occur. In the following, we focus on the control, the transmitted power and the quality of current drawn by this ac‐ac converter that will be called ac‐ac PDM converter and noted PDMC.

Figure 3.

Ac‐ac PDM converter (without smoothing filter).


3. PDM pattern generation

The PDM pattern generation is subject to two particular restrictions.

The first restriction concerns the adaptation of the PDM pattern frequency to the load resonance frequency. So that the switching cycles are not truncated, the PDM pattern period must be a multiple of the resonance period:

First restriction TPDM=kTr with k is an integer E2

To satisfy this restriction, several options are possible. We present below a PWM type technique but adapted to PDM control. It is based on a synchronous comparison of a control signal (ec) and a triangular carrier (Car) [12]. The synchronous comparison is carried out by a conventional comparator followed by a D flip‐flop (Figure 4).

Figure 4.

Adaptation of PDM frequency to resonance frequency by synchronous comparison.

When the PDM inverter is integrated into an ac‐ac series resonant converter, it is necessary that the PDM pattern satisfies a second restriction: its period (frequency) must be a sub‐multiple (multiple) of the period (frequency) of the dc link voltage:

Second restriction Tdc=qTPDM with q is an integer E3

If this restriction is not satisfied, a continuous component can appear in the current drawn from the electrical network. The substitution of Eq. (2) into Eq. (3) leads to restriction:

Tdc=NTres with N=q*k is an integer E4

To check this restriction, a calibration of the dc‐voltage period seen by the inverter is performed by the definition of the ZCD signal (Zero Crossing Detector) [12]. This signal is determined by the synchronous comparison of the ac‐supply voltage with positive and negative thresholds. The synchronous comparison is carried out here by the set two comparators—and logical gate—D flip‐flop. ZCD is at the zero level during a time which is a multiple of the period of resonance and which can be very close to the period of the rectified voltage if the thresholds are close to zero. ZCD, when it’s high, is used to reset the PDM pattern and the carrier’s generator. Henceforth, the useful (or usable) period of the rectified voltage is automatically adjusted with a multiple of the resonance period, and the triangular carrier is synchronized to the latter. Figure 5 shows the pattern generation circuit for an ac‐ac PDM converter. The PDM pattern duty cycle is identified with the control signal because the carrier is triangular, whereas the carrier frequency represents the PDM pattern length. As a result, the control signal controls the power while the carrier frequency controls the power variation resolution. In the following section, we establish the relation between the control signal and the transmitted power and the impact of the carrier frequency on the quality of the current drawn from the ac‐supply.

Figure 5.

PDM pattern generator performing synchronous comparison and calibration.


4. Conventional analysis

4.1. Input current of ac‐ac PDM converter

The drawn current from ac network and transmitted power by ac‐ac series resonant converter are determined under the following assumptions: (i) the load has a low damping coefficient; (ii) CHF capacitor absorbs HF component (twice the resonant frequency) of the inverter input current; (iii) the dc link voltage is assumed constant during a switching cycle; and (iv) no restriction is imposed on the PDM pattern except the restrictions of definition.

One determines successively the load current, the currents after and before the HF decoupling capacitor and the current drawn from the ac‐supply. Then, one calculates the Fourier series of the latter current. In Ref. [12], it is shown that if the PDM pattern is generated according to the solution of Section 3, the following results are obtained:

  1. the transmitted power in pu varies linearly with the control signal:


  2. the spectrum of the drawn current consists of harmonic pairs spaced from 2qFac

  3. and the power factor, calculated from the harmonic summation, is as follows:


It is independent of the PDM pattern frequency. The power factor decreases continuously when the transmitted power in pu varies from 1 to 0.

Failing to improve the power‐factor directly, an increase in the pattern frequency brings a better conditioning of the harmonic distortion (increase spacing and thus reject harmonics in high frequencies). But, it is observed that the more the frequency increases, the more one loses the linearity between power and control signal. We propose later in this chapter, a theoretical determination of the maximum frequency which preserves this linearity.

4.2. Input current of ac‐ac multi‐PDM converter and power factor correction

Correction by mutual compensation requires the use more than one inverter and an adapted control. The inverters are managed in such a way that the distortion produced by an inverter (zero current phase) is completely or partially masked by the other inverters. The inverters do not operate in inactive cycles simultaneously but successively. This management is based on the use of a set of interlaced carriers. This idea was developed for a system with several inverters and separate loads (each inverter feeds one load). Then, the idea was extended to the more realistic case of a single load [13]. The considered converter and its carriers are shown in Figure 6. It is called ac‐ac multi‐PDM converter and noted M‐PDMCG. If this converter consists of G inverters (Invg with g = 1, 2, …, G), the carrier associated with an Invg is as follows:

Figure 6.

Ac‐ac multi‐PDM converter (MPDMCG): topology and carriers in case G = 3.


and all inverters have the same control signal:


This converter behavior is modeled by a bi‐converter system with separate loads (ConvA and ConvB) and variable parameters. The control signals, carriers and transformer ratios of ConvA and ConvB vary according to the control signal. Figure 7 shows the topology of the bi‐converter system and the control parameters. The results, detailed in Ref. [13], are as follows:

Figure 7.

Bi‐converter equivalent system when (g1)/Gecg/G.

  1. Power versus control signal is piecewise linear:


    Where g1=floor( (integer portion of

  2. the spectrum of the drawn current consists of harmonic pairs spaced from 2GqFac

  3. the power factor, calculated from the harmonic summation, is:


    The power factor is equal to 1 in G points when the transmitted power is equal to (j/G)2 100% of its maximum value with j=1, 2, G, and

  4. the maximum power is G2 times greater than in the case of the PDMC.

This modeling is empirical because it is based solely on the observation of the converter behavior. However, since the behavior of a converter is defined by its topology and its control, the bi‐converter model is only valid for the control law considered during the observation phase.


5. Analysis by average modeling

The average modeling is a powerful tool for the regulation and simulation of power electronics converters. Its main disadvantage is that it can predict only the mean value [14]. High frequency ripple is lost or predicted with inaccuracy [15]. In the case of PDM converters, the dc link between the rectifier and the inverter ensures high frequency decoupling. The rectifier’s currents do not have high frequency ripple. The average modeling is thus a well‐adapted tool for the determination of the low frequency side currents in the PDM converters. This technique is already applied successfully to the PDM‐dual converters [16]. In the present work, it is applied for the first time to the PDM converters.

5.1. Average model of ac‐ac PDM converter

5.1.1. Modeling of series resonant inverter

The time is subdivided into half‐periods of resonance. Each half‐period is indicated by an index n. The load voltage switches from udc to +udc at instants n(Tr/2) and from +udc to udc at instants (n+1)(Tr/2) with n even number. The capacitor voltage is as follows:

vC(n+1)=vC(n) A+udc*(1+A) at the end of the (n+1)th half periodE11
vC(n+2)=vC(n+1) Audc*(1+A) at the end of the (n+2)th half periodE12

Under compact form, Eq. (11) and Eq. (12) become:

vC(n)=vC(n1) A+(1)n+1udc*(1+A) with n even or oddE13

Eq. (13) gives the value of the capacitor voltage at the end of the nth half‐period as a function of the value taken at the (n − 1)th half‐period. According to the initial value, Eq. (13) becomes:

vC(n)=(1)n{vC(0) Anudc*(1+A)i=0n1Ai}E14

Knowing that i=0n1Ai=1An1A, Eq. (14) becomes :

vC(n)=(1)n{vC(0) Anudc*(1An)1+A1A }E15

The pic value of load current during the nth half‐period is as follows:

i^(n)=C/L(vC(n)udc)exp(αTr/4) for n oddE16
i^(n)=C/L(vC(n)+udc)exp(αTr/4) for n evenE17

During the nth half‐period, the average value of inverter’s input current is as follows:


Since the initial value of udc is zero, writing Eq. (18) for n = 0 leads to:


It is deduced that


The substitution of Eq. (20) into Eq. (15) yields:

vC(n)=(1)n{π2C/Lexp(αTr/4)i(0) Anudc*(1An)1+A1A }E21

The substitution of Eq. (21) into Eq. (18) yields:

i(n)=i(0) An+udc4πC/Lexp(αTr/4)1A{1An1+A2A}E22

Under the assumption:


(this assumption is justified by the fact that (αTr/2=πξ) is close to zero), expression (22) is identified with that of the current in ReqLeq series branch supplied by a voltage udc with:


The inverter dc side can then be modeled by the average circuit constituted by ReqLeq series branch.

5.1.2. Modeling of PDM inverter

Pulse density modulation is introduced by considering a fictitious hard buck that connects the voltage source to the inverter, represented by its average model. The unit constitutes the average model of PDM inverter (Figure 8). The current drawn by this converter is as follows:

Figure 8.

Average model of PDM inverter.

idc(t)=udcReq{11exp((1d)Tr/τeq)1exp(Tr/τeq)exp(t/τeq)} for 0tdTPDME26
idc(t)=0 for dTPDMtTPDME27

Using Eq. (26) and Eq. (27), the mean value, RMS value and form factor are calculated. We obtain:

FF=d  τeq TPDM (1exp(dTPDMτeq))(1exp((1d)TPDMτeq))1exp(TPDMτeq)d2τeqTPDM(1exp(dTPDMτeq))(1exp((1d)TPDMτeq))1exp(TPDMτeq)+τeq2TPDM(1exp((1d)TPDMτeq)1exp(TPDMτeq))2(1exp(2dTPDMτeq))E30

5.1.3. Extension to ac‐ac converter

Now, we consider that the voltage udc is supplied by a single‐phase diode rectifier. During the jth PDM pattern period, we suppose that this voltage is as follows:


with θj=πq2j12 is the midpoint of jth pattern period.

By substitution of Eq. (31) into Eqs. (28) and (29), we obtain mean value, RMS value and form factor of idc during jth pattern period:


In the appendix, we show that the fundamental component and the RMS value of the current drawn from ac‐supply (Rectifier input current) and the mean and RMS values of the inverter input current during the jth PDM pattern period are linked by the following relationships:


Knowing that in the case of a single‐phase diode rectifier, the displacement factor is unitary, and the power factor is assimilated to the distortion factor:


Substitution of Eqs. (35), (34), (33) and (32) into Eq. (36) yields:

PF=ecq2Facτeq(1exp( ec/q2Facτeq))(1exp((1ec)/q2Facτeq))1exp( 1/q2Facτeq)ecq4Facτeq(1exp( ecq2Facτeq))(1exp((1ec) q2Facτeq))1exp( 1q2Facτeq)+qFacτeq(1e(1ec)q2Facτeq1e1q2Facτeq)2(1e2ecq2Facτeq)E37

The transmitted power is defined by:


Substitution of Eqs. (32) and (34) into Eq. (38) gives the transmitted power in pu:

p=ecq2Facτeq(1exp( ec/q2Facτeq))(1exp((1ec)/q2Facτeq))1exp( 1/q2Facτeq)E39

Its reference is as follows:


The expressions (37) and (39) can be greatly simplified, if we consider the hypothesis:


They become:


To establish the maximum value that q2Facτeq can take without the approximations becoming imprecise, we calculate the relative errors in the most unfavorable case:


It is checked that the most unfavorable case, that is, the errors are maximal, occurs when ec is minimal. For different values of ec,min, we plot these errors versus q2Facτeq (Figure 9). It is noted that the power error is not limited (it increase continuously). Eq. (43) gives values that can be truly erroneous if q2Facτeq is not kept below a maximum value (q2Facτeq )max. This means that in order to maintain a relative error less than a given limit, when ec varies between 1 and ec,min, the coefficient q must respect the constraint:

Figure 9.

Power and power factor errors versus q2Facτeq.

qqmax=(q2Facτeq )max/2FacτeqE46

This constraint means that:

Fcarτeq(q2Facτeq )maxE47



In Figure 9, we can directly read (q2Facτeq )max as a function of the maximum permissible error and for different values of ec,min. If, for example, to maintain the error below 30%, the carrier frequency must be less than the maximum frequency:

Fcar(Fcar)max=0.023/τeq si ec,min=0.1E49
Fcar(Fcar)max=0.119/τeq si ec,min=0.5E50

Eqs. (49) and (50) can be put in the general form:


where Lx(ec,min) is the maximum value that Fcarτeq must not exceed if we want Eq. (43) to give the power with a tolerance less than x when ec varies from 1 to ec,min.

Eq. (26) shows that idc has a static component and a transient component:

idcs(t)=udcReq for 0t(dTPDM=ec/Fcar)E52
idct(t)=udcReq1exp((1d)Tr/τeq)1exp(Tr/τeq)exp(t/τeq) for 0t(dTPDM=ec/Fcar)E53

Eq. (53) shows that the more we reduce Lx(ec,min), the more transient component is damped. Consequently, the currents become:


If the power and the power factor are determined from Eqs. (54) and (55), we find the expressions (42) and (43). This proves that the hypothesis H1, which allowed the passage of Eqs. (37) and (39) to Eqs. (42) and (43), indirectly signifies the predominance of the static component in idc.

5.2. Average model of ac‐ac Multi‐PDM converter (MPDMC)

The converter considered is that shown in Figure 6. By replacing each inverter by its average model, one builds the MPDMC’s average model (Figure 10).

Figure 10.

Average model of MPDMC.

According to this average model, the current drawn by the gth inverter is as follows:

  • zero, if its pattern is at zero:

    iac,g=0 if PDM_Pg=0E56

  • identical to the current drawn by a PDMC if its pattern is at 1, and the patterns of all the other inverters are at zero:

    iac,g=iac if PDM_Pg=1 and PDM_Pjg=0E57

  • identical to the current drawn by a PDMC multiplied by the number of inverters whose patterns are at 1, if its pattern is at 1:


Eqs. (56), (57) and (58) can be written in the form:


The current drawn by the MPDMC is the sum of the currents drawn by the various inverters:


Substitution of Eqs. (59) and (60) into Eq. (55) yields:


Comparing between Eqs. (61) and (55), we see that a M‐PDMC is a PDMC that would be modulated by the square of the sum of the different patterns.


6. MPDMC features: power factor correction and transmitted power

The behavior of the MPDMC is determined by three elements: the control signal, the carrier and the coordination of all the carriers. In this section, we discuss three types of coordination.

6.1. First coordination: interlaced carriers

In Figures 11 and 12, we traced interlaced carriers, the patterns PDM_Pg and (g=1GPDM_Pg)2 in the cases G = 2 and G = 3.

Figure 11.

Interlaced carriers for MPDMC2.

Figure 12.

Interlaced carriers for MPDMC3.

In the case G = 3, when 0ec1/3, we have 1 or 0 pattern at 1:

(g=1GPDM_Pg)2=1 during d(TPDM/3)E62.1.1
(g=1GPDM_Pg)2=0 during (1d)(TPDM/3)E62.1.2
with d=3.eCE62.1.3

when 1/3ec2/3, we have 2 or 1 patterns at 1 :

(g=1GPDM_Pg)2=22 during d(TPDM/3)E62.2.1
(g=1GPDM_Pg)2=12 during (1d)(TPDM/3)E62.2.2
with d=3.eC1E62.2.3

when 2/3ec3/3, we have 3 or 2 patterns at 1 :

(g=1GPDM_Pg)2=32 during d(TPDM/3)E62.3.1
(g=1GPDM_Pg)2=22 during (1d)(TPDM/3)E62.3.2
with d=3.eC2E62.3.3

Eqs. (62) can be generalized as follows:

when (g1)/Gecg/G, we have g or g − 1 patterns at 1 :

(g=1GPDM_Pg)2=g2 during d(TPDM/G)E63.1
(g=1GPDM_Pg)2=(g1)2 during (1d)(TPDM/G)E63.2
with d=G.eC(g1)E63.3
where (g1)=floor(G.eC)E63.4

From Eq. (63), we determine average value and RMS value of (g=1GPDM_Pg)2:


Using Eqs. (64) and (65), we determine transmitted power and power factor :

with d=G.eC(g1)E68
and (g1)=floor(G.eC)E69

We find: (i) the same characteristic power versus control signal as in Section 5 and (ii) the power factor is determined by an analytic expression and not by a summation of the harmonics.

6.2. Second coordination: distribution in uniform bandwidths

Instead of reducing the total harmonic distortion by a mutual compensation of the individual distortions (produced by each inverter), one can reduce it differently: all inverters operate at full power or at standstill, and they do not produce distortion, except one that operates in modulation to ensure power variation. To achieve this correction, the carriers are distributed in uniform bandwidths. All carriers have the same peak value:


In Figures 13 and 14, we plot uniformly superimposed carriers, associated patterns PDM_Pg and (g=1GPDM_Pg)2 in the cases G = 2 and G = 3.

Figure 13.

Carriers distributed in uniform bandwidths, G = 2.

Figure 14.

Carriers distributed in uniform bandwidths, G = 3.

In the case G = 3, Eq. (70) leads to:


when 0ec1/3, we have 1 or 0 pattern at 1:

(g=1GPDM_Pg)2=1 during d.TPDME72.1.1
(g=1GPDM_Pg)2=0 during (1d).TPDME72.1.2
with d=eC/Car^1=3.eCE72.1.3

when 1/3ec2/3, we have 2 or 1 patterns at 1:

(g=1GPDM_Pg)2=22 during d.TPDME72.2.1

(g=1GPDM_Pg)2=12 during (1d).TPDME72.2.2
with d=(eC1/3)/Car^2=3.eC1E72.2.3

when 2/3ec3/3, we have 3 or 2 patterns at 1:

(g=1GPDM_Pg)2=32 during d.TPDME72.3.1
(g=1GPDM_Pg)2=22 during (1d).TPDME72.3.2
with d=(eC2/3)/Car^3=3.eC2E72.3.3

Eqs. (72) can be generalized as follows:

when (g1)/Gecg/G, we have g or g − 1 patterns at 1:

(g=1GPDM_Pg)2=g2 during  d.TPDME73.1
(g=1GPDM_Pg)2=(g1)2 during (1d).TPDME73.2
with d=(G.eC(g1))/(G.Car^g)E73.3
where (g1)=floor(G.eC)E73.4

Using Eq. (73), we determine transmitted power and power factor:

with d=(G.eC(g1))/(G.Car^g)=G.eC(g1)E76
and (g1)=floor(G.eC)E77

It is because the carriers are distributed in uniform bandwidths that power and power factor versus control signal characteristics are the same as in the previous case. The novelty is that the power characteristic is defined by one and only one carrier depending on the value of ec. This is an advantage which facilitates the search of the conditions to correct the non‐linearity of power characteristic.

6.3. Third coordination: distribution in non‐uniform bandwidths

Using Eqs. (74) and (76), we determine the slope of the power characteristic


To linearize this power characteristic, all segments of the power characteristic must have the same slope G2 (because, when eC varies from 0 to 1, power varies from 0 to G2):


It is thus deduced that to linearize the power characteristic, it is necessary that:


The carriers are therefore distributed in non‐uniform bandwidths defined by:


Taking account of Eq. (80), the lower and upper limits of a bandwidth become:


For example, if one considers an MPDMC with three inverters, the three carriers and the three bandwidths are (Figure 15):

Figure 15.

Carriers distributed in non‐uniform bandwidths, G = 3.

Car1 : covers [0 1/9], its pic‐value is Car^1=1/9 and its upper limit: B1=1/9

Car2 : covers [1/9 4/9], its pic‐value is Car^2=3/9 and its upper limit: B2=4/9

Car3 : covers [4/9 9/9], its pic‐value is Car^3=5/9 and its upper limit: B3=9/9

The pattern duty cycle is defined by:

d=ecBLg1BLgBLg1 if BLg1ecBLgE83

Substitution of Eq. (82) into Eq. (83) yields:

d=G2ec(g1)22g1 with (g1)=floor(Gec)E84

Substitution of Eq. (84) into Eq. (74) leads to the expression of transmitted power:


Substitution of Eq. (84) into Eq. (75) leads to the expression of transmitted power:

PF=G2ecG2ec(g2+(g1)2)g2(g1)2 with (g1)=floor(Gec)E86

Eqs. (85) and (86) show that the power characteristic is linear and that the power factor is unitary in G points:

PF=1 when ec=BLg=(g/G)2 or when p=g2 with g=1,2, GE87

7. Simulation results

Simulations are carried out in the Matlab SimPowerSystems environment. We consider a RLC load (1.85 Ω, 20 μH, 90 nF), matching transformer ration 3/10 and an ac‐supply 120 V‐60 Hz. The results of four simulation series are presented. Figures 16 and 17 show examples of currents drawn by a PDMC and MPDMC2. Figures 18 and 19 show the theoretical and simulation results of transmitted power and power factor characteristics in the case of PDMC. Figures 20 and 21 show the theoretical and simulation results of transmitted power and power factor characteristics in the case of MPDMC2 and coordination’s types 1, 2 and 3. We note a good agreement between theoretical and simulation results.

Figure 16.

Current drawn by PDMC, ec=0.5.

Figure 17.

Current drawn by MPDMC2 carriers coordination type 2, ec=0.75.

Figure 18.

Power versus ec characteristic of PDMC.

Figure 19.

Power factor versus ec characteristic of PDMC.

Figure 20.

Power versus ec characteristic of MPDMC2.

Figure 21.

Power factor versus ec characteristic of MPDMC2.


8. Conclusion

The reflections and results presented in this chapter can be divided into two groups: the background and the novelties.

The background includes the PDM control principle, the PDM pattern generation and the characteristics of the ac‐ac PDM converter and ac‐ac Multi‐PDM converter. In the description of the PDM control principle, we deliberately sought to present the PDM control as a form of association based on role sharing between the concepts of soft switching and hard switching. The role of soft switching is to produce lossless switching, while the role of hard switching is to vary the power by deciding the nature of the switching cycles. This reflection on the nature of the PDM control led us to represent the operation of the PDM inverter by a setting in cascade of a chopper and a series resonant inverter. We have detailed a PDM pattern generation method for the ac‐ac PDM converter. It is a method inspired by PWM techniques, but adapted to the specificities of the PDM control (adaptation of the pattern frequency to both the resonant frequency and the ac‐supply frequency). This method is based on a synchronous comparison of a carrier with a control signal and a calibration of the useful period of the dc voltage. Without the detailed, we have given the power transmitted characteristics and the spectrum of the current drawn from the ac‐supply by an ac‐ac PDM converter. Without detailed, we gave the characteristics of the transmitted power and the spectrum of the current drawn from the electrical communication by a ac‐ac PDM converter. The power‐factor correction by a total or partial mutual compensation is presented. It leads to the definition of a converter with several inverters and interlaced carriers. This is the ac‐ac multi‐PDM converter. The behavior of this converter is modeled by a system bi‐converter.

The novelties include mainly the average modeling of ac‐ac PDM converter and ac‐ac multi‐PDM converter and the introduction of carrier coordination as a control parameter of ac‐ac multi‐PDM converter. The application of average modeling leads to the representation of the series resonant inverter by an equivalent RL branch. The replacement of the inverter by its equivalent RL branch in the ac‐ac PDM converter facilitates the analysis of this converter and makes it possible to establish (i) the conditions to preserve the linearity of the power characteristic and (ii) an analytical expression of the power‐factor. The replacement of the inverter by its equivalent RL branch in the ac‐ac Multi‐PDM converter allows modeling this converter by an operating model (a model that integrates the operations of the components of the converter). This makes it possible to envisage several types of coordination. Three types of coordination are presented. Coordination by stratified carriers allows (i) a power‐factor correction based on the search for a minimal distortion (ii) and to linearize the power characteristic.


By subdividing [0 π] into q PDM pattern periods, the expressions of the fundamental component and the RMS‐value of the drawn current are written:


Assuming that q is large enough so that the sin varies very little over the interval [(j1)π/q jπ/q], we write that:


Taking into account Eqs. (A.3) and (A.1) becomes:


Knowing that average and RMS values of idc are as follows:


It is established that:


Substitutions of Eq. (32) into Eqs. (A.7) and (37) into Eq. (A.8) yield:


Knowing that:


Eqs. (A.9) and (A.10) becomes:


Taking into account Eqs. (32) and (33), we obtain:



A(=exp(−αTr/2))Intermediate constant
CLoad’s capacitor
Fac (Tac)Ac‐supply frequency (period)
LLoad’s inductor
RLoad’s resistor
Tdc (=Tac/2)Period of voltage rectified
TPDMPDM pattern
TrResonance period
V^acAmplitude of ac‐supply voltage
dDuty cycle of PDM pattern
floorInteger portion
kPDM pattern length
qPDM pattern frequency in pu (FPDM=q2Fac)
α(=R/2L)Attenuation factor
τeq(=Leq/Req)Time constant of RL equivalent branch
ξ(=(R/2)C/L)Damping ratio


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Written By

Abdelhalim Sandali and Ahmed Chériti

Submitted: 22 September 2016 Reviewed: 06 March 2017 Published: 21 June 2017