The chapter is intended to provide the reader with means to reduce low‐frequency noise in Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET). It is demonstrated that low‐resistivity source and drain electrodes can greatly lower the low‐frequency noise level by suppressing their contribution to the total noise. Furthermore, new plasma processes having the advantages to work at low electron temperature can achieve a further reduction, thanks to the fabrication of a better gate oxide and to a reduction of damages generally induced by conventional plasma processes. Reducing the impact of the traps on the carrier flowing inside the channel by burying the channel can also achieve a reduction of the noise level, but unfortunately at the cost of a degradation of the electrical performances. Finally, the noise analysis of the low‐frequency noise in accumulation‐mode MOSFETs showed that these newly developed devices have a lower noise level than conventional structures, which, in addition to their superiority in term of electrical performances, establishes them as a serious platform for the next Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor (CMOS) technology.
- low‐frequency noise
- radical oxidation
- series resistances
- fabrication process
Since the dawn of electronics more than 50 years ago, manufacturers have been providing customers with faster and smaller chips by fabricating increasingly better devices and improving processes. The main strategy adopted has been to shrink the gate size of the MOSFETs to improve chip performances, especially speed. Since the signal‐to‐noise ratio was large enough, the noise was not an issue and its reduction dragged very little effort among the scientific community. After a steady working frequency doubling every year, the recent downscaling of the dimension has led to high stress and increased variability and, in turn, stagnation of performances of chips. There is no doubt that the increased noise is to blame for that standstill, even if other problems such as the doping concentration could be implicated as well. Nevertheless, the distinction between noise and signal has become critical and the noise issue must be tackled. A suppressed noise level should pave the way to once again lower biases leading to less heat, better reliability, and better performances.
Noise is a fluctuation of a quantity that shifts back and forth with uncertainty. In electronics, it is generally noted as a fluctuation of the voltage or current around its mean value and is ascribed to stochastic events which find their origin at a microscopic level trough the discrete nature of the transport or the Brownian nature of the carrier. There are several types of noises such as thermal noise, shot noise, generation‐recombination noise, inter‐band noise, and low‐frequency noise. They are generally classified upon their origin. Among these, the thermal noise and low‐frequency noise are of paramount importance in MOSFETs, with the latter one being of most concern since its origin is still in debate and that its evaluation for a given technology is made extremely difficult. Even if the low‐frequency noise has been a limiting factor of performances for analog circuits for several years, it has recently become as well an issue for digital ones. Indeed, even though its limitation applies in the low range of frequency, it is up‐converted into phase noise leading to time domain instabilities and therefore problems in the high‐frequency range. Its reduction is therefore mandatory not only for analog but also for digital circuits.
In Section 1, the theory of the low‐frequency noise in MOSFETs is briefly reviewed. While Sections 2 and 3 present new technologies to suppress it by the means of, respectively, silicide and damage free processes, Sections 4 and 5 introduce improved MOSFETs. Thus, the results regarding buried‐channel and accumulation‐mode MOSFETs are reported, respectively, in Sections 4 and 5.
2. Low‐frequency noise in MOSFETs
The MOSFET is a complex device composed of purely resistive parts surrounding the channel whose resistance is controlled by the bias applied at the gate electrode. It is therefore natural that the noise generated inside each region is propagating up to the source and the drain electrodes. However, the noise stemming from the channel is generally the most dominant one, even though the one coming from the surrounding areas can play an important role and can even take over as the main noise source . Figure 1(a) shows a schematic of a MOSFET structure while Figure 2(b) represents its equivalent noise circuit. The source access resistance, the drain access resistance, and the channel are the three main regions the noise is coming from and the total measured noise
It is worth noticing that
which represents the normalized noise of the current
His theory has been confirmed afterward by several researchers and is now well accepted among the scientific community. Within this theory, the noise is given by 
3. Source and drain contacts
When it comes to low‐frequency noise, the contribution stemming from the source and drain access series resistances is generally overlooked. This negligence can have tremendous impact on the noise analysis especially at high gate voltage where their contribution will mostly take over as the dominant noise.
As a matter of fact, this is not the noise generated inside the source and drain access series resistances, which is at stake but their contribution. Rather than reducing the noise sources, reducing their contribution is more efficient and easier. Indeed, the reduction of the resistance of the source and drain access contacts does not only mean a better drivability and a better transconductance but can guarantee a reduction of the propagation of the noise generated by the noise sources inside the contacts and, in turn, a reduction of the contribution of the source and drain contact noise to the total measured noise . The performance improvement of CMOS has become of paramount importance with scaled dimension. Much effort is being made to increase the carrier mobility by several means such as strained technology , different silicon orientation , or even different semiconductor . The reduction of the source and drain electrode series resistances is another means to improve the drivability and silicide has already been used for such purposes. Nitride alloy silicide is widely used to lower the Schottky barrier height to either n+ or p+ silicon down with contact resistance as low as 2 × 10–9 Ω cm2 in the best case . A new structure  and new processes  have been developed in order to further lower down the series resistances. Instead of using the same silicide for both p‐ and n‐MOSFETs, erbium has been selected to perfectly fit the requirement of n‐MOSFETs and palladium for the p‐MOSFETs. Additionally, tungsten metal stack above the thin silicide layer was introduced to reduce the sheet resistance and protect erbium from being oxidized. In order to confirm the above statement, two kinds of MOSFETs have been fabricated following the very same process flow, except during the source and drain contact fabrication stage. The source and drain contacts of the reference transistors have been fabricated with aluminum (Al), while erbium silicide associated with tungsten (ErSi2/W) has been used for the second set of transistors. The respective structures have been represented in Figure 3(a) and (b). While both wafers followed the same process flow until the contact lithography step, the ErSi
The wafer has been then loaded in lamp annealing chamber to finally form ErSi
4. Radical oxidation
The gate stack, especially, the gate insulator, is the most critical part of the MOSFET, mainly because of the defects that can appear during the fabrication and its tremendous impact on the device performance . It is absolutely true these days that the need of always‐faster devices and smaller chips also promote the appearance of undesirable effects such as increase of variability and random telegraph noise. Thermal oxidation has been the way, since the establishment of the MOSFET, to fabricate the gate insulator and while the generated SiO2 was at the beginning of poor quality, leading to high
Thermal oxidation, from its intrinsic chemical reaction, cannot be optimized anymore and will always promote the formation of damage (either inside the gate stack or cap layers) and will partly invalidate the flattening process and, in turn, deteriorate the surface roughness of the wafer. Thus, new oxidation processes have been developed to avoid these issues. They are all based on radical oxidation rather than chemical reaction to form SiO2 . The specificity of the damage‐free very low electron temperature microwave exited high‐density plasma is, as represented in Figure 6, that it can be employed for oxidation at low temperature, chemical vapor deposition, or even reactive ion etching. Very high quality gate insulator and reduced damages generally occurring during the etching and the fabrication of interconnect can be achieved thanks to this advanced process as shown in Figure 7 [15, 18, 19]. Contrary to the thermal oxidation, the radical oxidation has an oxidation rate that is almost regardless of the orientation of the silicon crystal on which the oxide is grown . Additionally, the radical oxidation does not only help reduce the interface trap density but also help preserve and even improve the flatness of the Si/SiO2 interface. Two sets of p‐MOSFETs have been fabricated in our clean room. They followed almost the same process flow; however, they differed in such a way that the first set featuring a radically grown oxide has been processed exclusively with advanced plasma equipment, while the second set has been processed using conventional processes, among which the thermal oxidation process.
Noise measurements have been performed in the linear and saturated region and for different gate sizes. The noise analysis has been carried out at 10 Hz. Results are presented in Figure 8, and they clearly indicate that the p‐MOSFET with a gate oxide fabricated by radical oxidation has a lower noise level than when the thermal oxidation process is used used, with a maximal reduction of over a decade. As expected, the noise stemming from series resistances and the noise from the channel are both contributing to the total noise, with the latter one being ascribed to the insulator charge and induced mobility fluctuations. In order to understand the origin of the noise reduction, the modeling of the p‐MOSFETs, featuring a gate oxide, fabricated by radical oxidation has been carried out. The result is reported in Figure 9 and it revealed an unexpected behavior, i.e., no induced mobility fluctuations. The contribution of the series resistances added to the sole insulator charge fluctuations has been enough to model the total noise. Even though the trapping/release mechanism at the origin of the 1/
5. Buried‐channel MOSFETs
5.1. Structure of buried‐channel MOSFET
The low‐frequency noise, such as 1/
5.2. Low‐frequency noise characteristics
Figure 12 shows the 1/
In the previous section, it is described that the noise can be reduced by introducing the buried‐channel MOSFETs because the channel is separated from the SiO2/Si interface. However, this means the gate capacitance becomes lower compared to the surface channel MOSFETs. Then, the
6. Accumulation‐mode MOSFETs
The separation between the interface and the channel is effective in reducing the noise in buried‐channel MOSFETs; however, the controllability of
The current generated inside the accumulation layer then adds to the bulk current. Therefore, in addition to, among other things, having an improved reliability  and being immune to radiation effects , they also have a better drivability than inversion‐mode MOSFETs since the total current is the sum of those generated inside the SOI and the accumulation layer . When the bulk current has reached its maximum, corresponding to the SOI completely neutral, the majority carrier accumulates at the front interface between the gate insulator and the SOI. Accumulation‐mode fully depleted SOI MOSFETs have been fabricated on Si(100) surface to investigate the noise characteristics. The SOI layer impurity has been adjusted by ion implantation to 2 × 1017 cm–3. The thickness of the SOI layer has been reduced down to 50 nm. In order to avoid the increase of noise due to the defects at the front interface and the impact of the surface roughness of the interface, the radical oxidation  added to the five‐step‐cleaning process  has been repeated four times until reaching a flattened interface with a roughness
The noise of the inversion‐ and accumulation‐mode MOSFETs has been reported in Figure 16. Even though their noise level is similar at low gate overdrive voltage, the superiority of the accumulation‐mode MOSFET over the inversion mode one becomes clear for voltage over 0 V. A gap of more than 1 decade is achieved at the best. While the noise of the inversion‐mode MOSFET can be ascribed to the interface traps  and series resistances at high bias , the origin of the noise for the accumulation‐mode one must be investigated with care. Indeed, as discussed earlier, three conduction mechanisms generate the current and are therefore generating their own noise. The modeling of each noise and finally the total modeled noise have been reported with lines in Figure 16. The noise stemming from the front and back interfaces is originating from the interface traps , like for the inversion‐mode MOSFET while the noise from the SOI layer and access resistances is explained in terms of fundamental fluctuations of the mobility of the Hooge model . Contrary to the inversion‐mode MOSFET, the front interface does not contribute to the total noise. The lower noise can be attributed to a change in the origin of the noise stemming from the channel, with the SOI region becoming the main contributor to the noise with regard to the channel and a significant shift toward the high gate voltage to turn the accumulation layer on. It is worth mentioning that the advantage of the accumulation‐mode MOSFET is effective for high doping concentration; otherwise, the accumulation layer will act like an inversion one  since it implies no contribution from either the back interface or the SOI layer to the total current.
In this chapter, we reviewed several ways to suppress the low‐frequency noise of MOSFETs and, in turn, the noise of analog and digital circuits. One of the most underrated approaches is to optimize the contacts and interconnects by the means of low‐resistive materials, so that their contribution to the total noise can be drastically reduced. It has also been shown that a great deal must be paid to the fabrication processes. Indeed, the use of processes demonstrating very low damage generation at all the stages of fabrication can lead to MOSFETs with better performances and especially reduced noise level due to a reduction of induced defects located at the gate stack and its surroundings. Additionally, these low‐defect processes based on the damage‐free, low‐temperature, high‐density plasma technology achieved a further reduction by means of the disappearance of one component of the low‐frequency noise, the induced mobility fluctuations one, bringing the noise of MOSFETs to the sole fluctuations of the insulator charges. Focusing on a different electronic structure can also achieve low‐noise MOSFETs. For example, minimizing the interaction carrier‐traps by moving away the channel – so that fewer traps are activated and less variations of the insulator charge are generated – can achieve a reduced noise. Unfortunately, this reduction is obtained at the cost of a degradation of the electrical performances. So, the most promising structure to suppress noise is in the form of the accumulation‐mode MOSFETs. Indeed, in addition to offer reduced low‐frequency noise when compared to conventional MOSFETs, their electrical performances are greatly improved. These devices obviously feature various assets, which should consequently pave the road for a new era of very low noise and high‐performance MOSFETs and bring microelectronic manufacturers back to the realization of highly performances and high‐speed analog and digital circuits.
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