Over the past few years tremendous progress has been made on the process, application, device physics and compact modeling of nanowire MOSFETs. We would like to review the above aspects of silicon-based nanowire, focusing on its crucial compact models and the circuit performance demonstration based on our group research work and understanding on nanowire MOSFET progress.
Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. Both the top-down (Singh et al., 2008) and bottom-up (Lu & Lieber, 2006) approaches are widely studied to prepare ultra small nanowire. With bottom-up method, nanowires are generally synthesized by using metal nanoclusters as catalysts via a vapor-liquid-solid process (Lu & Lieber, 2006). After growth nanowires are transferred to silicon substrate to form FET structure. With top-down technique there are various fabrication approaches, such as hard mask trimming, etching in H2 ambient and stress limited oxidation (Singh et al., 2008). 5-nm gate length device has been demonstrated (Liow et al., 2008). Nanowire MOSFETs prepared with both methods find application in logic circuits (Singh et al., 2008), memory (Singh et al., 2008) and sensors (Stern et al., 2008).
Due to the quantum confinement in cross section of nanowire MOSFETs, especially of nanowires with diameter smaller than 15nm, electron mobility behaves differently from its bulk counterpart. Phonon-limited electron mobility decreases with reducing the wire size (Kotlyar et al., 2004) while total electron mobility is enhanced due to volume inversion at high transverse field (Jin et al., 2007). Although whether or not ballistic transport can occur in the silicon nanowire MOSFETs with ultrasmall channel length is disputable (Ferry et al., 2008), it deserves our attention. In the ballistic transport regime, carrier scattering in the device channel is totally suppressed. The study of ballistic transport in nanowire MOSFETs provides the upper limit to their performances. Under extreme scaling of nanowire MOSFETs, the atoms in nanowire cross section are countable. It is believed that the change in bandstructure of one dimensional nanowire influences the device performances (Neophytou et al., 2008). The above mentioned phenomenon are studied and simulated with various numerical approaches and also need to be accounted for in the advanced compact models.
Compact models for silicon nanowire MOSFETs have been developed for design and simulation of nanowire-based circuits. They also provide guides for optimal device design. Natural length theory of nanowire MOSFETs sets the criterion of optimizing device parameters, e.g. the radius, oxide thickness to maintain electrical performance. Superior to Plummer’s work, Taur’s scaling theory (Yu et al., 2008) takes into account the lateral distribution of gate oxide field and allows consideration of relatively thicker high-k dielectric. Core models of undoped nanowire MOSFETs where quantum effect is not significant are well established (Iñíguez et al., 2005; Bian et al., 2007; He J. et al., 2007). By rigorously solving Poisson’s equation in polar coordinate, the electrostatic potential distribution in cross section of nanowire is obtained. Combined with Pao-Sah’s drift-diffusion formula, current characteristics of long channel ideal nanowire MOSFETs are derived. Following Ward’s channel charge partition scheme, terminal capacitance models are obtained. Various forms of this core model exist, such as charge-based (Iñíguez et al., 2005), potential-based (Bian et al., 2007) and carrier-based (He J. et al., 2007) model. Each has its own advantages. Potential-based model is further used to explain the dynamic depletion effect in nanowire (Zhang L. et al., 2009a), while charge-based model has been extended to cover the doped nanowire MOSFETs (Yang et al., 2008). In order to accurately reproduce the electric performances of nanowire MOSFETs, advanced effect models are integrated into the core model frame, e.g. short channel effects, quantum confinement effects, velocity saturation effect (Zhang L. et al., 2009b), etc. A preliminary compact model for silicon nanowire MOSFETs is presented in (Yang et al., 2008) where several advanced effect models are included as optional modules. Another capacitance based analytic model of ballistic silicon nanowire is also given in (Wang, 2005).
Working out an analytic model covering ballistic and diffusive transport and also realizing transition between both (Michetti et al.,2009) is another challenging task. With the above mentioned preliminary compact model for silicon nanowire MOSFET implemented into circuit simulations by Verilog-A, several representative logic circuits are simulated (Yang et al., 2008).
Current status process, device physics, simulation and modeling of silicon-based namowire MOSFETs is reviewed, and the circuit performance is also analyzed. Moreover, the future possible trend of nanowire MOSET is finally outlined in this chapter.
2. Nanowire fabrication process
Silicon nanowire (SiNW) transistors have shown promising potential to revolutionize the applications of electronic, optical, chemical and biological devices (Black, 2005；Barrelet et al.,2004; Ramanathan et al., 2005; Hood et al., 2004). The conventional approach for the fabrication of silicon nanowires is a bottom-up approach from one of many pathways ranging from chemistry, laser-assisted or e-beam directed patterning (Cui et al., 2001a) in a controllable fashion down to sub 10nm diameter in width. One of the many established methods is by nanocluster assisted vapor-liquid-solid (VLS) growth mechanism in which metal nanoclusters mediate the nanowire growth. A more subtle approach of the bottom-up method for the patterning of silicon nanowires is by laser-assisted catalytic growth (Zhang, Y. F. et al., 1998). A bottom-up formation approach is advantageous for creating small silicon nanowires. However, the orientation growth of the wires is a major issue and the repeatability for device use is highly challenging. The formation of silicon nanowires from the top-patterning takes a completely different philosophy from the chemical or laser-assisted method. It relies on the grid formation on standard mask and transformation onto the silicon wafer surface. Due to the limitations of photo-lithography, mostly top-down controlled patterning methods have been developed by successive stress-limited oxidation. One possible method is by thermal oxidation of silicon pre-cursor under refinement (Liu et al., 1993). The starting Si columns are first patterned by Reactive-Ion-Based techniques to refine very small dimensions of silicon pattern, allowing for a series of thermal oxidation with controlled temperature and time. Due to the accumulated stress, the oxidation rate becomes extremely slow and results in the formation of silicon nanowires. Silicon pillars down to 2nm in diameter have been successfully fabricated by stress-limited oxidation (Liu et al., 1994; Kedzierski et al., 1997).
2.1. Single nanowire fabrication
2.1.1. Top-down method
The formation of Silicon Nanowire from the top-patterning takes a completely different philosophy than the chemical or laser assisted method (Kedzierski et al., 1997). It relies on the grid formation on standard mask and transformation onto the silicon wafer surface. Unfortunately, the common challenge of photo-lithography is the definition limit due to the physical obstruction of visible light. Numerous methods are proposed to stretch the top-down patterning limit since silicon nanowires are widely studied. One possible method is by thermal oxidation of silicon pre-cursor under refinement as shown in Figure 1. A small silicon is firstly patterned by Reactive-Ion-Based techniques to refine very small dimensions of silicon pattern allowing for a series of thermal oxidation with controlled temperature and exposure time. Due to the surrounding stress developed at the silicon outer wall, the inside of silicon gradually decreases and results in trends of silicon nanowires.
This method is also applied onto Silicon-On-Insulator based materials (Black, 2005) to promote better stress limiting effect such that more rounded silicon cores are formed as shown in Figure 2. The extra buried oxide layer under the device silicon acts as a relieve site for oxidation flow promotion. In other words, the oxidation rate around the silicon is isotropic and hence the stress is evenly distributed along the surface. As a result, better control rates on the silicon cross-section can be achieved.
2.1.2. Bottom-up method
The fabrication of silcon nanowire comes from many pathways ranging from chemistry, laser assisted or e-beam directed patterning (Cui et al., 2001a) in a controllable fashion down to sub 10nm diameter in width. One out of the many established method is by nanocluster assisted vapor-liquid-solid (VLS) growth mechanism in which metal nanoclusters mediate the Nanowire growth. The size of the metal catalysts determines the diameter of the Nos implying that with a narrow size distribution could be obtained by exploiting well-defined catalysts. High single-crystallinity configuration is reached by the chemical controlled method; however, the drawback is an uncontrolled growth orientation which deters its motivation for transistor application use.
A more subtle approach of the bottom-up method as shown in Figure 3 for Silicon Nanowire patterning is by laser assisted catalytic growth (Zhang, Y. F. et al., 1998). The energy and pulsed controlled laser beam with sub-UV wavelength range is capable of cutting tiny target Silicon element site followed by a high temperature vapor condensation with the addition of metallic nano chemical cluster. The ablated silicon-metallic served as a growing site for silicon reaction growth in the liquid state under extremely high temperature. After cooling, the grown silicon solidities and results in strands of nanowires with better crystallinity and straightness. The above mentioned bottom-up formation approach is advantageous in creating small dimensions silicon nanowires (Figure 4). However, the orientation growth of the wires is a major issue and the repeatability for device use is highly challenging.
2.2. Multiple nanowire
The nanowires discussed above are single wires with localized shrinkage at a direct point of location (Black, 2005). As mentioned above, the excitement of multiple wires is the capability to increase the current throughput due to the carrier transport limitation for each single wire. The fabrication process for multiple wires is much complicated due to the replicating challenge for multiple patterns, or the ability to define grids in the multiple directions. A horizontal pitched silicon nanowire is shown by applying self-alignment of diblock copolymer films on an already lithographically defined mask (Figure 5). The interaction between the photo resist and co-reacting polymer aids to sub-divide the nano patterns into more and refined line structures (Bera et al., 2008). The promotion of multiple wires in the vertically direction is also proposed but with much greater challenge. One difficulty of vertical wires is the ability to control the vertical pitches. This problem can be resolved by utilizing the crystallinity orientation of silicon lattice structure along different direction. The existence of KOH etch is known for highly crystallinity oriented disruption. By splitting the crystal orientation, different etch planes are exposed and therefore oxidation of the structure will separate the silicon into different regions as shown in Figure 6. It is seen the above method has limitation to double silicon nanowires. To extend the number of small wires, another approach is proposed by utilizing the Si/SiGe technology (Namatsu et al., 1997). A stacked heterogeneous layer of mega structure is used to generate different silicon sites. The pattern precursor is then subjected to conventional oxidation process which than leaving multiple wires behind. This is currently the most reliable repeating process with virtually no limit on the number of stacked cores to be formed (Figure 7).
2.3. Vertically stacked nanowire process
The advantage of multiple wires is the capability to increase the current throughput with an increasing number of conducting channels. However, horizontal stacking increases the integration density and vertical pillars are hard to integrate into a traditional planar technology. A vertically stacked silicon nanowire concept has been introduced resulting in an increase in the drive current without impacting the density of integration (Fang et al., 2007).
Fabricating horizontal SiNWs using self-limiting oxidation has also been proposed (Liu et al., 2007). Silicon lines are defined on silicon-on-insulator with an electron beam lithography followed by metal liftoff process and silicon plasma etching. Low temperature oxidation is then used to shrink these lines to a sub-10 nm diameter. But the resulting geometry and shape of the nanowire are difficult to control and need sophisticated equipments and process control. A more controllable method has been demonstrated to fabricate horizontal nanowires using a multi-material system such as Si/SiGe/Ge/SiGe stacks (Bera et al., 2006; Dupre et al., 2008) but the process requires careful handling of the hetero-material interface. Among the methods to form vertical nanowires, the Bosch process plus stress-limited oxidation is the simplest in terms of the equipment needed.
2.3.1. Bosch process plus stress-limited oxidation approach and advantage
Figure 8 shows the key steps of the process to form vertically stacked nanowires. First, the Bosch Process is repeated by ICP to form a scallop pattern along the sidewall of a tall silicon ridge. Then stress-limited oxidation trims down the narrow region at the silicon ridge to form stacked nanowires (Ng.et al.,2007, 2009).
The active area is defined by a high resolution photo lithography on an oxide hardmask. The Bosch cycle technique (Chang et al., 2005) was employed to create a periodic sidewall profile by balancing the ICP etch and passivation step in each cycle. After the first etching phase, the patterned bulk-Si is first masked by a C4F8-based resistant polymer before the subsequent SF6 plasma etches in the unprotected region. ICP etch is proceeded for 7 seconds under C4F8 (15sccm), SF6 (45sccm), O2 (5sccm) at 600W. The passivation cycle continues for 5.2 seconds under C4F8 (75sccm) at 200W. The scallop pattern that results from this process is shown in Figure 9(a). The widths of the ridges and troughs are controlled by the initial lithography and the etch time versus the passivation time in each cycle. After forming the
scallop pattern, dry oxidation at 1000º C is performed to consume the narrow region of the silicon ridge and isolate the nanowires. The evolution of the process with time is shown in the SEM images in Figure 9(b)-(d). The oxidation is self-limiting due to the stress resulting from the volume expansion during the formation of the silicon dioxide as shown in Figure 9. It is noted that for an initial mask width of 100nm, the entire silicon ridge is consumed. For an initial mask width of 200nm and 300nm, the oxidation is self-limiting as shown in Figure 10. A reduction of oxide thickness (negative oxidation rate) is observed after prolonged oxidation due to the oxide densification effect. It should be noted that the oxide hardmask facilitates the removal of the incomplete ridge at the top of the silicon nanowire stack as illustrated in Figure 8(e) and (f) so that the dimensions of the stacked nanowires become more uniform.
By controlling the initial width of the wide and narrow regions of the silicon ridges the vertical separation between the wider regions, elliptical and even triangular nanowires can be formed. To ensure the nanowires can be separated, the width of the narrow regions of the ridge should be less than 200nm. Due to the curvature effect, oxidation is in general slower at the narrow regions. As a result, wide regions should be at least 100nm wider than the narrow regions to form the residual nanowires after prolonged oxidation. Despite the different crystal orientation, the oxidation rate after the nanowire separation is quite uniform in all directions regardless of initial shape and dimension. This observation is due to the nature of the stress-limited process rather than the reaction rate limited process.
Therefore, vertically stacked SiNWs have been successfully fabricated using Inductive Coupled Plasma etching followed by stress-limited oxidation through a careful design process and optimization. Since the SiNW is trimmed from the Si wafers, the single crystal property of the SiNW is maintained when observed from the atomic plane, showing the existence of the crystallographic alignment. The shape and size of the nanowires can be controlled by varying the process conditions.
3. Silicon-based nanowire MOSFETs modeling and simulation
3.1. Core model for undoped nanowire
As a result of the interest in implementing SRG MOSFET to extend the scaling of CMOS technology, physics-based models are important in electrical circuit simulators to predict the performance of circuits when these devices are in use. It is well known that a complete surrounding-gate MOSFET model should not only be used to predict the SRG MOSFET current-voltage characteristics, but also be used in the calculation of terminal charges and various capacitances in the large signal and small signal simulations.
Here, an analytic carrier-based terminal charge and capacitance-voltage compact model for the long channel undoped surrounding-gate MOSFETs is also developed directly from both the current continuity principle and channel charge partition scheme based on our previous theoretical results (He, J. et al.,2004, 2006a). The analytic model is based on the exact device physics and covers all regions of SRG MOSFET operation, from the sub-threshold to the strong inversion and from the linear to the saturation. Terminal charges and trans-capacitances of SRG MOSFETs are calculated with the newly developed model and further compared with the three-dimensional (3-D) numerical simulation.
The coordinate system and energy band used in this work is shown in Figure 11 with r representing the radial distance from the centre of the silicon film and r=R giving the silicon film radius. It is also assumed that the quasi-Fermi level is constant in the radial direction, so that the current flows only along the channel (y direction). The energy levels are referenced to the electron quasi-Fermi level of the source end since there is no body contact in the undoped SRG MOSFETs.
Following the basic device physics of SRG MOSFET (Jiménez et al., 2004; Iñíguez et al., 2005; Moldovan et al., 2007; He, J. et al.,2004, 2006a) under the Gradual-Channel–Approximation (GCA), the solution to the1-D Poisson–Boltzmann equation is valid in terms of the carrier concentration:
where all symbols have their common physics meanings:
is the thermal voltage.
is the silicon intrinsic carrier concentration (at room temperature).
is the induced carrier concentration at the reference coordinate point (at the centre of the silicon film in this study).
is the work function difference between the gate and the channel silicon body.
is the quasi-Fermi-potential with at the source end and at the drain end.
=q2ni/kTεsi is the reciprocal of the square of the intrinsic silicon Debye length.
Based on Poisson’s equation solution, the total inversion charge density is expressed as:
Following Pao-Sah current formulation (Pao & Sah, 1966), the drain current can be written as
where andare the solutions of Eq.(1) corresponding toand, respectively. is the effective mobility, assumed constant here. andare the SRG MOSFET channel width and length, respectively.
In order to simplify the derivation, we define a normalized carrier concentration. As a result, (5) is simplified to.
Based on a similar procedure, the analytic source and drain terminal charges are obtained and the final results are given as follows
The SRG MOSFET is essentially a three terminal device, a nine-capacitance matrix is written as
With the analytical expressions of the three terminal charges formulated, all capacitances are derived as a function of the carrier concentration in the silicon centre and by means of the series law of calculus. The analytical expressions of all nine trans-capacitances can be simplified by using the dependency of the trans-capacitance matrix:
The details of these independent trans-capacitances are displayed in (He J. et al., 2007). Using the derived analytic expressions of the carrier concentrations, terminal charges, and the trans-capacitances, all current-voltage and capacitance-voltage characteristics of a long channel surrounding-gate MOSFET device can be predicted and analyzed with respect to different geometrical parameters and bias operation conditions in Figure 12-18. The detailed discussion is included in (He J. et al., 2007). The validity of the analytical solutions is confirmed by comparing model predictions with simulation data obtained using the 3-D numerical solvers. Through the results and discussion, we get that the explicit expressions to the terminal charges and trans-capacitance not only lead to a more clear understanding of surrounding-gate MOSFET device physics, but also provide a better infrastructure to develop a complete carrier-based model for the surrounding-gate MOSFET based circuit simulation.
A basic feature of the above modeling works is to use an undoped (or lightly doped) body assumption to sustain the theory results. The idea of an undoped body, sometimes referred to as ‘‘intrinsic channel’’, is expected to have special advantages such as the low leakage current, free-statistic dopant fluctuation, and improved short-channel effects. However, the practical SRG MOSFET is always a doped body structure due to a small order unintentional doping) during the real fabrication process. Thus, the undoped body is only an ideal approximation for light and low-doped case in all non-classical CMOS device. The practical SRG device may be designed as a fully depleted MOSFET in order to take the advantages of the undoped body via the low body concentration process and materials. Since the dopant concentration does not only change the surface potential magnitude, but also strongly changes the device sub-threshold slope, an analytic doped SRG MOSFET model is highly desirable for the circuit design and performance test. So a compact model for doping nanowire is showed next.
3.2. Unified core model for dopings in nanowire
Following the carrier-based approach (He, J. et al., 2006a, 2006b) and using a superposition principle, an approximate carrier-based compact model for the fully depleted SRG MOSFETs with a finite doping body is approximately developed directly from both the Poisson equation solution and the Pao-Sah current formulation. The standard cylindrical coordinate formulation of the Poisson-Boltzmann equation in a doped SRG MOSFET is written as:
Where and are the intrinsic silicon concentration and the body doping concentration in the silicon film with the unit of, respectively and are the silicon dielectric constant and the electrostatic potential in respectively. is the cylindrical coordinate in along the radius direction of the silicon film. And are the thermal voltage and the quasi-Fermi-potential in Volt.
The Boltzmann statistics can be expressed as:
Where and are the induced electron concentration in and the electrostatic potential in V at. In a SRG MOSFET, the silicon radius center where the electric field is always zero is chosen as coordinate reference point.
The Poisson equation solution in terms of the carrier concentration can be written as (He, J. et al., 2006a, 2006b)
Where and are the silicon surface and centric potentials in contributed by the induced electron charge. is the Debye length in cm of silicon film with doping concentration of.
Similarly, we obtain the inversion density from the carrier-based Poisson equation solution in (He, J. et al., 2006a, 2006b)
If only the dopant is considered in (14) and the fully depletion approximation is used, the Poisson equation solution in the SRG can be written as
where is the depleted charge density in in the silicon film contributed by the doping atom. and are the silicon surface and centric potentials in contributed by the depletion charge density, respectively.
where and are the total silicon surface potential in and the total charge in contributed by the induced mobile electron charges and the depleted charges, respectively.
Through (21), we can get the surface potential in terms of the carrier concentration.
where, and the complete analytic solution of the Poisson equation is obtained in terms of the carrier concentration:
where is the bulk bias factor.
(24) gives the closed form expression of electron concentration at the silicon film center as a function of bias conditions, dopant concentration, and geometry sizes.
The drain current is written as:
Where and are solutions of (24) corresponding to being the source end voltage andbeing the drain end voltage, respectively. is the effective channel mobility of the SRG MOSFET in. and are the effective channel length and width of the SRG MOSFET in cm, respectively. Note that the can also be expressed as a function of by differentiating (24). Substituting these factors into (25), integrating can be performed approximately yet analytically to yield:
The fully depleted SRG MOSFET characteristics for all operation regions can be predicted from this compact yet continuous, analytic model. The characteristics of surface potential and centric potential for different doped concentrations from the intrinsic undoped assumption are showed in Figure 19and 20, and their relative error is also predicted by the analytic model compared with the 3-D numerical simulation. It is found that the relative error increases with the increase of the body concentration for the given geometry parameters, when the body doping concentration isthe relative error is within the order of 1e-3, but the relative error increases to the order of 1e-2 for the doping concentration up to. Figure 21 and 22 show the comparison of Ids versus VGS and VDS between the analytic solution (curves) and the 3-D simulation (symbols) for the different doping concentration. The SRG MOSFET current predicted by the analytic model shows a good match with the 3-D numerical simulation from the sub-threshold region to the strong inversion region for most doping concentrations.
We should point out that some second-order physics effects of the nanoscale SRG MOSFETs such as short-channel effects, the drain induced barrier lowering effect, and the more important inversion layer quantum effect (QME) are important for the analysis of nanoscale SRG MOSFET although they are ignored in above study to give a clear presentation of the SRG MOSFET charge and capacitance model. For example, the QME drives the peaks of electron concentration away from the interface between the gate oxide and the silicon film,
and pushes the peaks toward the centre of the silicon channel. As a result, the QME causes an increase in the threshold voltage and degradation in the sub-threshold slope, especially with the reduction of the silicon film radius. In addition, the short-channel effects also lead to the threshold voltage reduction and sub-threshold slope degradation with the reduction of the SRG MOSFET channel length. Next, we will introduce second-order physics effects in the compact model of the nanoscale SRG MOSFETs.
3.3. Unified model for nanowire with advanced effects
Starting from Poisson’s equation solution, an accurate inversion charge (Qin) equation is obtained for the long channel SNWTs with arbitrary doped bodies. Moreover, some advanced physical effects such as short channel effects (SCEs), quantum mechanical effects (QMEs), high field mobility degradation and velocity saturation have all been incorporated into the model.
3.3.1. Modeling short channel effects
For the transistor with short channel length, the voltage at the drain terminal has significant impact on the channel potential, known as SCEs. In generally, SCEs induce threshold voltage roll-off, subthreshold slope degradation, drain induced barrier lowering. In addition, channel length modulation and carrier velocity saturation and overshoot become important at short channel length as well. Here, SCEs are modeled following the BSIM5 approach. Assume the surface potential in a short channel device can be expressed as:
Its minimum value, which determines the threshold voltage at a low, is given by:
where is the natural length of SNWT by assuming the highest leakage path lies at the center of the channel. Combiningwith equation of boundary condition, we get a new surface potential solution in terms of inversion charge:
and a inversion charge solution can be obtained:
where is the subthreshold slope (SS);
is the SCEs factor;
is the new threshold voltage;
is the threshold voltage roll-off induced by the SCEs. A drain current expression can further be derived using (32):
Comparison with numerical simulation results shown in Figure 23(a) shows the correctness of the threshold voltage roll-off and DIBL described by the proposed SCEs model. Figure 23(b) shows that the transfer characteristics with subthreshold slope degradation as predicted in the proposed the short channel model. The strong inversion drain current is not affected by the SCEs, which is expected.
3.3.2. Modeling quantum-mechanical (QM) effects and other advanced physical effects
In highly scaled device, the QM confinement of the carrier in the thin silicon channel is significant. As in bulk MOSFETs, the large vertical electric field leads to a strong band bending and carrier confinement at the surface, known as EC as shown in Figure 24. The deviation of the location of peak carrier concentration from the surface decreases the channel carrier concentration and leads a decrease in the gate capacitance (Francis et al., 1992):
where is the effective mass of the electron corresponding to the lowest electric sub-band, and is the average surface field. Besides the EC, there is a strong carrier confinement in nanoscale SNWTs even at low electric fields in the channel. It is because the carriers are confined in a rectangular well formed by the gate insulator around, known as SC. In SC and EC, the conduction band split into several subbands as shown in Figure 24. Since the carriers stays at the subband with the lower energy first, the reduction of the amount of carriers can be modeled by the widening the effective band-gap (Arora, 1993) and replace in (32) by
The simulation results shown in Figure 23(b) illustrates the model can predicted the threshold voltage roll off and gate capacitance degradation induced by QME correctly.
The modeling of other advanced physical effects such as poly-depletion effects and mobility degradation of this work are imported from the BSIM5 approach. Velocity saturation, velocity overshoot and ballistic transport (source-end velocity limit) is handled in a unified way using the saturation charge concept:
where n and m are the only parameters. The effective inversion charge at the source and drain ends are substituted into the final current expression (26) to calculate the device output current. A complete ballistic transport model is not considered in this work, as ballistic transport will not be significant until the channel length is scaled to less than 10nm (Duan et al., 2001). The dc characteristics for a small size SNWT predicted by the complete compact model is demonstrated in Figure 25.
3.4. Ge/Si core/shell nanowire MOSFETs modeling
As one promising molecular device, Ge/Si core/shell nanowire MOSFET has been intensively studied experimentally and theoretically (Xiang et al., 2006; Lu et al., 2005; Fan et al., 2008; Musin & Wang, 2005; Liang et al., 2007; He, Y. et al., 2008) in recent years. Such a device utilizes the bandstructure engineering (Xiang et al., 2006), strain effect (He, Y. et al., 2008) and ballistic transport of 1-dimensional (1D) hole gas (Liang et al., 2007), resulting in very high carrier mobility and excellent performance. At the same time, an analytic compact model is also highly desirable for both physical insight into and performance evaluation of the core/shell based NWFET devices. However, it has not been available so far due to the complexity in analytically modeling the corresponding heterostructure, strain effect and ballistic transport. Nevertheless, some theoretical progresses on non-classical MOSFETs have provided the base for us to develop a primary analytical electrostatic potential model.
Here, starting from Poisson-Boltzmann equation in the Ge/Si core/shell NWFETs, the classical analytic expressions of electrostatic potential and charges in the semiconductor layers are derived out under the gradual channel approximation.
The schematic diagram and corresponding coordinate of a long channel Ge/Si core/shell NWFET are shown in Figure 26, where is the channel direction, is the radial direction, is the thickness of gate dielectric, and are the radii of germanium core and silicon shell, respectively.
The assumed condition in the model derivation include: an abrupt heterojunction between germanium and silicon, an intrinsic or lightly doped body and a long device channel. Quantum confinement and strain effect are neglected for simplicity. Under gradual channel approximation (GCA), the Poisson-Boltzmann equations in Ge/Si core/shell NWFETs are written as the following forms with only hole term considered:
whereis the electrostatic potential, is the self-built voltage of intrinsic Ge/Si heterojunction, is hole quasi-Fermi potential, is the electronic charge, is the thermal potential, and are the intrinsic carrier concentration and permittivity of germanium (silicon), respectively. The Ge/Si core/shell NWFET behaves like a depletion p-channel device due to the band offset between intrinsic germanium and silicon. Hole accumulation in both germanium core and silicon shell are handled while electron is neglected. Also notice that is assumed to be constant along the radius according to quasi-equilibrium approximation, being a negative value for p type device.
For simplicity, a normalized formulation of (41) is used to find its solution in the shell region, the detailed process is showed in (Zhang L. et al., 2008). (41) in the silicon shell layer is solved concisely as:
where and are two intermediary parameters to be decided by the boundary condition, is the Debye length of intrinsic silicon.
And then the radial electric field in the silicon shell layer is obtained:
Similarly, electrostatic potential and electric field in the germanium core layer are given at A=2:
whereis the Debye length of intrinsic germanium. Also the intermediary parameter is evaluated from the boundary condition.
At the interface between silicon and gate oxide layer, surface potential and electric filed are obtained according to the above equation:
Following Gauss’s Law and electric flux continuity condition, we get the final input voltage equation:
Similar to the existing compact models for bulk and other non-planar MOSFET, the input voltage equation and its solution is the base for further developing drain current models and advanced effect models. The detailed solving procedure for (48) is described as follows.
At the interface between germanium core layer and silicon shell layer both the potential and electric flux need to be continuous. So the parameters, andare arrived.
For the studied Ge/Si core/shell structure, it is verified that is always larger than 2 with gate voltage increasing for the Ge/Si core/shell structure. On the other hand, A has an upper limit set which is independent of the bias condition (Figure 27). And the three intermediary parameters are obtained simultaneously by the shooting secant method. After that, interface potential and centric potentialare obtained directly by substituting and into (44), respectively:
Hole charge density in germanium core and silicon shell layers are directly obtained through Gauss’s law:
The total hole charge density in the channel is also obtained as:
Note that represents the charge density per unit area at the interface between the silicon shell and oxide layer while denotes that at the interface between the germanium core layer and silicon shell layer. As a result, gate capacitance of the core/shell structure is obtained by differentiating gate charge with respect to the gate voltage as follows:
In summary, the analytical electrostatic potential equation and its solution are presented above. In this section the analytic potential model is verified through numerical simulation. The physical parameters of silicon and germanium in both the analytical model and numerical simulator are taken from (Sze, 1981). The spatial potential, electric field and hole charge density are obtained under classical device physics through intermediary parameter,and for the given gate voltage, quasi-Fermi potential and structure parameters. So once the three intermediary parameters are solved for the given bias and device geometry, the characteristics of the Ge/Si core/shell structure are directly obtained form the analytic model prediction. The potential, electric field and charge density solution are illustrated in Figure 28-32 for one geometry configuration:,, and in comparison with numerical simulation results. The results show that excellent agreements are observed between the analytic model and the numerical simulation in all these figures and the Ge/Si core/shell heterostucture NWFET exhibits its unique characteristics, much different from a common SRG MOSFET. A more detailed discussion is displayed in (Zhang L. et al., 2008).
4. Nanowire–based circuit simulation
Paralleling the advance of process technology to fabricate SNWT (Cui et al., 2001c; Duan et al., 2001), compact models for the SNWTs have also been developed for circuit simulations in recent years. A general model for doped SNWTs may be very useful for device scientists to optimize the device structure and for circuit designers to evaluate the performance of the SNWT circuits. Here, a design oriented compact model for SNWTs, applicable for a wide range of doping concentrations (i.e. from 1010 to 1019cm-3) and geometrical dimensions is presented. Starting from Poisson’s equation solution, an accurate inversion charge (Qin) equation is obtained for the long channel SNWTs with arbitrary doped bodies. Then a charge based drain current (Ids) expressions is derived. Transconductance (gm), output conductance (gds), terminal charges (Q) and capacitance (Cij) are all derived analytically and verified by TCAD simulation (Synopsys, 2005). And then this model is also implemented in the circuit simulator by the Verilog-A language and its application in circuit simulations is also demonstrated.
The device structure, coordinate system, and corresponding energy band diagram of a doped SNWT studied in this work are shown in Figure 33 (a), (b) and (c), respectively. For an n-type device, the hole Fermi level Efp remains constant along the channel if the current of majority carriers is neglected. Consequently, Efp can be defined as the energy reference level in this work. The 3D Poisson-Boltzmann equation in the SNWT structure is written as
where is the Fermi-potential, is the quasi-Fermi potential, is the channel potential, and is the Debye’s length of the silicon body with doping. All other variables have there usual meanings. All the potentials in this work are normalized by thermal voltage, and the charges by, unless otherwise specified. is the effective oxide capacitance.
This 3D problem is simplified into two separate parts along the vertical and current flow directions. And we get the relationship:
where is the transistor threshold voltage similarly to bulk MOSFET; is the extra part of threshold voltage induced by the special geometric structure of SNWT and is given as the total mobile charge sheet density in the channel.
Through the above equation, the validity of the threshold voltage modeling is verified, see Figure 34， and the characteristics of inversion charge with different condition are got and shown in Figure 35.
The analytical drain current expression is obtained as:
where is the effective mobility in the channel; is the quasi-Fermi potential in the drain terminals; and are normalized inversion charge per unit gate area at the source and drain terminals with
Transconductance and output conductance can be derived analytically from the expressions of drain current:
Analytical expressions for inversion charges at each terminal are desired for efficient transient circuit simulation. For a SNWT, there are three terminal charges, associating with gate, source, and drain, respectively: the gate charge Qg can be computed by integrating the channel charge density along the channel; The drain and source charges, denoted as Qd and Qs, can be derived analytically by using the Ward-Dutton linear-charge-partition method:
where are obtained from the current continuity condition
The model predicted I-V characteristics are verified by comparing with TCAD simulation under various biasing voltages, a wide range of doping concentrations and geometric dimensions as shown in Figure 36. The error between the proposed model and the 3-D numerical simulation is less than 5% with devices with intrinsic to heavily doped body with a doping of 1019 cm-3. The numerical simulation results demonstrate the accuracy of the proposed model from the linear to saturation and from the sub-threshold to strong inversion regions.
In contrast to digital circuits, analog design focus on the first derivatives such as gm/Ids and Cij, which are shown in Figure 37. At Vds=0, Cgs=Cgd and Csg=Cdg in the figures indicate that the developed model has inherent the source/drain symmetry characteristic, which is important for analog and RF applications. Note that the verifications of the core I-V and C-V models are done without any fitting parameters.
The compact SNWT model has been implemented in a commercial circuit simulator ADS2006A by the Verilog-A language to demonstrate practicality of the model. This implementation includes a procedure to produce an initial guess and convergent correction methods to help the nonlinear equation (32) to calculate the inversion charge. DC, ac, and transient simulations of many sample circuits are performed. Figure 38 shows the transient analysis of a 21-stage SNWT ring oscillator by this model. The waveforms of three successive stages are plotted in the figure. Compared with a ring oscillator constructed by DG MOSFETs (Taur et al., 2004), the oscillator frequency in this work is much higher, illustrating a smaller transistor input capacitances relative to the higher current drive in SNWT device. In the case of high parasitic capacitance, parallel connection of several SNWTs can be used.
In this chapter, after a brief outline of the silicon-based nanowire fabrication technology, we discussed simulation and compact model of nanowire MOSFET following the device physics understanding and exploring. In the developed compact model, the short channel effect, quantum mechanic effect and other are analyzed and the predicted results are also compared with the 3-D numerical simulation. Based on such a verified physics based SPICE model, the nanowire based circuit performance is simulated and demonstrated.
This work is supported by the Fundamental Research Project of Shenzhen Science & Technology Foundation (JC200903160353A), the Shenzhen Science & Technology Foundation (CXB201005250031A), and the Industry, Education and Academy Cooperation Program of Guangdong (2009B090300318).