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Silicon-Based Nanowire MOSFETs: From Process and Device Physics to Simulation and Modeling

Written By

Jin He, Haijun Lou, Lining Zhang and Mansun Chan

Submitted: 28 January 2011 Published: 18 July 2011

DOI: 10.5772/16345

From the Edited Volume

Nanowires - Implementations and Applications

Edited by Abbass Hashim

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1. Introduction

Over the past few years tremendous progress has been made on the process, application, device physics and compact modeling of nanowire MOSFETs. We would like to review the above aspects of silicon-based nanowire, focusing on its crucial compact models and the circuit performance demonstration based on our group research work and understanding on nanowire MOSFET progress.

Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. Both the top-down (Singh et al., 2008) and bottom-up (Lu & Lieber, 2006) approaches are widely studied to prepare ultra small nanowire. With bottom-up method, nanowires are generally synthesized by using metal nanoclusters as catalysts via a vapor-liquid-solid process (Lu & Lieber, 2006). After growth nanowires are transferred to silicon substrate to form FET structure. With top-down technique there are various fabrication approaches, such as hard mask trimming, etching in H2 ambient and stress limited oxidation (Singh et al., 2008). 5-nm gate length device has been demonstrated (Liow et al., 2008). Nanowire MOSFETs prepared with both methods find application in logic circuits (Singh et al., 2008), memory (Singh et al., 2008) and sensors (Stern et al., 2008).

Due to the quantum confinement in cross section of nanowire MOSFETs, especially of nanowires with diameter smaller than 15nm, electron mobility behaves differently from its bulk counterpart. Phonon-limited electron mobility decreases with reducing the wire size (Kotlyar et al., 2004) while total electron mobility is enhanced due to volume inversion at high transverse field (Jin et al., 2007). Although whether or not ballistic transport can occur in the silicon nanowire MOSFETs with ultrasmall channel length is disputable (Ferry et al., 2008), it deserves our attention. In the ballistic transport regime, carrier scattering in the device channel is totally suppressed. The study of ballistic transport in nanowire MOSFETs provides the upper limit to their performances. Under extreme scaling of nanowire MOSFETs, the atoms in nanowire cross section are countable. It is believed that the change in bandstructure of one dimensional nanowire influences the device performances (Neophytou et al., 2008). The above mentioned phenomenon are studied and simulated with various numerical approaches and also need to be accounted for in the advanced compact models.

Compact models for silicon nanowire MOSFETs have been developed for design and simulation of nanowire-based circuits. They also provide guides for optimal device design. Natural length theory of nanowire MOSFETs sets the criterion of optimizing device parameters, e.g. the radius, oxide thickness to maintain electrical performance. Superior to Plummer’s work, Taur’s scaling theory (Yu et al., 2008) takes into account the lateral distribution of gate oxide field and allows consideration of relatively thicker high-k dielectric. Core models of undoped nanowire MOSFETs where quantum effect is not significant are well established (Iñíguez et al., 2005; Bian et al., 2007; He J. et al., 2007). By rigorously solving Poisson’s equation in polar coordinate, the electrostatic potential distribution in cross section of nanowire is obtained. Combined with Pao-Sah’s drift-diffusion formula, current characteristics of long channel ideal nanowire MOSFETs are derived. Following Ward’s channel charge partition scheme, terminal capacitance models are obtained. Various forms of this core model exist, such as charge-based (Iñíguez et al., 2005), potential-based (Bian et al., 2007) and carrier-based (He J. et al., 2007) model. Each has its own advantages. Potential-based model is further used to explain the dynamic depletion effect in nanowire (Zhang L. et al., 2009a), while charge-based model has been extended to cover the doped nanowire MOSFETs (Yang et al., 2008). In order to accurately reproduce the electric performances of nanowire MOSFETs, advanced effect models are integrated into the core model frame, e.g. short channel effects, quantum confinement effects, velocity saturation effect (Zhang L. et al., 2009b), etc. A preliminary compact model for silicon nanowire MOSFETs is presented in (Yang et al., 2008) where several advanced effect models are included as optional modules. Another capacitance based analytic model of ballistic silicon nanowire is also given in (Wang, 2005).

Working out an analytic model covering ballistic and diffusive transport and also realizing transition between both (Michetti et al.,2009) is another challenging task. With the above mentioned preliminary compact model for silicon nanowire MOSFET implemented into circuit simulations by Verilog-A, several representative logic circuits are simulated (Yang et al., 2008).

Current status process, device physics, simulation and modeling of silicon-based namowire MOSFETs is reviewed, and the circuit performance is also analyzed. Moreover, the future possible trend of nanowire MOSET is finally outlined in this chapter.


2. Nanowire fabrication process

Silicon nanowire (SiNW) transistors have shown promising potential to revolutionize the applications of electronic, optical, chemical and biological devices (Black, 2005Barrelet et al.,2004; Ramanathan et al., 2005; Hood et al., 2004). The conventional approach for the fabrication of silicon nanowires is a bottom-up approach from one of many pathways ranging from chemistry, laser-assisted or e-beam directed patterning (Cui et al., 2001a) in a controllable fashion down to sub 10nm diameter in width. One of the many established methods is by nanocluster assisted vapor-liquid-solid (VLS) growth mechanism in which metal nanoclusters mediate the nanowire growth. A more subtle approach of the bottom-up method for the patterning of silicon nanowires is by laser-assisted catalytic growth (Zhang, Y. F. et al., 1998). A bottom-up formation approach is advantageous for creating small silicon nanowires. However, the orientation growth of the wires is a major issue and the repeatability for device use is highly challenging. The formation of silicon nanowires from the top-patterning takes a completely different philosophy from the chemical or laser-assisted method. It relies on the grid formation on standard mask and transformation onto the silicon wafer surface. Due to the limitations of photo-lithography, mostly top-down controlled patterning methods have been developed by successive stress-limited oxidation. One possible method is by thermal oxidation of silicon pre-cursor under refinement (Liu et al., 1993). The starting Si columns are first patterned by Reactive-Ion-Based techniques to refine very small dimensions of silicon pattern, allowing for a series of thermal oxidation with controlled temperature and time. Due to the accumulated stress, the oxidation rate becomes extremely slow and results in the formation of silicon nanowires. Silicon pillars down to 2nm in diameter have been successfully fabricated by stress-limited oxidation (Liu et al., 1994; Kedzierski et al., 1997).

2.1. Single nanowire fabrication

2.1.1. Top-down method

The formation of Silicon Nanowire from the top-patterning takes a completely different philosophy than the chemical or laser assisted method (Kedzierski et al., 1997). It relies on the grid formation on standard mask and transformation onto the silicon wafer surface. Unfortunately, the common challenge of photo-lithography is the definition limit due to the physical obstruction of visible light. Numerous methods are proposed to stretch the top-down patterning limit since silicon nanowires are widely studied. One possible method is by thermal oxidation of silicon pre-cursor under refinement as shown in Figure 1. A small silicon is firstly patterned by Reactive-Ion-Based techniques to refine very small dimensions of silicon pattern allowing for a series of thermal oxidation with controlled temperature and exposure time. Due to the surrounding stress developed at the silicon outer wall, the inside of silicon gradually decreases and results in trends of silicon nanowires.

Figure 1.

Stress limited oxidation Silicon Nanowire (From Liu H. et al. Appl. Phys. Lett., Vol. 64, No.11, (Mar 1994))

This method is also applied onto Silicon-On-Insulator based materials (Black, 2005) to promote better stress limiting effect such that more rounded silicon cores are formed as shown in Figure 2. The extra buried oxide layer under the device silicon acts as a relieve site for oxidation flow promotion. In other words, the oxidation rate around the silicon is isotropic and hence the stress is evenly distributed along the surface. As a result, better control rates on the silicon cross-section can be achieved.

Figure 2.

Silicon-On-Insulator based Silicon Nanowire (From Kedzierski J., J. Vac. Sci. Technol. B, Vol. 15, No. 6, (July 1997))

2.1.2. Bottom-up method

The fabrication of silcon nanowire comes from many pathways ranging from chemistry, laser assisted or e-beam directed patterning (Cui et al., 2001a) in a controllable fashion down to sub 10nm diameter in width. One out of the many established method is by nanocluster assisted vapor-liquid-solid (VLS) growth mechanism in which metal nanoclusters mediate the Nanowire growth. The size of the metal catalysts determines the diameter of the Nos implying that with a narrow size distribution could be obtained by exploiting well-defined catalysts. High single-crystallinity configuration is reached by the chemical controlled method; however, the drawback is an uncontrolled growth orientation which deters its motivation for transistor application use.

Figure 3.

Silicon Nanowire prepared by laser ablation method (From Alfredo M. Morales, Science 279, 208 (1998))

A more subtle approach of the bottom-up method as shown in Figure 3 for Silicon Nanowire patterning is by laser assisted catalytic growth (Zhang, Y. F. et al., 1998). The energy and pulsed controlled laser beam with sub-UV wavelength range is capable of cutting tiny target Silicon element site followed by a high temperature vapor condensation with the addition of metallic nano chemical cluster. The ablated silicon-metallic served as a growing site for silicon reaction growth in the liquid state under extremely high temperature. After cooling, the grown silicon solidities and results in strands of nanowires with better crystallinity and straightness. The above mentioned bottom-up formation approach is advantageous in creating small dimensions silicon nanowires (Figure 4). However, the orientation growth of the wires is a major issue and the repeatability for device use is highly challenging.

Figure 4.

Diameter controlled synthesis by single metallic crystal. The scale bar is 20 nm. (From Cui Y., Applied Physics Letters Volume 78, Number 15)

2.2. Multiple nanowire

The nanowires discussed above are single wires with localized shrinkage at a direct point of location (Black, 2005). As mentioned above, the excitement of multiple wires is the capability to increase the current throughput due to the carrier transport limitation for each single wire. The fabrication process for multiple wires is much complicated due to the replicating challenge for multiple patterns, or the ability to define grids in the multiple directions. A horizontal pitched silicon nanowire is shown by applying self-alignment of diblock copolymer films on an already lithographically defined mask (Figure 5). The interaction between the photo resist and co-reacting polymer aids to sub-divide the nano patterns into more and refined line structures (Bera et al., 2008). The promotion of multiple wires in the vertically direction is also proposed but with much greater challenge. One difficulty of vertical wires is the ability to control the vertical pitches. This problem can be resolved by utilizing the crystallinity orientation of silicon lattice structure along different direction. The existence of KOH etch is known for highly crystallinity oriented disruption. By splitting the crystal orientation, different etch planes are exposed and therefore oxidation of the structure will separate the silicon into different regions as shown in Figure 6. It is seen the above method has limitation to double silicon nanowires. To extend the number of small wires, another approach is proposed by utilizing the Si/SiGe technology (Namatsu et al., 1997). A stacked heterogeneous layer of mega structure is used to generate different silicon sites. The pattern precursor is then subjected to conventional oxidation process which than leaving multiple wires behind. This is currently the most reliable repeating process with virtually no limit on the number of stacked cores to be formed (Figure 7).

Figure 5.

Horizontal Multiple Silicon Nanowires. (From, C. T. Black, Applied Physics Letters 87, 163116 2005)

Figure 6.

SiGe based vertical multiple Silicon Nanowire (From L. K. Bera, IEEE IEDM '06, pp. 551-554)

Figure 7.

Twin KOH based Multiple Silicon Nanowire (From Hideo Namatsu, J. Vac. Sci. Technol. B, Vol.15, No.5)

2.3. Vertically stacked nanowire process

The advantage of multiple wires is the capability to increase the current throughput with an increasing number of conducting channels. However, horizontal stacking increases the integration density and vertical pillars are hard to integrate into a traditional planar technology. A vertically stacked silicon nanowire concept has been introduced resulting in an increase in the drive current without impacting the density of integration (Fang et al., 2007).

Fabricating horizontal SiNWs using self-limiting oxidation has also been proposed (Liu et al., 2007). Silicon lines are defined on silicon-on-insulator with an electron beam lithography followed by metal liftoff process and silicon plasma etching. Low temperature oxidation is then used to shrink these lines to a sub-10 nm diameter. But the resulting geometry and shape of the nanowire are difficult to control and need sophisticated equipments and process control. A more controllable method has been demonstrated to fabricate horizontal nanowires using a multi-material system such as Si/SiGe/Ge/SiGe stacks (Bera et al., 2006; Dupre et al., 2008) but the process requires careful handling of the hetero-material interface. Among the methods to form vertical nanowires, the Bosch process plus stress-limited oxidation is the simplest in terms of the equipment needed.

2.3.1. Bosch process plus stress-limited oxidation approach and advantage

Figure 8 shows the key steps of the process to form vertically stacked nanowires. First, the Bosch Process is repeated by ICP to form a scallop pattern along the sidewall of a tall silicon ridge. Then stress-limited oxidation trims down the narrow region at the silicon ridge to form stacked nanowires ( al.,2007, 2009).

The active area is defined by a high resolution photo lithography on an oxide hardmask. The Bosch cycle technique (Chang et al., 2005) was employed to create a periodic sidewall profile by balancing the ICP etch and passivation step in each cycle. After the first etching phase, the patterned bulk-Si is first masked by a C4F8-based resistant polymer before the subsequent SF6 plasma etches in the unprotected region. ICP etch is proceeded for 7 seconds under C4F8 (15sccm), SF6 (45sccm), O2 (5sccm) at 600W. The passivation cycle continues for 5.2 seconds under C4F8 (75sccm) at 200W. The scallop pattern that results from this process is shown in Figure 9(a). The widths of the ridges and troughs are controlled by the initial lithography and the etch time versus the passivation time in each cycle. After forming the

Figure 8.

Nanowire formation by Bosch etching and stress-limited oxidation (From R. M. Y. Ng, IEEE Elect. Dev. Lett, Vol. 30, No. 5, 2009)

scallop pattern, dry oxidation at 1000º C is performed to consume the narrow region of the silicon ridge and isolate the nanowires. The evolution of the process with time is shown in the SEM images in Figure 9(b)-(d). The oxidation is self-limiting due to the stress resulting from the volume expansion during the formation of the silicon dioxide as shown in Figure 9. It is noted that for an initial mask width of 100nm, the entire silicon ridge is consumed. For an initial mask width of 200nm and 300nm, the oxidation is self-limiting as shown in Figure 10. A reduction of oxide thickness (negative oxidation rate) is observed after prolonged oxidation due to the oxide densification effect. It should be noted that the oxide hardmask facilitates the removal of the incomplete ridge at the top of the silicon nanowire stack as illustrated in Figure 8(e) and (f) so that the dimensions of the stacked nanowires become more uniform.

Figure 9.

TEM images showing the time evolution of the nanowire geometry (a) right after the Bosch etching and after (b) 30mins (c) 60mins and (d) 120mins of oxidation (From R. M. Y. Ng, IEEE Elect. Dev. Lett, Vol. 30, No. 5)

Figure 10.

Sidewall oxidation rate at 1000º C in oxygen ambient with different top oxide hardmask widths (From R. M. Y. Ng, IEEE Elect. Dev. Lett, Vol. 30, No. 5)

By controlling the initial width of the wide and narrow regions of the silicon ridges the vertical separation between the wider regions, elliptical and even triangular nanowires can be formed. To ensure the nanowires can be separated, the width of the narrow regions of the ridge should be less than 200nm. Due to the curvature effect, oxidation is in general slower at the narrow regions. As a result, wide regions should be at least 100nm wider than the narrow regions to form the residual nanowires after prolonged oxidation. Despite the different crystal orientation, the oxidation rate after the nanowire separation is quite uniform in all directions regardless of initial shape and dimension. This observation is due to the nature of the stress-limited process rather than the reaction rate limited process.

Therefore, vertically stacked SiNWs have been successfully fabricated using Inductive Coupled Plasma etching followed by stress-limited oxidation through a careful design process and optimization. Since the SiNW is trimmed from the Si wafers, the single crystal property of the SiNW is maintained when observed from the atomic plane, showing the existence of the crystallographic alignment. The shape and size of the nanowires can be controlled by varying the process conditions.


3. Silicon-based nanowire MOSFETs modeling and simulation

3.1. Core model for undoped nanowire

As a result of the interest in implementing SRG MOSFET to extend the scaling of CMOS technology, physics-based models are important in electrical circuit simulators to predict the performance of circuits when these devices are in use. It is well known that a complete surrounding-gate MOSFET model should not only be used to predict the SRG MOSFET current-voltage characteristics, but also be used in the calculation of terminal charges and various capacitances in the large signal and small signal simulations.

Here, an analytic carrier-based terminal charge and capacitance-voltage compact model for the long channel undoped surrounding-gate MOSFETs is also developed directly from both the current continuity principle and channel charge partition scheme based on our previous theoretical results (He, J. et al.,2004, 2006a). The analytic model is based on the exact device physics and covers all regions of SRG MOSFET operation, from the sub-threshold to the strong inversion and from the linear to the saturation. Terminal charges and trans-capacitances of SRG MOSFETs are calculated with the newly developed model and further compared with the three-dimensional (3-D) numerical simulation.

The coordinate system and energy band used in this work is shown in Figure 11 with r representing the radial distance from the centre of the silicon film and r=R giving the silicon film radius. It is also assumed that the quasi-Fermi level is constant in the radial direction, so that the current flows only along the channel (y direction). The energy levels are referenced to the electron quasi-Fermi level of the source end since there is no body contact in the undoped SRG MOSFETs.

Figure 11.

The coordinate system(a) and energy band(b) used in this work. (From He J. IEEE TED, Vol. 54, NO. 6, June 2007)

Following the basic device physics of SRG MOSFET (Jiménez et al., 2004; Iñíguez et al., 2005; Moldovan et al., 2007; He, J. et al.,2004, 2006a) under the Gradual-Channel–Approximation (GCA), the solution to the1-D Poisson–Boltzmann equation is valid in terms of the carrier concentration:


where all symbols have their common physics meanings:

1/β=kT/qis the thermal voltage.

niis the silicon intrinsic carrier concentration (1.14×1010cm3at room temperature).

n0is the induced carrier concentration at the reference coordinate point (at the centre of the silicon film in this study).

Δϕiis the work function difference between the gate and the channel silicon body.

Vchis the quasi-Fermi-potential with Vch=0at the source end and Vch=Vdsat the drain end.

Li2=q2ni/kTεsi is the reciprocal of the square of the intrinsic silicon Debye length.

Based on Poisson’s equation solution, the total inversion charge density is expressed as:


Following Pao-Sah current formulation (Pao & Sah, 1966), the drain current can be written as


where n0sandn0dare the solutions of Eq.(1) corresponding toVch=Vs=0andVch=Vds, respectively. μ0is the effective mobility, assumed constant here. WandLare the SRG MOSFET channel width and length, respectively.

Substituting n0withdVch/dyand the inversion charge expression in Eq. (2) into (3) and performing analytical integration, the carrier-based drain current is obtained:






In order to simplify the derivation, we define a normalized carrier concentrationρ=1R28Li2n0ni. As a result, (5) is simplified toF(ρ)=lnρ+2ρ1+θ(ρ22ρ1).

Based on a similar procedure, the analytic source and drain terminal charges are obtained and the final results are given as follows



M(ρ)=(43ρ-352ρ-2ρ1+13ρρ2lnρ12(lnρ)2)                       +θ(32ρ-4439ρ-3+92ρ-2+2-6ρ+6ρ23ρ3lnρ)                      +2θ2(1 5ρ-5ρ-4+53ρ-3ρ-2)E9



From Eqs.6-9, all three terminal charges of SRG MOSFETs can be analytically calculated from the normalized electron concentration ρs and ρd from the solutions of (1) corresponding to Vch=0 andVch=Vds, respectively.

The SRG MOSFET is essentially a three terminal device, a nine-capacitance matrix is written as

Cij={QiVj       i=jQiVj  ij=[CssCsdCsgCdsCddCdgCgsCgdCgg]E11

With the analytical expressions of the three terminal charges formulated, all capacitances are derived as a function of the carrier concentration in the silicon centre n0s and n0d by means of the series law of calculus. The analytical expressions of all nine trans-capacitances can be simplified by using the dependency of the trans-capacitance matrix:


The details of these independent trans-capacitances are displayed in (He J. et al., 2007). Using the derived analytic expressions of the carrier concentrations, terminal charges, and the trans-capacitances, all current-voltage and capacitance-voltage characteristics of a long channel surrounding-gate MOSFET device can be predicted and analyzed with respect to different geometrical parameters and bias operation conditions in Figure 12-18. The detailed discussion is included in (He J. et al., 2007). The validity of the analytical solutions is confirmed by comparing model predictions with simulation data obtained using the 3-D numerical solvers. Through the results and discussion, we get that the explicit expressions to the terminal charges and trans-capacitance not only lead to a more clear understanding of surrounding-gate MOSFET device physics, but also provide a better infrastructure to develop a complete carrier-based model for the surrounding-gate MOSFET based circuit simulation.

Figure 12.

Terminal charge versus gate voltage for differentVds, compared with the numerical 3-D simulation (symbols) for a long channel undoped surrounding-gate MOSFET with L=1um, tox=2nm, R=20nm, u0=300cm2/Vs, and W=2πR. (From He J. IEEE TED, Vol. 54, No. 6, June 2007)

Figure 13.

Terminal charge versus Vds for different Vgs (From He J. IEEE TED, Vol. 54, No. 6, June 2007)

Figure 14.

Gate trans-capacitance versus gate voltage for different Vds(He J. From He J., IEEE TED, Vol. 54, No. 6, June 2007)

Figure 15.

Gate voltage related trans-capacitances versus Vds (From He J. IEEE TED, Vol. 54, No. 6, June 2007)

Figure 16.

Source terminal trans-capacitances versus Vgs (From He J. IEEE TED, Vol. 54, No. 6, June 2007)

Figure 17.

Drain terminal trans-capacitances versus Vds (From He J. IEEE TED, Vol. 54, No. 6, June 2007)

Figure 18.

Drain related trans-capacitances versusVds (From He J. IEEE TED, Vol. 54, No. 6, June 2007)

A basic feature of the above modeling works is to use an undoped (or lightly doped) body assumption to sustain the theory results. The idea of an undoped body, sometimes referred to as ‘‘intrinsic channel’’, is expected to have special advantages such as the low leakage current, free-statistic dopant fluctuation, and improved short-channel effects. However, the practical SRG MOSFET is always a doped body structure due to a small order unintentional doping(1012cm3~1015cm3) during the real fabrication process. Thus, the undoped body is only an ideal approximation for light and low-doped case in all non-classical CMOS device. The practical SRG device may be designed as a fully depleted MOSFET in order to take the advantages of the undoped body via the low body concentration process and materials. Since the dopant concentration does not only change the surface potential magnitude, but also strongly changes the device sub-threshold slope, an analytic doped SRG MOSFET model is highly desirable for the circuit design and performance test. So a compact model for doping nanowire is showed next.

3.2. Unified core model for dopings in nanowire

Following the carrier-based approach (He, J. et al., 2006a, 2006b) and using a superposition principle, an approximate carrier-based compact model for the fully depleted SRG MOSFETs with a finite doping body is approximately developed directly from both the Poisson equation solution and the Pao-Sah current formulation. The standard cylindrical coordinate formulation of the Poisson-Boltzmann equation in a doped SRG MOSFET is written as:


Where ni and Naare the intrinsic silicon concentration and the body doping concentration in the silicon film with the unit ofcm3, respectively εsi and ϕ are the silicon dielectric constant and the electrostatic potential in Volt respectively. ris the cylindrical coordinate in cmalong the radius direction of the silicon film. 1/βAnd Vare the thermal voltage and the quasi-Fermi-potential in Volt.

The Boltzmann statistics can be expressed as:




Where n0 and ϕ0 are the induced electron concentration in cm3and the electrostatic potential in V atr=0. In a SRG MOSFET, the silicon radius center where the electric field is always zero is chosen as coordinate reference point.

The Poisson equation solution in terms of the carrier concentration can be written as (He, J. et al., 2006a, 2006b)


Where ϕSI and ϕ0I are the silicon surface and centric potentials in Voltcontributed by the induced electron charge. LD=εsikT/q2Nais the Debye length in cm of silicon film with doping concentration ofNa.

Similarly, we obtain the inversion density from the carrier-based Poisson equation solution in (He, J. et al., 2006a, 2006b)


If only the dopant is considered in (14) and the fully depletion approximation is used, the Poisson equation solution in the SRG can be written as


where Qb is the depleted charge density in Ccm2in the silicon film contributed by the doping atom. ϕsBand ϕ0B are the silicon surface and centric potentials in Vcontributed by the depletion charge density, respectively.




and (4) plus (5):


where ϕs and Qtot are the total silicon surface potential in Vand the total charge in Ccm2 contributed by the induced mobile electron charges and the depleted charges, respectively.

Through (21), we can get the surface potential in terms of the carrier concentration.


whereα2=qNaR216εsi, and the complete analytic solution of the Poisson equation is obtained in terms of the carrier concentration:


where γ=2qεsiNaCox is the bulk bias factor.

(24) gives the closed form expression of electron concentration at the silicon film center as a function of bias conditions, dopant concentration, and geometry sizes.

The drain current is written as:


Where n0S and n0D are solutions of (24) corresponding to V=0 being the source end voltage andV=Vds being the drain end voltage, respectively. μis the effective channel mobility of the SRG MOSFET incm2/V.s. Land W=2πR are the effective channel length and width of the SRG MOSFET in cm, respectively. Note that the dV/dy can also be expressed as a function of n0 by differentiating (24). Substituting these factors into (25), integrating can be performed approximately yet analytically to yield:




The fully depleted SRG MOSFET characteristics for all operation regions can be predicted from this compact yet continuous, analytic model. The characteristics of surface potential and centric potential for different doped concentrations from the intrinsic undoped assumption are showed in Figure 19and 20, and their relative error is also predicted by the analytic model compared with the 3-D numerical simulation. It is found that the relative error increases with the increase of the body concentration for the given geometry parameters, when the body doping concentration is1e16cm3the relative error is within the order of 1e-3, but the relative error increases to the order of 1e-2 for the doping concentration up to1e17cm3. Figure 21 and 22 show the comparison of Ids versus VGS and VDS between the analytic solution (curves) and the 3-D simulation (symbols) for the different doping concentration. The SRG MOSFET current predicted by the analytic model shows a good match with the 3-D numerical simulation from the sub-threshold region to the strong inversion region for most doping concentrations.

We should point out that some second-order physics effects of the nanoscale SRG MOSFETs such as short-channel effects, the drain induced barrier lowering effect, and the more important inversion layer quantum effect (QME) are important for the analysis of nanoscale SRG MOSFET although they are ignored in above study to give a clear presentation of the SRG MOSFET charge and capacitance model. For example, the QME drives the peaks of electron concentration away from the interface between the gate oxide and the silicon film,

Figure 19.

a) the comparison of the surface potential versus gate voltage curves for five different doped concentrations and (b) the relative error of the surface potential. (From He J. Semicond. Sci. Technol. 22 (2007) 671–677)

Figure 20.

a) the comparison of the centric potential versus gate voltage curves and (b) the resultant relative error(from He J. Semicond. Sci. Technol. 22 (2007) 671–677)

Figure 21.

Ids versus VGS and compared with the 3-D numerical simulation (from He J. Semicond. Sci. Technol. 22 (2007) 671–677)

Figure 22.

Ids versus VDS and compared with the 3-D numerical simulation (from He J. Semicond. Sci. Technol. 22 (2007) 671–677)

and pushes the peaks toward the centre of the silicon channel. As a result, the QME causes an increase in the threshold voltage and degradation in the sub-threshold slope, especially with the reduction of the silicon film radius. In addition, the short-channel effects also lead to the threshold voltage reduction and sub-threshold slope degradation with the reduction of the SRG MOSFET channel length. Next, we will introduce second-order physics effects in the compact model of the nanoscale SRG MOSFETs.

3.3. Unified model for nanowire with advanced effects

Starting from Poisson’s equation solution, an accurate inversion charge (Qin) equation is obtained for the long channel SNWTs with arbitrary doped bodies. Moreover, some advanced physical effects such as short channel effects (SCEs), quantum mechanical effects (QMEs), high field mobility degradation and velocity saturation have all been incorporated into the model.

3.3.1. Modeling short channel effects

For the transistor with short channel length, the voltage at the drain terminal has significant impact on the channel potential, known as SCEs. In generally, SCEs induce threshold voltage roll-off, subthreshold slope degradation, drain induced barrier lowering. In addition, channel length modulation and carrier velocity saturation and overshoot become important at short channel length as well. Here, SCEs are modeled following the BSIM5 approach. Assume the surface potential in a short channel device can be expressed as:


whereϕs0is the solution of the 2D Poisson’s equation. After substituting (28) into (14) and considering boundary condition, we got


Its minimum value, which determines the threshold voltage at a lowvds, is given by:


where λ=toxeffR2εsiεox+14R2 is the natural length of SNWT by assuming the highest leakage path lies at the center of the channel. Combiningϕs0with equation of boundary condition, we get a new surface potential solution in terms of inversion charge:


and a inversion charge solution can be obtained:


where α=1+2fSCE is the subthreshold slope (SS);

fSCE=1/[2cosh(L/2/λ)2]is the SCEs factor;

νth=vth0+Δvth,VOL+Δvth,SCEis the new threshold voltage;

Δνth,SCE=fSCE[2(νth,Longqdepvbi)vds]is the threshold voltage roll-off induced by the SCEs. A drain current expression can further be derived using (32):




Comparison with numerical simulation results shown in Figure 23(a) shows the correctness of the threshold voltage roll-off and DIBL described by the proposed SCEs model. Figure 23(b) shows that the transfer characteristics with subthreshold slope degradation as predicted in the proposed the short channel model. The strong inversion drain current is not affected by the SCEs, which is expected.

Figure 23.

a) the threshold voltage roll-off versus channel length and (b) transfer characteristics in the short channel model (From Yang J. IEEE TED, Vol. 55, No. 11, November 2008)

3.3.2. Modeling quantum-mechanical (QM) effects and other advanced physical effects

In highly scaled device, the QM confinement of the carrier in the thin silicon channel is significant. As in bulk MOSFETs, the large vertical electric field leads to a strong band bending and carrier confinement at the surface, known as EC as shown in Figure 24. The deviation of the location of peak carrier concentration from the surface decreases the channel carrier concentration and leads a decrease in the gate capacitance (Francis et al., 1992):


where meis the effective mass of the electron corresponding to the lowest electric sub-band, and Eavg=Cox(qdep+q¯in/3)/βεsi is the average surface field. Besides the EC, there is a strong carrier confinement in nanoscale SNWTs even at low electric fields in the channel. It is because the carriers are confined in a rectangular well formed by the gate insulator around, known as SC. In SC and EC, the conduction band split into several subbands as shown in Figure 24. Since the carriers stays at the subband with the lower energy first, the reduction of the amount of carriers can be modeled by the widening the effective band-gap (Arora, 1993) and replace vch in (32) by


The simulation results shown in Figure 23(b) illustrates the model can predicted the threshold voltage roll off and gate capacitance degradation induced by QME correctly.

The modeling of other advanced physical effects such as poly-depletion effects and mobility degradation of this work are imported from the BSIM5 approach. Velocity saturation, velocity overshoot and ballistic transport (source-end velocity limit) is handled in a unified way using the saturation charge concept:


where n and m are the only parameters. The effective inversion charge qineff at the source and drain ends are substituted into the final current expression (26) to calculate the device output current. A complete ballistic transport model is not considered in this work, as ballistic transport will not be significant until the channel length is scaled to less than 10nm (Duan et al., 2001). The dc characteristics for a small size SNWT predicted by the complete compact model is demonstrated in Figure 25.

Figure 24.

Energy-band diagrams showing the carrier confinement and the quantization of electronic energy levels in the small size channel due to electrical confinement and structural confinement (From IEEE TED, Vol. 55, No. 11, November 2008)

Figure 25.

a) Ids-Vgs and (b) Ids-Vds characteristics predicted by the complete compact model for a small size SNWT (From IEEE TED, Vol. 55, No. 11, November 2008)

3.4. Ge/Si core/shell nanowire MOSFETs modeling

As one promising molecular device, Ge/Si core/shell nanowire MOSFET has been intensively studied experimentally and theoretically (Xiang et al., 2006; Lu et al., 2005; Fan et al., 2008; Musin & Wang, 2005; Liang et al., 2007; He, Y. et al., 2008) in recent years. Such a device utilizes the bandstructure engineering (Xiang et al., 2006), strain effect (He, Y. et al., 2008) and ballistic transport of 1-dimensional (1D) hole gas (Liang et al., 2007), resulting in very high carrier mobility and excellent performance. At the same time, an analytic compact model is also highly desirable for both physical insight into and performance evaluation of the core/shell based NWFET devices. However, it has not been available so far due to the complexity in analytically modeling the corresponding heterostructure, strain effect and ballistic transport. Nevertheless, some theoretical progresses on non-classical MOSFETs have provided the base for us to develop a primary analytical electrostatic potential model.

Here, starting from Poisson-Boltzmann equation in the Ge/Si core/shell NWFETs, the classical analytic expressions of electrostatic potential and charges in the semiconductor layers are derived out under the gradual channel approximation.

The schematic diagram and corresponding coordinate of a long channel Ge/Si core/shell NWFET are shown in Figure 26, where z is the channel direction, ris the radial direction, toxis the thickness of gate dielectric, r0and Rare the radii of germanium core and silicon shell, respectively.

Figure 26.

Shematic diagrame of a Ge/Si core/shell NWFET

The assumed condition in the model derivation include: an abrupt heterojunction between germanium and silicon, an intrinsic or lightly doped body and a long device channel. Quantum confinement and strain effect are neglected for simplicity. Under gradual channel approximation (GCA), the Poisson-Boltzmann equations in Ge/Si core/shell NWFETs are written as the following forms with only hole term considered:


whereϕ is the electrostatic potential, Vbiis the self-built voltage of intrinsic Ge/Si heterojunction, Vchis hole quasi-Fermi potential, qis the electronic charge, Vtis the thermal potential, niGe(nisi)and εGe(εsi)are the intrinsic carrier concentration and permittivity of germanium (silicon), respectively. The Ge/Si core/shell NWFET behaves like a depletion p-channel device due to the band offset between intrinsic germanium and silicon. Hole accumulation in both germanium core and silicon shell are handled while electron is neglected. Also notice that Vch is assumed to be constant along the radius according to quasi-equilibrium approximation, being a negative value for p type device.

For simplicity, a normalized formulation of (41) is used to find its solution in the shell region, the detailed process is showed in (Zhang L. et al., 2008). (41) in the silicon shell layer is solved concisely as:


where βsi and A are two intermediary parameters to be decided by the boundary condition, Lsiis the Debye length of intrinsic siliconLsi=εsiVt/(qnisi).

And then the radial electric field in the silicon shell layer is obtained:


Similarly, electrostatic potential and electric field in the germanium core layer are given at A=2:




whereLGe is the Debye length of intrinsic germaniumLGe=εGeVt/(qniGe). Also the intermediary parameter βGe is evaluated from the boundary condition.

At the interface between silicon and gate oxide layer, surface potential and electric filed are obtained according to the above equation:


Following Gauss’s Law and electric flux continuity condition, we get the final input voltage equation:

Vch(VgsΔϕ)Vt=εsiεoxln(1+toxR)[(A2)+2Aβsi(R/r0)A1βsi(R/r0)A]++ln(2A2Lsi2R2) +ln[βsi(Rr0)A]2ln[1βsi(Rr0)A]E50

Similar to the existing compact models for bulk and other non-planar MOSFET, the input voltage equation and its solution is the base for further developing drain current models and advanced effect models. The detailed solving procedure for (48) is described as follows.

At the interface between germanium core layer and silicon shell layer both the potential and electric flux need to be continuous. So the parametersA, βsiandβGeare arrived.

For the studied Ge/Si core/shell structure, it is verified that Ais always larger than 2 with gate voltage increasing for the Ge/Si core/shell structure. On the other hand, A has an upper limit set which is independent of the bias condition (Figure 27). And the three intermediary parameters are obtained simultaneously by the shooting secant method. After that, interface potential ϕr0 and centric potentialϕ0are obtained directly by substituting r=r0 and r=0into (44), respectively:


Hole charge density in germanium core and silicon shell layers are directly obtained through Gauss’s law:



The total hole charge density in the channel is also obtained as:


Note that Qmsirepresents the charge density per unit area at the interface between the silicon shell and oxide layer while QmGe denotes that at the interface between the germanium core layer and silicon shell layer. As a result, gate capacitance of the core/shell structure is obtained by differentiating gate charge Qg with respect to the gate voltage as follows:


where dϕs/dA and dVgs/dA are obtained from (46) and (48), respectively.

Figure 27.

The parameter A versus Vgsfor different Ge/Si core/shell structures (Zhang L. IEEE TED, Vol. 55, No. 11, Nov. 2008)

In summary, the analytical electrostatic potential equation and its solution are presented above. In this section the analytic potential model is verified through numerical simulation. The physical parameters of silicon and germanium in both the analytical model and numerical simulator are taken from (Sze, 1981). The spatial potential, electric field and hole charge density are obtained under classical device physics through intermediary parameterA,βsi and βGe for the given gate voltage, quasi-Fermi potential and structure parameters. So once the three intermediary parameters are solved for the given bias and device geometry, the characteristics of the Ge/Si core/shell structure are directly obtained form the analytic model prediction. The potential, electric field and charge density solution are illustrated in Figure 28-32 for one geometry configuration:R=10nm,r0=5nm , and tox=2nmin comparison with numerical simulation results. The results show that excellent agreements are observed between the analytic model and the numerical simulation in all these figures and the Ge/Si core/shell heterostucture NWFET exhibits its unique characteristics, much different from a common SRG MOSFET. A more detailed discussion is displayed in (Zhang L. et al., 2008).

Figure 28.

Potential distribution along the radial of a Ge/Si core/shell structure. The lines denote results obtained from the analytic model and the symbols are results from numerical simulation (Zhang L. IEEE TED, Vol. 55, No. 11, Nov. 2008)

Figure 29.

Formula: Eqn188.wmf>,ϕsand ϕr0of a Ge/Si core/shell structure as functions of ϕ0obtained form the analytic model (curves) in comparison with numerical simulation (symbols) (Zhang L. IEEE TED, Vol. 55, No. 11, Nov. 2008)

Figure 30.

Electric field and hole density distributions along the radial of a Ge/Si core/shell structure atVgs, obtained from the analytic model (lines) in comparison with numerical simulation (symbols) (Zhang L. IEEE TED, Vol. 55, No. 11, Nov. 2008)

Figure 31.

Charge densityVgs=1V,QmGe and Qmsiof a Ge/Si core/shell structure as functions ofQg both in linear and logarithm coordinates, obtained from the analytic model (lines) in comparison with numerical simulation (symbols). (Zhang L. IEEE TED, Vol. 55, No. 11, Nov. 2008)

Figure 32.

Normalized gate capacitance Vgs curves as a function of Cgg/Cox from the analytic model (solid lines) in comparison with numerical simulation (symbols). Dotted lines denote three correspondingVgs (Zhang L. IEEE TED, Vol. 55, No. 11, Nov. 2008)


4. Nanowire–based circuit simulation

Paralleling the advance of process technology to fabricate SNWT (Cui et al., 2001c; Duan et al., 2001), compact models for the SNWTs have also been developed for circuit simulations in recent years. A general model for doped SNWTs may be very useful for device scientists to optimize the device structure and for circuit designers to evaluate the performance of the SNWT circuits. Here, a design oriented compact model for SNWTs, applicable for a wide range of doping concentrations (i.e. from 1010 to 1019cm-3) and geometrical dimensions is presented. Starting from Poisson’s equation solution, an accurate inversion charge (Qin) equation is obtained for the long channel SNWTs with arbitrary doped bodies. Then a charge based drain current (Ids) expressions is derived. Transconductance (gm), output conductance (gds), terminal charges (Q) and capacitance (Cij) are all derived analytically and verified by TCAD simulation (Synopsys, 2005). And then this model is also implemented in the circuit simulator by the Verilog-A language and its application in circuit simulations is also demonstrated.

Figure 33.

a) Stereoscopic schematic, (b) cross-section schematic, and (c) energy band diagram of an N-type SNWT (From Yang J., IEEE TED, Vol. 55, No. 11, Nov. 2008)

The device structure, coordinate system, and corresponding energy band diagram of a doped SNWT studied in this work are shown in Figure 33 (a), (b) and (c), respectively. For an n-type device, the hole Fermi level Efp remains constant along the channel if the current of majority carriers is neglected. Consequently, Efp can be defined as the energy reference level in this work. The 3D Poisson-Boltzmann equation in the SNWT structure is written as


where 1rddr(rdϕdr)+d2ϕdy2=1LD2[1+eϕvch2ϕf] is the Fermi-potential, ϕf=ln(Na/ni)is the quasi-Fermi potential, vchis the channel potential, and ϕ is the Debye’s length of the silicon body with dopingLD2=kTεsi/q2Na. All other variables have there usual meanings. All the potentials in this work are normalized by thermal voltageNa, and the charges byβ, unless otherwise specified. β/Coxis the effective oxide capacitance.

This 3D problem is simplified into two separate parts along the vertical and current flow directions. And we get the relationship:


where vgsvth0Δvth,VOLvch=qin+lnqin+ln(1+Hqin) is the transistor threshold voltage similarly to bulk MOSFET; νth0=Δϕ+2ϕf+qdepln4εsiRCoxqdepis the extra part of threshold voltage induced by the special geometric structure of SNWT and Δvth,VOL=ln12qdep[1exp(CoxR2εsiqdep)] is given as the total mobile charge sheet density in the channel.

Figure 34.

a) Vth model is compared with TCAD extracted by second derivative method in a long channel SNWT (From Yang J., IEEE TED, Vol. 55, No. 11, Nov. 2008)

Through the above equation, the validity of the threshold voltage modeling is verified, see Figure 34, and the characteristics of inversion charge with different condition are got and shown in Figure 35.

Figure 35.

Inversion charge equation verification for long channel SNWTs (a) with doping variation, (b) with geometric size variation in doped case and (c) with geometric size variation in undoped case (From Yang J., IEEE TED, Vol. 55, No. 11, Nov. 2008)

The analytical drain current expression is obtained as:


where Ids=2πRμeffCoxβ2Leff[f(qd)f(qs)] is the effective mobility in the channel; μeffis the quasi-Fermi potential in the drain terminals; Vdsand qd are normalized inversion charge per unit gate area at the source and drain terminals with qs

Transconductance and output conductance can be derived analytically from the expressions of drain current:


Analytical expressions for inversion charges at each terminal are desired for efficient transient circuit simulation. For a SNWT, there are three terminal charges, associating with gate, source, and drain, respectively: the gate charge Qg can be computed by integrating the channel charge density along the channel; The drain and source charges, denoted as Qd and Qs, can be derived analytically by using the Ward-Dutton linear-charge-partition method:


where Qs=QgQd are obtained from the current continuity condition


The model predicted I-V characteristics are verified by comparing with TCAD simulation under various biasing voltages, a wide range of doping concentrations and geometric dimensions as shown in Figure 36. The error between the proposed model and the 3-D numerical simulation is less than 5% with devices with intrinsic to heavily doped body with a doping of 1019 cm-3. The numerical simulation results demonstrate the accuracy of the proposed model from the linear to saturation and from the sub-threshold to strong inversion regions.

In contrast to digital circuits, analog design focus on the first derivatives such as gm/Ids and Cij, which are shown in Figure 37. At Vds=0, Cgs=Cgd and Csg=Cdg in the figures indicate that the developed model has inherent the source/drain symmetry characteristic, which is important for analog and RF applications. Note that the verifications of the core I-V and C-V models are done without any fitting parameters.

The compact SNWT model has been implemented in a commercial circuit simulator ADS2006A by the Verilog-A language to demonstrate practicality of the model. This implementation includes a procedure to produce an initial guess and convergent correction methods to help the nonlinear equation (32) to calculate the inversion charge. DC, ac, and transient simulations of many sample circuits are performed. Figure 38 shows the transient analysis of a 21-stage SNWT ring oscillator by this model. The waveforms of three successive stages are plotted in the figure. Compared with a ring oscillator constructed by DG MOSFETs (Taur et al., 2004), the oscillator frequency in this work is much higher, illustrating a smaller transistor input capacitances relative to the higher current drive in SNWT device. In the case of high parasitic capacitance, parallel connection of several SNWTs can be used.

Figure 36.

dc I-V characteristics verification for long channel SNWTs (a) Ids-Vds (b) Ids-Vgs with doping variation (Symbols: TCAD, Lines: Model) and (c) Ids-Vgs with geometric size variation. (From Yang J., IEEE TED, Vol. 55, No. 11, Nov. 2008)

Figure 37.

ac characteristics verification of the model for a long channel SNWT (a) gm-efficiency, (b) C-Vds, (c) C-Vgs (at Vds≠0) and (d) C-Vgs (at Vds=0) (From Yang J., IEEE TED, Vol. 55, No. 11, Nov. 2008)

Figure 38.

a) Circuit schematic of a 21-stage SNWT ring oscillator, and (b) the waveforms of three successive outputs in a transient analysis by ADS2006A (From Yang J., IEEE TED, Vol. 55, No. 11, Nov. 2008)


5. Conclusion

In this chapter, after a brief outline of the silicon-based nanowire fabrication technology, we discussed simulation and compact model of nanowire MOSFET following the device physics understanding and exploring. In the developed compact model, the short channel effect, quantum mechanic effect and other are analyzed and the predicted results are also compared with the 3-D numerical simulation. Based on such a verified physics based SPICE model, the nanowire based circuit performance is simulated and demonstrated.



This work is supported by the Fundamental Research Project of Shenzhen Science & Technology Foundation (JC200903160353A), the Shenzhen Science & Technology Foundation (CXB201005250031A), and the Industry, Education and Academy Cooperation Program of Guangdong (2009B090300318).


  1. 1. Arora, N., MOSFET models for VLSI circuit simulation: theory and practice, Springer-Verlag New York Inc., ISBN 0387823956, Secaucus, NJ, USA
  2. 2. BarreletC. J.GreytakA. N.LieberC. M. 2004 Nanowire Photonic Circuits Elements, Nano Letters, 4 10 (September, 2004), 19811985 , 0000-00101021
  3. 3. BeraL. K.NguyenH. S.SinghN.LiowT. Y.HuangD. X.HoeK. M.TungC. H.FangW. W.RustagiS. C.JiangY.LoG. Q.BalasubramanianN.KwongD. L.ThreeDimensionally.StackedSi.GeNanowire.ArrayGate-All-Around-Mp.TsO. S. F. E.InternationalI. E. E. E.ElectronDevices.Meeting 2006 551554 , 1-4244-0438-X San Francisco, CA, USA, Dec 11-13, 2006
  4. 4. BlackC. T. 2005 Self-aligned self assembly of multi-nanowire silicon field effect transistors, Appl. Phys. Lett. 87 16 (October 2005), 163116163118 , 0003-6951
  5. 5. BianW.HeJ.TaoY.FangM.FengJ. 2007 An analytic potential-based model for undoped nanoscale surrounding-gate MOSFETs, IEEE Transactions on Electron Devices, 54 9 (Sept. 2007), 22932303 , 0018-9383
  6. 6. ChangC.WangY. F.KanamoriY.ShihJ. J.KawaiY.LeeC. K.WuK. C.EsashiM. 2005 Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures, J. Micromech. Microeng., 15 3 ( March 2005), 580585 , 0960-1317
  7. 7. CuiY.LieberC. M. 2001 Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks, Science, 291 5505 (February 2001), 851853 , 1095-9203
  8. 8. CuiY.LauhonL.GudiksenM.WangJ.LieberC. 2001 Diameter-controlled synthesis of single-crystal silicon nanowires, Applied Physics Letters, 78 15 (APRIL 2001), 22142216 , 1077-3118
  9. 9. CuiY.WeiQ.ParkH.LieberC. M. 2001 Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species, Science, 293 5533 (August 2001), 12891292 , 1095-9203
  10. 10. DuanX.HuangY.CuiY.WangJ.LieberC. M. 2001 Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices, Nature, 409 (January 2001), 6669 , 0028-0836
  11. 11. Dupre, C., et. al. 15nm-diameter 3D Stacked Nanowires with Independent Gates Operation: ΦFET, IEEE International Electron Devices Meeting, 2008 749752 , 978-1-42442-377-4 San Francisco, CA, USA, Dec15-17, 2008
  12. 12. FangW. W.SinghN.BeraL. K.NguyenH. S.RustagiS. C.LoG. Q.BalasubramanianN.KwongD. L. 2007 “Vertically stacked SiGe nanowire array channel CMOS transistors”, IEEE Electron Device Letters, 28 3 (March 2007), 211213 , 0741-3106
  13. 13. FanZ.HoJ. C.JacobsonZ. A.RazaviH.JaveyA. 2008 Large-scale, heterogeneous integration of nanowire arrays for image sensor circuitry, Proc. Nat. Acad. Sci., 105 32 (Aug., 2008), 1106611070 , 110661-1070
  14. 14. FerryD.GilbertM.AkisR. 2008 Some considerations on nanowires in nanoelectronics, IEEE Transactions on Electron Devices, 55 11 (Nov. 2008), 28202826 , 0018-9383
  15. 15. FrancisP.TeraoA.FlandreD.Van de WieleF. 1992 Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold, Microelectronic Engineering, 19 1-4 , (August 2002), 815818 , 0167-9317(92)90551-2
  16. 16. He, J., & Chan, M., physics based analytical solution to undoped cylindrical surrounding-gate (SRG) MOSFETs. 15 IEEE Int. Conf. on Devices, Circuits and Systems, 2628 , 0-78038-777-5 Republic, Nov.3-5, 2004
  17. 17. HeJ.ZhangX.ZhangG.ChanM.WangY. 2006 A carrier-based DCIV model for long channel undoped cylindrical surrounding-gate MOSFETs, Solid-State Electronics, 50 3 (March, 2006), 416421 , 0038-1101
  18. 18. HeJ.ZhangX.ZhangG.ChanM.WangY.completeA.carrier-basednon-charge-sheet.analytictheory.fornano-scale.undopedsurrounding-gate. M. O. S. F. E.Ts Proceedings of ISQED’2006, 115120 , 0-76952-523-7 Jose, Costa Rica, Mar. 28 2006 2006
  19. 19. HeJ.BianW.TaoY.YangS.TangX. 2007 Analytic carrier-based charge and capacitance model for long-channel undoped surrounding-gate MOSFETs, IEEE Transactions on Electron Devices, 54 6 (June 2007), 14781485 , 0018-9383
  20. 20. HeY.FanC.ZhaoY.DuG.LiuX.HanR.Impactof.inhomogeneousstrain.onthe.valenceband.structureof.Ge-Sicore-shell.nanowiresProc. Int. Conf. on Simulation of Semiconductor Process and Devices, 121124 121124 978-1-42441-753-7 Hakone, Sept. 9-11, 2008
  21. 21. HoodL.HeathJ. R.PhelpsM. E.LinB. 2004 Systems Biology and New Technologies Enable Predictive and Preventative Medicine, Science, 306 5696 (October 2004), 640643 , 1095-9203
  22. 22. IñíguezB.JiménezD.RiogJ.HamidH. A.MarsalL. F.PallarèsJ. 2005 Explicit continuous model for long channel undoped surrounding-gate MOSFETs, IEEE Trans on Electron Devices, 52 8 (Aug. 2005), 18681873 , 0018-9383
  23. 23. JiménezD.SáenzJ. J.IñíguezB.SuñéJ.MarsalL. F.PallarèsJ. 2004 Continuous analytical current-voltage model for surrounding-gate MOSFETs, IEEE Electron Device Letters, 25 8 (Aug. 2004), 571573 , 0741-3106
  24. 24. JinS.FischettiM.TangT. 2007 Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity, Journal of Applied Physics, 102 8 (October 2007), 083715083728 , 0021-8979
  25. 25. KedzierskiJ.BokorJ.KisielowskiC. 1997 Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation, J. Vac. Sci. Technol. B, 15 6 (July 1997), 28252828 , 0073-4211X
  26. 26. KotlyarR.ObradovicB.MatagneP.StettlerM.GilesM. 2004 Assessment of room-temperature phonon-limited mobility in gated silicon nanowires, Applied Physics Letters, 84 25 (June 2004), 52705272 , 0003-6951
  27. 27. LiangG.XiangJ.KharcheN.KlimeckG.LieberC. M.LundstromM. 2007 Performance Analysis of a Ge/Si Core/Shell Nanowire Field-Effect Transistor, Nano Letter, 7 3 (January, 2007), 642646
  28. 28. LiowT.TanK.LeeR.ZhuM.TanB.SamudraG.BalasubramanianN.YeoY. 2008 "5 nm gate length Nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free Melt-Enhanced Dopant (MeltED) diffusion and activation technique," Symposium on VLSI Technology, 3637 , 978-1-42441-802-2 Honolulu, HI, June 17-19, 2008
  29. 29. LiuH.BiegelsenD. K.JohnsonN. M.PonceF. A.PeaceR. F. W. 1993 Self-limiting oxidation of Si nanowires, J. Vac. Sci. Technol. B, 11 6 (Nov 1993), 25322537 , 1071-1023
  30. 30. LiuH.BiegelsenD. K.PonceF. A.JohnsonN. M.PeaceR. F. W. 1994 Self-limiting oxidation for fabricating sub-5nm silicon nanowires, Applied Physics Letters, 64 11 (Mar 1994), 13831385 , 0003-6951
  31. 31. LuW.XiangJ.TimkoB. P.WuY.LieberC. M. 2005 One-dimensional hole gas in germanium/silicon nanowire heterostructures, Proc. Nat. Acad. Sci., 102 29 (July, 2005), 1004610051 , 100461-0051
  32. 32. LuW.LieberC. 2006 Semiconductor nanowires, Journal of Physics D: Applied Physics, 39 21 (June, 2006), R387 0022-3727
  33. 33. MichettiP.MugnainiG.IannacconeG. 2009 Analytical model of nanowire FETs in a partially ballistic or dissipative transport regime, IEEE Transactions on Electron Devices, 56 7 (July 2009), 14021410 , 0018-9383
  34. 34. MoldovanO.IñíguezB.JiménezD.RiogJ. 2007 Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs, IEEE Trans on Electron Devices, 54 1 (January, 2007), 162165 , 0018-9383
  35. 35. MusinR. N.WangX. Q. 2005 Structural and electronic properties of epitaxial core-shell nanowire heterostructures, Physics Review B, 71 15 (April 2005), 1553815541 , 1098-0121
  36. 36. MoralesA.LieberC.laserA.ablationmethod.forthe.synthesisof.crystallinesemiconductor.nanowires 1998 Science, 279 208 (JANUARY 1998), 208211 , 1095-9203
  37. 37. NamatsuH.HoriguchiS.NagaseM.KuriharaK. 1997 ”Fabrication of one-dimensional nanowires structures utilizing crystallographic orientation in silicon and their conductance characteristics”, J. Vac. Sci. Technol. B, 15 5 (July 1997), 16881696 , 0073-4211X
  38. 38. NeophytouN.PaulA.LundstromM.KlimeckG. 2008 Bandstructure effects in silicon nanowire electron transport, IEEE Transactions on Electron Devices, 55 6 (June 2008), 12861297 , 0018-9383
  39. 39. NgR. M. Y.WangT.LiuF.ZuoX.HeJ.ChanM. 2009 Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress Limited Oxidation, IEEE Electron Device Letters, 30 5 (May 2009), 520522 , 0741-3106
  40. 40. NgR. M. Y.WangT.ChanM.NewA.Approachto.FabricateVertically.Stacked-CrystallineSingle.SiliconNanowires.Proceedings 2007 2007 IEEE EDSSC, 133136 , 978-1-42440-637-1 Tainan, Taiwan, China, December 20-22, 2007
  41. 41. PaoH. C.SahC. T. 1966 Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors, Solid-State Electronics, 9 10 (September 2002), 927937 , 0038-1101(66)90068-2
  42. 42. RamanathanK.BangarM. A.YunM.ChenW.MyungN. V.MulchandaniA. 2005 Bioaffinity Sensing Using Biologically Functionalized Conducting Polymer Nanowire, J. AM. CHEM. SOC., 127 2 (December, 2004), 496497 , 0000-00101021
  43. 43. SinghN.BuddharajuK. D.ManhasS. K.AgarwalA.RustagiS. C.LoG. Q.BalasubramanianN.KwongD. L. 2008 2008), Si, SiGe Nanowire Devices by Top-Down Technology and Their Applications, IEEE TRANSACTIONS ON ELECTRON DEVICES, 55 11 (July, 2008), 31073118 , 0018-9383
  44. 44. SternE.VacicA.ReedM. 2008 Semiconducting nanowire field-effect transistor biomolecular sensors, IEEE Transactions on Electron Devices, 55 11 (Nov. 2008), 31193130 , 0018-9383
  45. 45. Synopsys, TCAD Sentaurus Device User’s Manual, Mountain View, 2005 2005
  46. 46. SzeS. M.Physicsof.SemiconductorDevices. 2 ed. Wiley, 978-0-47114-323-9 New York, USA
  47. 47. TaurY.LiangX.WangW.LuH. 2004 A continuous, analytic drain-current model for DG MOSFETs, IEEE Electron Device Letter, 25 2 (Feb. 2004), 107109 , 0741-3106
  48. 48. XiangJ.LuW.HuY.YanH.LieberC. M. 2006 Ge/Si nanowire heterostructures as high performance field-effect transistors, Nature, 441 25 (May 2006), 489493 , 0028-0836
  49. 49. YangJ.HeJ.LiuF.ZhangL.ZhangX.ChanM. 2008 A compact model of silicon-based nanowire MOSFETs for circuit simulation and design, IEEE Transactions on Electron Devices, 55 11 (Nov. 2008), 28982906 , 0018-9383
  50. 50. YuB.WangL.YuanY.AsbeckP.TaurY. 2008 Scaling of nanowire transistors, IEEE Transactions on Electron Devices, 55 11 (Nov. 2008), 28462858 , 0018-9383
  51. 51. ZhangL.HeJ.ZhangJ.LiuF.FuY.SongY.ZhangX. 2008 An Analytic Model for Nanowire MOSFETs With Ge/Si Core/Shell Structure," IEEE Transactions on Electron Devices, 55 11 (Nov. 2008), 29072917 , 0018-9383
  52. 52. ZhangL.ZhangJ.LiuF.ChenL.XuY.ZhouW.HeF.Ananalytic.channelpotential.basedmodel.fordynamic.depletionsurrounding-gate.mosfetswith.arbitrarydoping.level 1 Asia Symposium on Quality Electronic Design, ASQED 2009, 131135 , 978-1-42444-952-1 Kuala Lumpur, Malaysia, 15-16 July 2009
  53. 53. ZhangL.GuanY.ZhouW.ChenL.XuY.HeJ. 2009 A carrier-based analytic drain current model incorporating velocity saturation for undoped surrounding-gate MOSFETs, Semiconductor Science and Technology, 24 11 (Oct. 2009), 115003115010 , 0268-1242
  54. 54. ZhangY. F.TangY. H.WangN.YuD. P.LeeC. S.BelloI.LeeS. T. 1998 Silicon nanowires prepared by laser ablation at high temperature, Applied Physics Letters, 72 15 (Apr 1998), 18351837 , 0003-6951
  55. 55. Wang, J., “Device Physics and Simulation of Silicon Nanowire Transistors”, PhD thesis, Purdue University, 2005

Written By

Jin He, Haijun Lou, Lining Zhang and Mansun Chan

Submitted: 28 January 2011 Published: 18 July 2011