The Analogue/Digital Converters (ADCs) play a very important role in several wideband applications like wired and wireless high speed telecommunication systems (e.g., 802.11g) or communication over powerlines (IEEE P.1901). High definition TV or high precision real time image processing are also examples of applications that require a conversion rate of several hundreds MSamples/sec or even multi-GSsamples/sec.
While the ADCs may operate in an optimal way when they are initially designed and verified using DC simulation, a transient simulation can designate several problems that appear during the high speed operation. Additional linearity errors are posed by process variations and component mismatches after the chip fabrication. Finally, operating conditions like voltage supply levels and temperature variations can also affect the linearity of an ADC. Several foreground and background calibration techniques have been proposed in the literature. Most of them are developed for specific ADCs and cannot be applied to different ADC architectures.
The most important error sources and the most popular calibration methods for Pipelined, Segmentation/Reassembly and Sigma Delta ADCs as well as a number of generic error compensation methods based on the processing of the ADC output are presented in (Balestrieri et al, 2005). A popular error correction technique used in pipelined ADCs exploits the least significant bit of a “coarse” ADC stage for the error detection and correction. For example, in (Colleran & Abidi, 1993) a 10-bit ADC is constructed by a 4-bit “coarse” and a 7-bit “fine” ADC. The least significant bit of the coarse ADC should match the most significant bit of the fine ADC. Similarly, a 10-bit pipeline ADC consists of a coarse 6-bit and a fine 5-bit ADC in (Sone et al, 1993). Two more recent approaches that are described in (Kurose et al, 2006) and in (Ahmed & Johns, 2005)(Ahmed & Johns, 2008) use 8 stages of 1.5-bit and a 2-bit Flash ADC stage in a 10-bit (or 11-bit in (Ahmed & Johns, 2008)) pipelined ADC architecture. Moreover, in (Ahmed & Johns, 2008), the DAC linearity errors are also taken into consideration. The use of a redundant signed digit also appears at an Analogue-to-Quaternary pipelined converter in (Chan et al, 2006).
The ADC architectures that are based on high precision capacitors suffer from the effects of the mismatch. In (Wit et al, 1993), an additional array of capacitors is used for real time trimming that is performed by an algorithm implemented on-chip in order to handle component ageing. Trimming arrays are also used in (Ohara et al, 1987). A digital calibration of the capacitor mismatch, the comparator offsets and the charge injection offsets in a pipelined ADC is performed in (Karanicolas et al, 1993) for the improvement of DNL errors.
The biasing of the operational amplifiers used in a pipelined ADC according to the power supply, the temperature and the sampling speed is determined by calibration in (Iizuka et al, 2006). The offset of the residue amplifiers is calibrated in the background in (Ploeg et al, 2005) (Van De Vel, 2009). Background calibration is also performed in (McNeill et al, 2005) where two identical algorithmic ADCs operate in parallel, their output is averaged and any difference in their results steers the calibration procedure. In (Wang et al, 2009), a nested digital calibration method is described for a pipeline ADC that does not require an input Sample/Hold Amplifier. A digital background calibration technique is proposed in (Hung & Lee, 2009) to correct gain errors in pipelined ADCs. This calibration technique performs the error estimation and the adaptive error correction based on the concept of split ADCs. In (Sun et al, 2008), a technique called Commutated Feedback Capacitor Switching is used to extract information about the mismatches of the capacitors used and then this information is exploited by a digital background calibration method.
Post processing techniques offer a different approach to the linearity error reduction of the ADCs. While all the aforementioned techniques target to the correction of the error sources, the post processing methods operate on the ADC output. The Differential or Integral Non-Linearity (DNL/INL) errors can be measured in order to estimate correction factors for each output code. These correction factors are stored in large lookup tables and are added to or subtracted from the corresponding output codes at real time. These lookup tables are also subject to real time calibration as described in (De Vito et al, 2007). The estimation of the correction factors can be performed in the simplest case by applying successive DC levels at the ADC input and measuring the DNL of the generated ADC output codes (Provost & Sanchez-Sinencio, 2004). More sophisticated techniques apply a sinusoidal signal to the ADC input and construct a Histogram using the resulting ADC output in order to estimate the DNL errors and consequently the correction factors (Correa-Alegria & Cruz-Sera, 2009).
In this chapter, some representative calibration approaches presented in the literature are described emphasising on the more general ones in the sense that they can be applied to different ADC architectures. Moreover, the calibration schemes proposed by the authors in a current mode implementation of a 12-bit ADC with a novel binary tree structure (Petrellis et al, 2010a) as well as in a voltage mode subrange ADC (Petrellis et al, 2010b, 2010c) are also presented since they can also be used in different target applications.
2. Resistor and capacitor trimming
The highest speed ADCs are based on the Flash or Parallel architecture where the input signal is concurrently compared to
A significant linearity error source in these ADCs is the component mismatches in the resistor ladders. If the tolerance in these resistors is expressed as ±
High precision capacitors are used in several ADC architectures that are based on charge redistribution, integrators, Sigma-Delta ADCs etc (Quiquempoix et al, 2006). Capacitor trimming can be performed in a similar way to the resistors whenever high precision capacitors have to be used (Wit et al, 1993). A simple way to perform such a capacitor trimming is shown in Fig. 1b. If the tolerance of a capacitor C is ±
3. Redundant bits in pipeline ADCs
Pipeline, Subfolder and Subrange ADCs can achieve a descent resolution higher than 8-bit with a conversion speed that is comparable to that of the Flash ADCs. This is achieved by using a number of Flash ADC stages with lower resolution. For example in a two stage Pipeline ADC with
4. Bias adjustment
The biasing of the operational and differential amplifiers used in several ADC architectures like pipeline or Sigma Delta ADCs often requires an accurate real time calibration around a typical value. An ordinary DAC cannot offer a high resolution adjustment since its dynamic range spans from 0 volts to its maximum range and is not focused around the typical bias
value that is required. For example, if an accurate adjustment has to be performed around 500mV in a range of ±16mV in steps of 1mV, then an ordinary 10-bit DAC would be required with reference voltage of 1024mV. Such an ADC is capable of providing any of the voltages between 0 and 1023mV in steps of 1mV, but most of these output levels would be unused in the specific bias requirement.
A much lower area/power 5-bit DAC would be sufficient if it could provide an offset of 484mV and a dynamic range of 32mV above the 484mV level. This can be achieved e.g., with a weighted current source DAC with offset like the one presented in (Petrellis et al, 2010a). An example of such a 3-bit DAC is shown in Fig. 3. The output current range of such a DAC is
5. Averaging the output of a pair of identical ADCs
Another method for the detection and the correction of errors at an ADC output is based on the generation of a duplicated output by a pair of identical ADCs (McNeil et al, 2005). For example, if two ADCs accept the same input they should generate the same digital output. Nevertheless, their outputs may differ slightly due to component mismatches and process variations. The averaging of these outputs can lead to an error reduction. Assuming that the ADC digital outputs are
The main drawback of this approach is the required die area and power duplication. A difference in the ADC outputs may trigger a more sophisticated calibration algorithm that corrects the error at its source instead of simply using the average of these outputs.
6. Lookup tables with DNL error correction factors
Another error correction technique that is based on the processing of the ADC output, estimates the DNL error of each output code and a corresponding correction factor. All of these correction factors are stored in a lookup table and are accessed at real time in order to determine how the current output code should be altered to improve linearity.
The DNL error is defined using the ADC transfer function shown in Fig. 4. In the ideal case, any output code should have the same width as the Least Significant Bit (LSB):
The parameter Vref is the maximum input voltage of the ADC and
The lookup tables with the correction factors may also require real time calibration as described in (De Vito et al, 2007).
7. Current mode circuit calibration
In current mode implementations of ADCs, the current mirrors play a very important role. For example, in current mode Flash ADCs, the input current is compared to a number of current levels that are generated from a single reference level using appropriately scaled mirrors. The input (
Nevertheless, this scaling is not as accurate as indicated by equation (7) due to component mismatches, while it is also affected by temperature. Cascode current mirrors offer a higher accuracy and temperature stability than simple current mirrors due to higher output resistance but their usage leads to slower implementations.
In (Petrellis et al, 2010a) two versions of an ADC that is based on a current mode integer division are presented. Higher speed can be achieved by using simple current mirrors instead of cascode ones for the generation of reference currents and the implementation of operations like subtraction and multiplication/division by a constant. Since simple current mirrors are faster but more sensitive to component mismatches and temperature variations than cascode ones, replacing some critical simple current mirrors with gain-boosted ones in such an ADC can reassure its correct operation without sacrificing speed. The biasing of these gain-boosted mirrors is controlled by an appropriate calibration algorithm.
The novel ADC architecture presented in (Petrellis et al, 2010a) is based on the integer division of an input current
The current mode integer division can be implemented by the circuit shown in Fig. 5. If the relation (8) holds, then
A novel ADC architecture based on integer division was presented in (Petrellis et al, 2010a) and is shown in Fig. 6. A binary tree structure is used and each node of the tree implements an integer division by a number of the form:, where
Simple current mirrors with small transistors can be used to implement time critical operations of the ADC architecture that is shown in Fig. 6. At such critical nodes like the ones at the root of the binary tree of Fig. 6, gain-boosted current mirrors can be used like (M5, M6, IC0) and (M7, M8, IC1) that are shown in Fig. 7.
The gain-boosted current mirrors can also be used in different ADC architectures like current mode pipeline ADCs. The adjustment of the subtraction outcome between the DAC output of a pipeline stage from its input in order to generate the residue can be carried out by a gain boosted current mirror arrangement like the one presented in Fig. 7.
8. Non-monotonic error elimination
Non-monotonic errors are a significant issue at several architectures but fortunately in most cases they do not appear at random transitions. For example, in two-stage pipeline ADCs such monotonic errors may appear during the transition of the residue signal between two peak values. For example, the sawtooth signal shown in Fig. 8 may represent two periods of a pipeline ADC residue. As can be seen in this figure the linearity of this residue is not very good since this signal does not start to rise immediately. Moreover, non-monotonic errors appear during the falling edge of each tooth since it does not fall immediately from its peak value to its minimum.
In ADCs like the ones presented in (Petrellis et al, 2010a) the severe non-monotonic errors appear whenever the bit No. 4 changes. Generally we assume that non-monotonic errors appear when the bit
A simple way to handle this kind of problem is to detect the changes in the bit No. 4 and keep the previous ADC output stable for an interval equal to the falling edge of the residue. Although, this technique does not lead to a linear solution, it eliminates most of the non-monotonic errors that are more important than the ones of the linearity. A simple analogue circuit capable of performing this non-monotonic error elimination is shown in Fig. 9.
When the input of each XOR gate in Fig. 9 rises from 0 to 1 the connected capacitor is charged almost immediately but when the input changes from 1 to 0, the capacitor is discharged through the resistor connected in parallel with the capacitor. During the time that it takes the capacitor to discharge the inputs of the corresponding XOR gate are different and its output is 1 generating a pulse with a duration that is determined by the
The BUSY signal duration cannot be determined very accurately in the way described above because it depends on the
9. Correction of differential signals in voltage mode ADCs
High speed conversion is achieved by ADCs that operate on differential signals. The differential amplifiers are faster because the stage that converts the differential signal to a single-ended one is omitted. Moreover, differential signals are more immune to noise interference.
In voltage mode ADCs like the one presented in (Petrellis et al, 2010b, 2010c), the differential amplifiers that are used to perform addition or subtraction are also sensitive to component mismatches that can lead to the drifting of the output differential signals, away from their predefined levels as well as the modification of their amplitude. The authors propose a calibration method that continuously observes such differential signals and shifts them appropriately to their correct positions. Auxiliary components like draft frequency detectors and digital to analogue converters that generate fine voltage levels around an offset, are also required in such ADC architectures and are described in this paragraph.
A monitoring circuit can be used to decide whether two differential signals overlap or not. For example, if Fig. 12 shows the optimal differential residue signals form, then a voltage comparator that accepts as input these differential signals can decide whether they overlap or not.
The circuit shown in Fig. 13a monitors two differential signals (
When the calibration starts, the counter of Fig. 13a is cleared, shifting away the signals
A higher resolution can be achieved at the output of the DAC in the range that we are interested in, if a DAC with offset is used like the one presented in paragraph 4. An undesirable phase difference in the signals
The undesirable phase shift of the signals
The comparator of Fig. 14 and the 2nd Counter are used to enumerate how many times a monitored differential signal like
The 2nd Counter output of the draft range detector of Fig. 14 can also control the bias of an ADC pipeline stage that accepts as input the signals
The use of the Differential Signal Monitor and the Delay Insertion/Level Shifting circuit of Fig. 13 as well as the draft Frequency Range Detector of Fig. 14 are demonstrated in Fig. 15. The differential sawtooth curves at the bottom of that figure represent the monitored residue signals (
10. Post processing techniques for linearity improvement
The use of the correcting factors stored in lookup tables that were presented in paragraph 6 is a type of post processing technique. The authors are currently developing different post processing techniques that are general enough to be used for the linearity improvement of several ADC architectures. These techniques are based on the fact that often the high DNL errors have a periodic form and appear at output codes with a specific format. For example, in a two stage pipeline ADC the residue that serves as input to the “fine” ADC stage may not consist of identical teeth in the sense that some teeth may have different amplitude or offset as shown in Fig. 16.
If the differential signals of Fig. 16 are input to a 4-bit “fine” Flash ADC, then the two resistor ladders that generate the voltage levels of each differential comparator at the input stage of this ADC have to be biased appropriately. Consider for example the differential signal at the top of Fig. 16. If the input range of this signal is assumed to be 680mV..880mV in order to cover the minimum/maximum peaks of all teeth, then some codes will be missing at the ADC output since some teeth do not span at the whole range (they have a lower than 200mV amplitude). In order to avoid missing codes, a smaller range can be assumed for this specific differential signal e.g., 700mV..840mV. A similar biasing approach may be chosen for the differential signal at the bottom of Fig. 16 to avoid missing codes. Nevertheless, in this case the codes of the binary form x0000 and x1111 will have a significantly higher DNL error than the others due to the teeth clipping. In fact, the DNL of these output codes will probably be higher than 1 LSB.
A post processing technique is under development by the authors that corrects such a high DNL error by detecting the erroneous codes at the ADC output and replacing them with successive codes of 1-bit higher resolution. The rest of the codes are simply shifted appropriately and their resolution is also extended by 1-bit. In order to decide the duration of the inserted codes an averaging of the ADC output code duration is continuously performed by a digital circuit. Simulation results show that the SNDR of the 8-bit ADC described in (Petrellis et al, 2010c) can be increased in this way by up to 6dB.
In a more general approach, the average duration of the ADC output codes can be continuously estimated, and a correction of the successive codes’ duration can be carried out. For example, if a code appears in average 5 consequent times while the codes X and X+1 appear 7 and 3 times respectively, then the last 2 appearances of X can be replaced with X+1.
The appropriate calibration techniques allow the ADCs to operate at the extremely high conversion rates required by the nowadays applications. Although many ADC architectures require customised solutions it was attempted to select and present the most popular and general ones. A number of calibration and post processing techniques that have been developed by the authors have also been presented. These techniques include current mode calibration based on the use of gain boosted mirrors as well as voltage mode calibration methods that perform differential signal monitoring, level shifting, delay insertion, frequency range detection and bias adjustment.
Part of this work has been supported by Analogies SA and is patent pending. (Application No. PCT/GB2009/051101).