Jose Nunez-Yanez

Jose Nunez-Yanez is a Reader in Adaptive and Energy efficient computing and a member of the Microelectronics group. He holds a Ph.D. in hardware-based parallel data compression from the University of Loughborough, UK, with three patents awarded on the topic of high-speed parallel data compression. His main area of expertise is in the design of reconfigurable architectures for signal processing with a focus on run-time adaptation, parallelism, and energy-efficiency. In 2006 he was a Marie Curie research fellow at ST Microelectronics, Milan, Italy working on the automatic design of hardware accelerators for video processing. In 2011 he was a Royal Society research fellow at ARM Ltd, Cambridge, the UK working on high-level modeling of the energy consumption of heterogeneous many-core systems. Dr. Nunez-Yanez is the PI in several industrial and UK research council projects in energy efficient and high-performance computing including a CASE award by ARM in the field of run-time energy prediction and energy-aware scheduling. He has also written and co-written more than 100 publications in this area.

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