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True-time delay (TTD) cells are used in timed array receivers for wideband multi-antenna topologies. TTD cells are divided into two major categories: silicon-based and non-silicon-based structures. Non-silicon-based structures have very good bandwidth but are bulky in the below 10 GHz frequency band. Silicon-based TTD cells are much more compact and better candidates for integrated circuit (IC) design. Passive and active approaches are the two ways to have a silicon-based TTD cell. Passive TTD cells are built by transmission lines (TL), artificial transmission lines (ATL), and LC ladder networks. Their power consumption is very low, and the delay bandwidth is good, but they are still bulky at low frequencies like below 5 GHz applications. Active all-pass filters as TTD cells are presented for these issues. In this chapter, we will discuss the challenges of inductor-based TTD cells. Then, inductor-less TTD cells are presented to address some of the previous structure’s issues. Finally, we will talk about these structures’ challenges as well. Then, the nonidealities effects on the TTD cell’s performance are investigated, and the body bias technique is presented to address these issues.
*Address all correspondence to: ahmad.yarahmadi@modares.ac.ir
1. Introduction
Nowadays, linearity and dynamic range are critical issues for radars, A/D conversion, multi-standard applications like IoT or 5G/6G communications, receiver chains in communication systems, data processing, and imaging sensors [1, 2, 3, 4, 5, 6]. Multi-antenna systems like phased array topologies are suitable for this matter since they can do analog beamforming with very good performance in narrow-band applications [7]. They can do the beamforming task with an approximation of the incident signal. They approximate the delay of the signal with phase change in the phased array multi-antenna system [8]. This approximation is one by phase shifters as the core block of a phased array system. They are quite good for narrow-band signals, but for wideband applications, they suffer from the beam squint phenomena [9].
Unfortunately, other problems arise in wide-band applications like intrinsic narrow-band characteristics, spatial interferences, pulse dispersion, and inter-symbol interference (ISI) [10]. So, another topology must be considered for this matter, leading to the timed array receiver. This structure replaces phase shifters with TTD cells as the system’s core in wide-band applications. The TTD cells delay the received signal in contrast to phase shifters which approximate the delay time with a phase shift.
There are two approaches to creating a TTD cell, silicon-based and non-silicon-based TTD cells [2]. Non-silicon-based TTD cells have better performance than silicon-based TTD cells but have some limitations like considerable production cost concerning the rival. So, although the silicon-based TTD cells have a significant loss and high footprint, they are preferable for mass production and low-cost purposes [10]. Silicon-based TTD cells have two separate categories. Passive TTD cells are based on transmission lines (real or artificial) and LC ladders [11, 12]. These topologies have great performance for high frequencies (10 GHz and beyond). But they are very bulky for low frequencies. Active TTD cells are a solution for below 5 GHz applications. in these topologies, all-pass filters are used to create an active TTD cell, and passive inductors are used to ensure the wideband performance of the structure [4, 13].
Figure 1 shows the literature review of TTD cells, and the state-of-the-art design in this area is depicted. This chapter discusses the reason for the high DV (delay-variation) for larger delay amounts in the inverter-based inductor-less active TTD cell. Also, the mechanism of the body biasing scheme for improving the performance of the TTD cell is presented, too.
Figure 1.
The diagram of the literature review of TTD cells.
Based on the above discussion, an active all-pass filter can be a good solution for designing a true time delay cell. However, there are some design considerations about the low frequency (below 10 GHz) wideband design of TTD cells. In the following paragraphs, we will discuss why an inductor-less TTD cell is needed and why Padé approximation is used to create an all-pass transfer function from the TTD transfer function. Also, we will see the minimum and maximum available delay amounts for a TTD cell with proper characteristics.
2.1 Inductor-less design
In this chapter, we have focused on low-frequency wideband applications. Most of this band’s applications demand a very compact structure. Also, the integration ability of circuits is necessary because these cells will be used in the mass production of different devices. So, the chip area and production cost are very important issues, too. On the other hand, the structure must work in various applications. For example, it could be a part of a multi-input multi-output structure like a smartphone, drone, or even an automobile.
An inductor is a bulky and limiting element, and this issue is critical for low frequencies like 1–5 GHz applications because they are large enough in this band. As a result, there is a trade-off here in choosing an inductor [4, 14]. If high-quality off-chip inductors are used, the total cost will increase dramatically. Furthermore, the system’s performance will be impacted and bounded if the on-chip inductor is used.
This trade-off could be minimized with advancing technology because on-chip high-quality inductors are available for the advanced chip technologies. Another benefit of these technologies is their smaller parasitic capacitances, which lead us to use inductor-less designs with acceptable wideband performance.
Another issue for inductor-based designs is that the design transformation from one technology node to another (mostly to an advanced one) has a complex procedure. In contrast, it is very simple for an inductor-less design to be transformed into another technology node. This issue is so important concerning the technology improvement speed. Since we almost need to redesign an inductor-based structure, design cost, and total cost are more in these topologies.
However, the chip production cost is higher for more advanced technology nodes. So, there are better choices than bulky elements like inductors below 5 GHz applications. They will impact the total budget of the design dramatically. On the other side, mass production demands production costs as low as possible in most applications.
In the layout and tape-out steps of the chip design, we need to use a trial-and-error procedure to find the proper performance of an inductor-based structure since there is no exact model for them. It forces us to need more design time and lead us to more design cost. Although off-chip inductors are a good candidate to eliminate some of the above issues, they will increase the total cost dramatically, which eventually leads us to a lower yield.
Recently inductor-less active TTD cells have been presented in the literature to address these issues. In these active TTD cells, the transfer function of the cell will be approximated with an all-pass filter, usually with Padé or Taylor approximation. Nevertheless, these topologies suffer from high DV (delay variations) in their wideband performance [4, 11, 13]. Inverter-based active TTD cells are presented to overcome their DV issue of them in the 1–5 GHz band [15]. This TTD cell delays the incident signal with 10 ps and 3% DV. However, for larger delay values, the DV of the TTD cell will drop dramatically (for example, for a 50 ps delay amount). The body bias technique can be applied to the TTD cell to address this issue.
2.2 Minimum and maximum required delay amount
Delay systems consisted of several delay cells to create a timed array receiver. In a timed array receiver and for a lined antenna topology based on the number of antenna elements, their topology, the distance between the elements, operational frequency, etc. A minimum and maximum required delay can be calculated for a specific purpose [16]. Assume the system has an N-element antenna, the operational frequency is from fmin to fmax, the maximum steering angle concerning boresight is ±θ, and b-bit spatial resolution is required. The noise figure (NF) is set to be better than NFmax; there is no grating lobe and 40 dB depth for sidelobe is available.
For this preferred system, the distance between antenna elements, maximum delay amount, delay step (minimum delay), and noise figure of each channel can be calculated as follows [17, 18]:
To avoid grating lobes, d, the distance between antenna elements should be less than half of the wavelength of fmax:
d≤λf,max2E1
The maximum required delay amount of a timed array system is equivalent to the maximum steering angle of the system (θmax). It depends on three terms: the number of antenna elements (N), the distance between antenna elements (d), and the maximum steering angle (θmax). Concerning these terms, the maximum required delay amount of the channel will be [10]:
τmax=N−1dsinθmaxcE2
In this equation, c is the speed of light in a vacuum. From this equation, and for the incident signal angle concerning bore sigh (θin), the delay step can be calculated as follows:
Δτ=N−1dsinθincE3
This delay step in a timed array receiver equals a 4-bit resolution in a phased array receiver system. The minimum delay of the timed array system also can be calculated as the following equation:
τmin=sinθmin2fE4
Based on the above discussion, four antenna elements in a lined topology are required for an assumed 1–5 GHz application and 60 degrees of steering angle with a 4-bit resolution. The distance between them will be d = 3 cm, the maximum delay amount will be 260 ps, and the minimum delay amount will be 12.5 ps.
With this information, we can design the required delay system as shown below, so the delay block, which means a true time delay cell, can be designed for this system (Figure 2).
Figure 2.
The timed array system with four antenna elements in the lined topology.
2.3 Delay approximation accuracy analysis
The two most common approaches to approximating true time delay transfer function (TF) are the Padé approximation and Taylor approximation. The Taylor expansion of ideal delay TF can be written as follows [19]:
e−sT≃1−sT1!+sT22!+…+−1nsTnn!E5
However, this TF does not meet the physical requirements to create a filter. To make it feasible for filter design, we must modify this equation with the following one:
e−sT=e−sT2+T2=e−sT2e−sT2=e−sT2esT2E6
As a result, this modification improves the approximation’s accuracy, so the Taylor approximation is applicable for delay approximation for below 4th-order approximations. The fifth order and above approximations will face instability issues and are not available for filter design. The Taylor approximation for 1 to 5-order approximations is shown in Table 1.
The Taylor approximation for the time delay transfer function.
Based on these five transfer functions, the MATLAB simulation for their step response concerning true time delay is done, and the results as the order of approximation increases, the precision increases, too.
Another approach to creating the TF of an all-pass filter is the Padé approximation. In this case, the TF of true timed delay will approximate with this eq. [20]:
e−sT≃∑i=0n+m−1isTii!=∑i=0mpisTi∑i=0nqisTiE7
Table 2 shows the TF of the approximation for one to five orders. Furthermore, Figure 3 depicts their frequency response versus the ideal step response. It is worth mentioning that in practical designs, because of unstable zeros of TF, below 10-order approximations are feasible. This approximation does not need any modifications for lower orders. So, it can be a better choice for simple designs. Based on these five transfer functions, the MATLAB simulation for step response of them concerning true time delay is done, and the results are shown in Figure 3.
The Padé approximation for the time delay transfer function.
Figure 3.
The step response of equal order numerator and denominator of the TF’s fraction for Padé approximation versus TTD for a 5-second delay.
The simulations of both approximations show that the Padé approximation has a more accurate response concerning Taylor approximation. For example, for the 5th-order approximation, the accuracy of Padé is 30 times better than Taylor’s approximation.
So, the first step to designing a TTD cell is to use a Padé approximation with proper order for an intended purpose. Because lower orders are simple, but higher orders are more accurate. For our TTD cell, we have focused on simplicity, So the lower orders are chosen.
Another important issue that is remained here is the difference between true time delay (τd) and group delay (τg). To investigate more about them, first, the phase response of both first and second-order approximations are calculated here:
φ1st,orderω=−2tan−1ωT2E8
φ2nd,orderω=−2tan−16ωT12−ω2T2E9
From these two equations, the delay amount of both approximations can be calculated:
τd1ω=−φ1st,orderωω=2tan−1ωT22E10
τ2ω=−φ2nd,orderωω=2tan−16ωT12−ω2T22E11
Furthermore, from these equations, the group delay of both approximations can be calculated:
τg1ω=−ddωφ1st,orderω=21+ωT2E12
τg2ω=−ddωφ2nd,orderω=273+ω3T312+35ω2T212−ω2T2E13
2.4 Maximum available flat delay amount
From these four equations, the group delay and true time delay are equal when the phase changes are linear, i.e., linear phase response. This matter can be calculated from these equations:
τg=τd
⇒−φωω=−dφωdω
⇒dωω=dφωφω
⇒∫dωω=∫dφωφω
⇒lnφω=lnω+c
⇒φω=elnω+c=elnωec
⇒φω=C.ωE14
From the above calculations, and concerning the value of phase, we can write the below equation for both first and second-order approximations:
φω=−2ArctanωT2=LinearCωE15
φω=−2Arctan6ωT12−ωT2=LinearCωE16
Both equations are arctangent-based. As shown in Figures 4–6, the response will be linear up to 23 degrees (0.4 radians) which means, until the phase argument reaches this amount, the output of the TTD cell will remain linear.
Figure 4.
The comparison between y = arctan (x) and y = x.
Figure 5.
The comparison between y = arctan (x) and y = x in magnified mode.
Figure 6.
The inverter-based inductor-less TTD cell is proposed in [15].
So, for the 5 GHz application, this maximum delay can be calculated from the previous Eqs. (15) and (16). For the first-order approximation, the delay amount will be T = 25 ps, and for the second-order approximation, the delay amount will be T = 24 ps. Up to this amount, the TTD cell will remain in a linear area, and the group delay and true time delay are equal.
It is why most active TTD cells with larger delay values suffer from DV in lower frequencies. For example, [13, 14] tried to provide 24 ps and 59 ps delays, but they have 30% and 50% DV. [11, 21] also have a borderline 10% DV for their bandwidth.
So, for having larger delays, it is inevitable to use circuit-level or system-level approaches like master-save, DLL (delay lock loop), and phase linearizer to address this issue [10, 22, 23].
2.5 Inductor-less TTD cell with COMS inverter cell
As mentioned above, the ideal transfer function of a TTD cell can be approximated with Padé approximation [15]. The equation of this approximation can be written as follows:
Hs=e−sτ≈2−sτ2+sτ=1−sτ21+sτ2=−−21+sτ2+1E17
This equation shows that the all-pass filter can be created with a low pass filter and a gain stage. The inverter-based structure for a TTD cell is proposed in [15] as shown in Figure 6.
In this TTD cell, the second path is the gain stage with a gain of 2. It consists of M4 and M5. The first pass is the low pass filter section which consists of M1, M2, M3, R, and C. To investigate the structure’s performance, first, we must calculate the low-frequency gain of the cell. The overall gain of the structure ignoring parasitic capacitances comes from this equation:
voutvin=Av1+Av2
Av1=gm3gm4+1/RL1−Rgm1+gm21+sCR,Av2=gm5gm4+1/RLE18
In this equation, Av1 and Av2 are the low-frequency gains of the first and second stages. The overall gain is the summation of these two gains since the two paths are parallel. In this equation, R and C are the feedback resistor and second-stage capacitances of the TTD cell. RL is the output load (usually 50 ohms). gm1, gm2, gm3, gm4, and gm5 are the M1 to M5 transconductances. This gain can be rewritten as follows if we made some assumptions:
voutvin=Av1+Av2=1−sRC1+sRC
if
gm5=gm4+1/RL,gm31−Rgm1+gm2gm4+1/RL=−2E19
With this assumption, the all-pass filter with equal frequency for the left-handed pole and right-handed zero is created. From the previous discussion, the true time delay of this TTD cell can be calculated as follows:
τdω=2tan−1ωRCωE20
This equation means that the delay of the TTD cell can be manipulated just with the R and C of the TTD cell. Although all parasitic parameters can change the value, R and C are the dominant parameters for this matter. While R is used as the feedback resistor and ensures the wideband application of the structure, capacitor C is relaxed to create an arbitrary delay amount. There are many trade-offs and non-idealities in the TTD cell design, like input capacitance of the stage, parasitic zero and pole, limited bandwidth, finite output impedance, noise, and nonlinearity of the structure. They are deeply discussed in [15]. The TTD cell must have input/output impedance matching since it may work in a delay line.
From Figure 7, the TTD cell provides a 10.6 ps delay amount with 3% DV in the 1–5 GHz. The loss of TTD cells is acceptable, and S21 is better than −3.9 dB. The TTD cell has input/output impedance matching, and S11 and S22 are below −10 dB. This TTD cell works well to provide a 10 ps delay amount. However, a larger delay will have a bounded delay bandwidth, and the DV will arise, as discussed earlier. Another issue for this novel structure is its performance against process variations, aging effects, field variations, and other non-idealities. We need a solution to ensure its performance against these issues.
Figure 7.
The S11, S22, gain, and delay of the TTD cell.
2.6 The TTD cell improvement
There are two major issues in inductor-less TTD cells. The High value of DV for large delay amounts and non-ideality issues like process, supply voltage, and temperature (PVT) variations, aging effects, and mismatch between TTD cell’s devices. A few approaches to address these issues are discussed in the introduction section. Here we will discuss another approach to improve the TTD cell’s performance.
As the semiconductor industry develops, the size of the transistors decreases. This size reduction causes some stability issues for transistors, especially for high-frequency applications. Due to this size reduction, the transistors are more sensitive to PVT variations, aging effects, and field variations.
The effect of these non-idealities will show on the change in threshold voltage of the transistor, which changes the transistor’s transconductance and noise parameters of the device. The threshold voltage can be defined as a function of three parameters as follows:
Vt=Vt0+γ2ФF−VBS−2ФFE21
In this equation, Vt is the threshold voltage when the body bias is available (VBS, not zero), Vt0 is the threshold voltage when the body bias (VBS = 0 V) is zero, Ф𝐹 is the Fermi potential, and usually is 0.3–0.4 V1/2. γ is the body parameter, also known as the body coefficient, and comes from the below equation:
γ=toxεox2qεSiNAE22
In this equation, tox is oxide thickness, εox is the permittivity of oxide,εSi is the permittivity of silicon, NA is the doping density, and q equals the electrical charge. γ is always positive.
From Eq. (21), Process variations change the body coefficient, which leads to Vt variation. Temperature variations and field effects change the Fermi potential level, which leads to Vt variation, too. Fortunately, from Eq. (21), another phenomenon can be observed. If the threshold voltage faces any change by the non-idealities, we can manipulate it by VBS to compensate for that variation deliberately.
With this technique, we can provide a larger delay with the proposed TTD cell since any delay variation can be tuned by the body bias of the TTD cell’s devices. Moreover, the structure will be robust against any non-ideality from PVT, again effects or field effects.
The results of the body bias technique are depicted in Figure 8. Delay, S11, S22, and S21 with and without body bias techniques are depicted in this figure. The delay amount of the TTD cell is 50.95 ps with only 2% DV in the 1–5 GHz band. The TTD shows a flat delay response compared to the TTD without body bias. The loss (S21) of the TTD cell is improved, and we have a flatter S21 parameter. S11 and S22 are below −10 dB and improved with the body bias technique.
Figure 8.
The Results of TTD cell with and without body bias technique.
In this chapter, we have discussed wide-band TTD cells. There are two major TTD cells, silicon-based and non-silicon-based TTD cells. In this chapter, we studied why silicon-based TTD cells are used in today’s IC design. Then we faced two major approaches for designing a silicon-based TTD cell. Active TTD cells are used for high frequencies (upper than 10 GHz), and active TTD cells are used for low frequencies (below 5 GHz). Active TTD cells have two topologies, inductor-based TTD cells, and inductor-less TTD cells. This chapter deeply discussed why we do not prefer inductors in our designs. Also, active TTD cells suffer from high DV, which its roots are discussed here. Finally, we have presented an inductor-less inverter-based TTD cell. This cell works well, but if we need large delay amounts, it will face high DV, too. The body bias technique is applied to the TTD cell to overcome the DV issue. The results are fruitful, and the structure provides larger amounts of delay with a flat frequency response. Moreover, the TTD cell is robust against non-idealities like PVT variations, aging effects, and field effects.
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Written By
Ahmad Yarahmadi
Submitted: 26 December 2022Reviewed: 30 March 2023Published: 19 April 2023
Open access peer-reviewed chapter
