Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC Converter (2-pscB)

Abstract

In this chapter, we introduce the concept of the Inherited Automatic Current Sharing Mechanism (ACSM) in a two-phase series capacitor buck topology (2-pscB). This topology was introduced to power laptops as low-voltage and high-current Voltage Regulator Modules as well as non-isolated Point-of-Load converters (Vin < 12 V). To satisfy the converter stability, a state-space modeling technique of switching intervals coupled with parasitic component linearization is developed. Due to the series capacitor charging period miscalculation, the applicability of the ACSM of 2-pscB switching topology for high-power electronic applications is still very limited. Inserting a series capacitor between power switches of phase A increases loop parasitic inductance, introduces a time delay mismatch between the gate voltages of the two switches, and causes interference with the synchronization of the dead time between both phases of 2-pscB converters since the phase B has no series capacitor. This mismatch reduces the heat distribution efficiency and lifetime. As such, a complete model study delivered by the converter is required to design a robust controller. Driven to explore the series capacitor voltage feedback mechanism, frequency analysis of transfer functions, and filter behavior with experimental prototype examples (Vin < 120 V) have been presented for the first time to demonstrate the theoretical analysis. Obtained efficiency was up to 94.9% at full load.

1. Introduction

The current sharing mechanism concept for conventional multi-phase converters, which are designed based on sensing each phase current to deliver the current information to their controllers, is one of main issues of its implementation. In conventional buck converters, this mechanism may require a preset current sharing ratio at the expense of efficiency, which eventually requires a larger sensing circuit to achieve the sensing accuracy of each phase. Introducing the concept of automatic current sharing in two-phase series capacitor buck topology (2-pscB) is one of the solutions to tackle this issue.

One of the main benefits of a 2-pscB converter is power management to obtain the highest performance of the regulator, automatic power management between phases is used, and the current is evenly distributed between the phases. If the current balance is not fully achieved, input and output ripple cancelation benefits are interrupted, resulting in stability problems. With complete current sharing, better thermal performance and efficiency at higher loads are guaranteed, because all output load is not concentrated in one group of Si MOSFETs/GaNs switches or in a single inductor; otherwise, the unmatched currents may cause a sharp drop in efficiency, instead of two or more phases sharing the thermal burden, the current will pass and cause failure in one phase. The typical topology and time intervals for 2-pscB are shown in Figure 1.

Figure 1.

Two-phase series capacitor buck converter a) topology and b) time intervals.

There are many advantages attached to this power conversion topology, such as:

• Reducing switching voltage level (e.g., reducing V_DS by half). This results in better efficiency when switching losses E_oss is reduced and becomes suitable for high-switching frequencies.

• Reducing output voltage ripple and current ripple by the third.

• Reducing the size of the filter inductor by almost half.

• The inductors act as current sources to softly charge and discharge the series capacitor in four-mode power stages (self-charging).

• Flexible intervals time where intervals can (nearly) be reduced to two as a regular buck.

• Automatic current balancing between phases can be easily achieved when the two inductors have the same size, same storage energy, and the inductors’ current shapes are the same. In special cases, even if the inductors are not the same, e.g., manipulating the pulse intervals can achieve the current balancing by increasing one or more switch duty cycles.

• In general, there is no need to have any phase current sensing elements to achieve the current sharing, which is a critical issue for distributing the heat, especially at high current demand.

• The duty ratio is doubled to achieve the same specification of a single buck compared with conventional buck converters for the same conversion ratio; this makes series capacitor buck topology easier to control in high-frequency applications.

2. The 2-pscB regulator states equations

The main objective of this section is to derive the transfer functions governing the operation of the 2-pscB converter. Since this converter is nonlinear and time-varying, it utilizes the switching function of the converter power device to achieve high efficiency. Due to the non-ideal characteristics of the switches and their conduction mode resistance during the switching transition, and because the voltage and current will not suddenly become zero during the switching time, this response brings a certain power loss to the system. In modeling, the load current is assumed to be unknown, as such assumed that this topology consists of non-ideal (transistors, inductor, and capacitor), and they have resistance in conduction conditions. The nonlinear—regulator active switches—circuit elements have other non-ideal effects like a voltage drop of conduction mode of active switches, which is neglected due to the complexity of modeling process. This state-space averaging model could be used to design a robust controller that can satisfy the stability and performance conditions of the converter. Small-signal model linearization of four switching intervals using a state-space average model is required. However, the non-idealistic nature of switches with their conduction mode resistance generates some power losses due to the finite voltage and current during switching transitions. Therefore, a complete model includes all the system parameters has to be generated, such as the turn-on resistance of the diode switch, the parasitic resistances of the inductor and capacitor, and the unidentified load current that can be delivered from the converter. The first step in modeling is to convert a complex circuit into a simplified circuit, in which circuit rules can be established. In a switching regulator, a component that stores energy in a circuit or system (such as capacitor voltage and inductor current) is of great significance. The linear and time-invariant system consists of four regions: the two on-regions of input source and series-capacitor energy storage source and two off-regions. The on-time is denoted by D₁T, D₃T, and the off-time is denoted by D₂T, (1 − D₁-D₂-D₃) T.

Thus.

$${\mathrm{d}}_1\mathrm{T}={\mathrm{D}}_1\mathrm{T}.$$

$$\left(d_{\mathit{2}}-d_{\mathit{1}}\right)T=D_{\mathit{2}}T.$$

$$\left(d_{\mathit{3}}-d_{\mathit{2}}\right)T=D_{\mathit{3}}T.$$

$$\left(1-d_{\mathit{3}}\right)T=\left(1-D_{\mathit{1}}-D_{\mathit{2}}-D_{\mathit{3}}\right)T.$$E1

In which T is the period of the steady-state output voltage. Figure 1 shows a two-phase series capacitor buck switching regulator. The four switches are turned on (off) by a pulse with a period of T, and its duty cycle is d seconds. Therefore, we can represent the simple equivalent circuit of the system in four on and off modes. To look at the stages of operation of this converter in a steady state during the first mode, the high-side switch of phase A, switch Q₁₁, is on, and the inductor current in inductor L₁ charges up the series capacitor a small amount. Using two series capacitors or more Cs₁, Cs₂, .., Cs_n in parallel will reduce the parasitic resistance r_Cs to half or less. This topology has a duty cycle as follows.

$$\frac{V_o}{V_{\mathit{\text{in}}}}=\frac{d_1\left(d_3-d_2\right)}{d_1+d_3-d_2}=\frac{D_1{D}_3}{D_1+D_3}$$E2

Where $d_1$, $d_2$, $d_3$ represent intervals for capacitor series buck modes.

When these intervals are equal $D_1$= $D_2$ = $D_3$ = D = t_on/T.

Hence,

$$\frac{V_o}{V_{\mathit{\text{in}}}}=\frac{D}{2}=\frac{t_{\mathit{on}}}{2T}$$E3

At current sharing balance between the two phases, switching voltage must be the same where,

$$d_1\left(V_{\mathit{\text{in}}}-V_{\mathit{Cs}}\right)=V_{\mathit{Cs}}\left(d_3-d_2\right)$$E4

or

$$\frac{V_{\mathit{Cs}}}{V_{\mathit{\text{in}}}}=\frac{d_1}{d_1+d_3-d_2}=\frac{D_1}{D_1+D_3}$$E5

From Eqs. (2, 5) at steady-state condition we conclude that

$$\frac{V_o}{V_{\mathit{cs}}}=D_3$$E6

Consideration of i_L, v_Cs, and v_Co as our state variables of the continuous-time LTI system consists of a state equation and output equation. As a result, the multiphase controller maximizes the duty cycles of both phases during the transient period to the maximum of 25% of the period while maintaining 25% of the time between each duty cycle. All phase inductors that parallel each other are reduced by several phases where a smaller equivalent inductance can charge the output capacitor faster than bigger ones. This issue also reduces the overshooting when the excess charge stored in the inductor of each phase partially discharges at the phases turn-off state, and then the rest transfers to the output capacitor.

On the other hand, the first drawback of this topology is that it has a 50% duty cycle limit. This limitation means that the high-side switches Q₁₁ and Q₂₁ cannot be turned on at the same time, coupled with the fact that conventional buck gives the converter an inherent 2:1 step-down; therefore, the theoretical minimum input voltage rate is four times the output voltage. In other words, the minimum input voltage is going to be almost five times the output voltage when we take losses into account.

$$V_{\mathit{\text{in}}}\ge \mathit{4}\left(V_o+E_{\mathit{oss}}\right)$$E7

3. Small signal average switching model

In literature, many approaches have been proposed for modeling DC-DC converters, e.g., averaged nonlinear formulation in which switching frequency is dependent. Another approach is large-signal presentations of the variable-structure system [1], where the state-space averaging approach is widely used, which yields an average and linearized model formulation [2] depending on the switching frequency, this model is non-linear and time-varying [3]. The sources of disturbance in power DC-DC systems are many [4, 5]. Figure 2 shows a functional diagram representing some of these sources, where v_o and i_L are dependent on independent inputs.

Figure 2.

Block diagram illustrated the dependence of v_o on independent inputs.

$$v_o\left(t\right)=f_1\left\{v_{\mathit{\text{in}}}\left(t\right),i_{\mathit{\text{out}}},D_1\left(t\right),D_3\left(t\right)\right\}$$E8

$$i_L\left(t\right)=f_2\left\{v_{\mathit{\text{in}}}\left(t\right),i_{\mathit{\text{out}}},D_1\left(t\right),D_3\left(t\right)\right\}$$E9

The equivalent circuit model of the 2-pscB converter can be expressed as seen in Figure 3, which contains four independent inputs (input voltage, two control input variation, and load current) and one output dependent variable. Therefore, the ideal transformer averaging model concept can be directly applied to represent the converter.

Figure 3.

The 2-pscB system ac small signal variations model.

$$V_{\mathit{sw}1}=D_1\left(V_{T1}-V_{T2}\right)=D_1\left(V_{\mathit{\text{in}}}-V_{\mathit{Cs}}\right)$$E10

$$V_{\mathit{sw}2}=D_3\left(V_{T2}-V_{T3}\right)=D_3{V}_{\mathit{Cs}}$$E11

By realizing Eqs. (10) and (11), a large signal average switch model can be formed with transformers and similar average current equations, hence,

$$v_y=v_{\mathit{\text{in}}}-v_{\mathit{Cs}}$$E12

$$i_L\left(t\right)=i_{P1}\left(t\right)+i_{P2}\left(t\right)$$E13

$$\frac{v_o}{i_L}=R//\frac{1}{S{C}_o}$$E14

where p₁, p₂ are phase current points, at complete current sharing conditions, ideal transformers for both phases will be symmetrical such as

$$D_1{i}^{\mathrm{ˆ}}{p}_1=D_3{i}^{\mathrm{ˆ}}{p}_2$$E15

Another way to illustrate 2-pscB converter system ac small signal variations model is seen in Figure 4, the output voltage variation can be expressed.

Figure 4.

Open loop impedance of 2-pscB converter.

$$v_o\left(s\right)=G_{\mathit{vd}}\left(s\right)\left\{D_1\left(s\right)+D_3\left(s\right)\right\}+G_{v-\mathit{\text{in}}}\left(s\right)v_{\mathit{\text{in}}}\left(s\right)-Z_{\mathit{\text{out}}}\left(s\right)i_{\mathit{\text{out}}}\left(s\right)$$E16

Where $G_{v-\mathit{\text{in}}}\left(s\right)$ and $G_{\mathit{vd}}\left(s\right)$ are the line-to-output and control-to-output transfer function expression, respectively. Manipulate block diagram to solve for $v_o\left(s\right)$. Hence

$$v_o=V_{\mathit{ref}}\frac{G_c{G}_r{G}_{\mathit{vd}}/V_M}{1+H{G}_c{G}_r{G}_{\mathit{vd}}/V_M}+V_{\mathit{\text{in}}}\frac{G_{v-\mathit{\text{in}}}}{1+H{G}_c{G}_r{G}_{\mathit{vd}}/V_M}\pm i_{\mathit{\text{out}}}\frac{Z_{\mathit{\text{out}}}}{1+H{G}_c{G}_r{G}_{\mathit{vd}}/V_M}$$E17

which is of the form,

$$v_o=V_{\mathit{ref}}\frac{1}{H}\frac{T}{1+T}+V_{\mathit{\text{in}}}\frac{G_{v-\mathit{\text{in}}}}{1+T}\pm i_{\mathit{\text{out}}}\frac{Z_{\mathit{\text{out}}}}{1+T}$$E18

With $\mathsf{T}\left(\mathsf{s}\right)=H\left(s\right)G_c\left(s\right)G_r\left(s\right)G_{\mathit{vd}}\left(s\right)/V_M$

$T\left(s\right)$ is the product of the small-signal gains in the foreword and feedback paths of the control loop, the modulator voltage is V_M, and H(s) is the current sensor gain. $Z_{\mathit{\text{out}}}$ is converter output impedance formula. To find the output voltage at the equilibrium case and complete current sharing, writing the KVL for the simple loops of Figure 5, we get:

Figure 5.

Complete block diagram of two-phase series capacitor voltage regulator.

$$v_o=i_L\left(R//\frac{1}{s{C}_o}\right)=\left(i_{L1}+i_{L2}\right)\left(R//\frac{1}{s{C}_o}\right)$$E19

$$i_{L1}\left(2\mathit{sL}\right)-i_{L2}\left(\mathit{sL}\right)=\frac{1}{2}{v}_{\mathit{\text{in}}}{D}_1+\frac{1}{2}{v}_{\mathit{\text{in}}}{D}_3$$E20

$$i_{L2}\left(\mathit{sL}\right)-i_{L1}\left(\mathit{sL}\right)+i_{L2}\left(R//\frac{1}{s{C}_o}\right)=\frac{1}{2}{v}_{\mathit{\text{in}}}{D}_3$$E21

After calculating the previous equations, we conclude

$$v_o=\frac{2R}{\mathit{sL}\left(\mathit{sR}{C}_o+1\right)}\left(\frac{1}{4}{v}_{\mathit{\text{in}}}\left(D_1+D_3\right)-v_o\right)$$E22

In other words,

$$\frac{v_o}{v_{\mathit{\text{in}}}}=\frac{\frac{D_1+D_3}{4}}{s^2\frac{L{C}_o}{2}+s\frac{L}{2R}+1}$$E23

This formula represents converter line-to-output transfer function.

$${\left.G_{v-\mathit{\text{in}}}\left(s\right)=\frac{v_o\left(s\right)}{v_{\mathit{\text{in}}}\left(s\right)}\right|}_{D_1=D_3=0,i_{\mathit{\text{out}}}=0}=\frac{\frac{D_1+D_3}{4}}{\frac{s^2}{{\omega }_o^2}+\frac{s}{Q_o{\omega }_o}+1}$$E24

At $D_1=D_3=D$

$$G_{v-\mathit{\text{in}}}\left(s\right)=\frac{D}{2}=G_{\mathit{go}}$$

And

$$G_{v-\mathit{\text{in}}}\left(s\right)=G_{v-\mathit{\text{in}}}\left(s\right){\left.\right|}_{\mathit{\text{phase}}I}+G_{v-\mathit{\text{in}}}\left(s\right){\left.\right|}_{\mathit{\text{phase}}\mathit{II}}$$

$$=\frac{v_o\left(s\right)}{v_{\mathit{\text{in}}}\left(s\right)}{\left.\right|}_{D_1=0,i_{\mathit{\text{out}}}=0}+\frac{v_o\left(s\right)}{v_{\mathit{\text{in}}}\left(s\right)}{\left.\right|}_{D_3=0,i_{\mathit{\text{out}}}=0}$$E25

$$G_{v-\mathit{\text{in}}}\left(s\right){\left|{}_{\mathit{\text{phase}}I}=G_{v-\mathit{\text{in}}}\left(s\right)\right|}_{\mathit{\text{phase}}\mathit{II}}=\frac{\frac{D_{1,3}}{4}}{\frac{s^2}{{\omega }_o^2}+\frac{s}{Q_o{\omega }_o}+1}$$E26

Where the angular frequency and quality factor are

$${\omega }_o=\sqrt{\frac{2}{C_{o}L}}, Q_O=R\sqrt{\frac{2C_o}{L}}$$

To generate a Laplacian formula represents converter control-to-output transfer function $G_{\mathit{vD}}\left(s\right)$,

$${\left.G_{\mathit{vD}}\left(s\right)=\frac{v_o\left(s\right)}{D\left(s\right)}\right|}_{v_{\mathit{\text{in}}}=0,i_{\mathit{\text{out}}}=0}=\frac{\frac{v_{\mathit{\text{in}}}}{2}}{\frac{s^2}{{\omega }_o^2}+\frac{s}{Q_o{\omega }_o}+1}$$E27

$$G_{\mathit{vD}}\left(s\right)=G_{\mathit{vD}}\left(s\right){\left|{}_{\mathit{\text{phase}}I}+G_{\mathit{vD}}\left(s\right)\right|}_{\mathit{\text{phase}}\mathit{II}}=\frac{v_o\left(s\right)}{D_1\left(s\right)}{\left|{}_{v_{\mathit{\text{in}}}=0,i_{\mathit{\text{out}}}=0}+\frac{v_o\left(s\right)}{D_3\left(s\right)}\right|}_{v_{\mathit{\text{in}}}=0,i_{\mathit{\text{out}}}=0}$$E28

At complete current sharing

$$G_{\mathit{vD}}\left(s\right){\left|{}_{\mathit{\text{phase}}I}=G_{\mathit{vD}}\left(s\right)\right|}_{\mathit{\text{phase}}\mathit{II}}=\frac{\frac{v_{\mathit{\text{in}}}}{4}}{\frac{s^2}{{\omega }_o^2}+\frac{s}{Q_o{\omega }_o}+1}$$E29

To derive converter output impedance formula

$${\left.Z_{\mathit{\text{out}}}=\frac{v_o\left(s\right)}{i_{\mathit{\text{out}}}\left(s\right)}\right|}_{v_{\mathit{\text{in}}}=0,D_1=D_3=0}$$

$$=\left(R//\frac{\mathit{sL}}{2}//\frac{1}{s{C}_o}\right)=\frac{2\mathit{sL}}{s^2\frac{L{C}_o}{2}+s\frac{L}{2R}+1}=\frac{2\mathit{sL}}{\frac{s^2}{{\omega }_o^2}+\frac{s}{Q_o{\omega }_o}+1}$$E30

In some analyses, accurate models are needed; thus, these formulas represent the transfer functions with output filter parasitic components,

$${\left.G_{v-\mathit{\text{in}}}\left(s\right)=\frac{v_o\left(s\right)}{v_{\mathit{\text{in}}}\left(s\right)}\right|}_{D_1=D_3=0,i_{\mathit{\text{out}}}=0}$$

$$=\frac{\frac{D}{2}\left(s\frac{2C_o{r}_{\mathit{Co}}}{2R+r_L}+\frac{2R}{2R+r_L}\right)}{s^2\left(\frac{\mathit{RL}{C}_o+L{C}_o{r}_{\mathit{Co}}}{2R+r_L}\right)+s\left(\frac{L+R{C}_o{r}_L+C_o{r}_L{r}_{\mathit{Co}}+2R{C}_o{r}_{\mathit{Co}}}{2R+r_L}\right)+1}$$E31

$${\left.G_{\mathit{vD}}\left(s\right)=\frac{v_o\left(s\right)}{D\left(s\right)}\right|}_{v_{\mathit{\text{in}}}=0,i_{\mathit{\text{out}}}=0}$$

$$=\frac{v_{\mathit{\text{in}}}\frac{R}{2R+r_L}\left(s\frac{C_o{r}_{\mathit{Co}}}{R}+1\right)}{s^2\left(\frac{\mathit{RL}{C}_o+L{C}_o{r}_{\mathit{Co}}}{2R+r_L}\right)+s\left(\frac{L+R{C}_o{r}_L+C_o{r}_L{r}_{\mathit{Co}}+2R{C}_o{r}_{\mathit{Co}}}{2R+r_L}\right)+1}$$

$$=\frac{R}{2R+r_L}\frac{v_{\mathit{\text{in}}}\left(\frac{s}{{\omega }_x}+1\right)}{\frac{s^2}{{\omega }_o^2}+\frac{s}{Q_o{\omega }_o}+1}$$E32

Where,

$${\omega }_x=\frac{R}{C_o{r}_{\mathit{Co}}},{\omega }_o=\sqrt{\frac{2R+r_L}{L{C}_o\left(R+r_{\mathit{Co}}\right)}},Q_o=\frac{\sqrt{{\mathit{LC}}_o\left(2R+r_L\right)\left(R+r_{\mathit{Co}}\right)}}{\left(L+R{C}_o{r}_L+C_o{r}_{\mathit{Co}}{r}_L+2R{C}_o{r}_{\mathit{Co}}\right)}$$E33

Therefore, the choice of components used in a switching regulator has a large impact on its performance. Critical components such as switching elements, magnetic components, and filter capacitors all affect both the switching frequency and the overall efficiency of the converter. In the previous sections, the power switch, inductances, and capacitances were all considered ideal components. But real components are not ideal and have parasitic properties, which will affect the overall performance of the DC-DC converter. A typical output capacitor always exhibits stray elements such as r_Co. This parasitic element introduces a zero in the control-to-output transfer function see Eq. (32). The relationship between the output parasitic capacitor (r_Co + ∆r_Co) and converter control-to-output transfer function is illustrated in Figure 6.

Figure 6.

G_vD and output capacitor ESR parasitic variation from 0 to 90 mΩ.

When using the ceramic output capacitor, the output capacitor parasitic r_Co effect is aggravated at relatively high frequencies, often above the switching frequency so it can be seen in the gain graph. The parameter ${\omega }_o$ is the angular corner frequency, which is defined as follows.

$$f_o=\frac{{\omega }_o}{2\pi }$$

$$f_o=\frac{1}{2\pi }\sqrt{\frac{2R+r_L}{\mathit{RL}{C}_o+L{C}_o{r}_{\mathit{Co}}}}$$E34

To get a well-regulated average output voltage signal, the switching frequency must be greater than 10 times of angular corner frequency (cutoff frequency) for small or invisible output voltage ripple.

$$f_{\mathit{sw}}>10f_o$$

Thus, $f_{\mathit{sw}}\approx 20f_o$ is recommended. The converter output impedance transfer function formula, including output filter parasitic, is presented as follows.

$$Z_{\mathit{\text{out}}}=\frac{s^2\left(\frac{\mathit{RL}{C}_o{r}_{\mathit{Co}}}{2R+r_L}\right)+\mathit{sR}\left(\frac{L+C_o{r}_{\mathit{Co}}{r}_L}{2R+r_L}\right)+\frac{R{r}_L}{2R+r_L}}{s^{2}L{C}_o\left(\frac{R+r_{\mathit{Co}}}{2R+r_L}\right)+s\left(\frac{L+R{C}_o{r}_L+C_o{r}_L{r}_{\mathit{Co}}+2R{C}_o{r}_{\mathit{Co}}}{2R+r_L}\right)+1}$$E35

For inequality conditions, we find

$$Z_{\mathit{\text{out}}}=\frac{Z_g\left(\frac{S^2}{{\omega }_k^2}+\frac{S}{Q_k{\omega }_k}+1\right)}{\left(\frac{S^2}{{\omega }_o^2}+\frac{S}{Q_o{\omega }_o}+1\right)}$$E36

Where:

$$Z_g=\frac{R{r}_L}{2R+r_L},{\omega }_k=\sqrt{\frac{r_{L1}+r_{L2}}{\left(L_1+L_2\right)C_o{r}_{\mathit{Co}}}},Q_k=\frac{\sqrt{\left(r_{L1}+r_{L2}\right)\left(L_1+L_2\right)C_o{r}_{\mathit{Co}}}}{\left(L_1+L_2\right)+\left(r_{L1}+r_{L2}\right)C_o{r}_{\mathit{Co}}}$$E37

$${\omega }_o=\sqrt{\frac{2R+r_L}{L{C}_o\left(R+r_{\mathit{Co}}\right)}},Q_o=\frac{\sqrt{{\mathit{LC}}_o\left(2R+r_L\right)\left(R+r_{\mathit{Co}}\right)}}{\left(L+R{C}_o{r}_L+C_o{r}_{\mathit{Co}}{r}_L+2R{C}_o{r}_{\mathit{Co}}\right)}$$E38

From Eq. (35), inductance parasitic variation (r_L + ∆r_L) affects output impedance in lower frequencies, often below the switching frequency so the gain graph increases with the inductance parasitic increases, as can be seen in Figure 7.

Figure 7.

Z_out and inductor parasitic r_L variation from 0 to 90 mΩ..

Output capacitor ESR parasitic variation affects the output impedance in high frequencies, as can be seen in Figure 8. From the previous two figures, we can summarize the observations in another way, where the output impedance is represented by the contribution of the filter components, as shown in Figure 9. By the below graph’s inspection of Figure 9, we can see that the inductor resistive path r_L dominates the impedance in DC. As frequency increases, the inductor then enters the spectrum. The capacitor impedance starts to take over the inductive section at higher frequencies until it becomes a short circuit and leaves the output impedance value to its series loss r_Co. To solve for the peak value of output impedance at resonance value of f_o, since r_Co contribution is small and neglected at low frequencies.

Figure 8.

Z_out and output capacitor ESR parasitic variation from 0 to 90 mΩ..

Figure 9.

Output impedance bode diagram spectrum.

$$\left|Z_{\mathit{\text{out}}-\mathit{Max}}\right|\mathit{dB}=R\sqrt{\frac{2Z_o^2+r_L^2}{\frac{2}{Z_o^2}{\left(Z_o^2+R{r}_L\right)}^2+r_L^2}}$$E39

Where $Z_o=\sqrt{\frac{L}{C_o}}$ is the characteristic impedance of the filter.

The output filter size needs to be very carefully selected to minimize voltage drop and power loss, which can be achieved by minimizing the output impedance [6]. Therefore, to get rid of the resonance frequency and maintain a good gain value, it is necessary to select a natural frequency higher than the resonance frequency. The natural frequency should be in the output capacitor region, where the influence of inductance is minimal. Thus,

$$\left|Z_{o-\mathit{Min}}\right|\cong \sqrt{{\left(\frac{1}{2\pi f_{\mathit{max}}{C}_o}\right)}^2+r_{\mathit{Co}}^2}$$E40

4. Inductor currents derivation

Based on the concept of automatic current sharing, we need to study the inductor current of each phase. For steady-state conditions, as seen from Figure 10, during interval state one and state three, the current through the inductors increases in phase sequence because energy is being stored in the inductors from the input supply or series capacitors. During the off-time of each phase, the current through inductors decreases as both inductors are sourcing energy to the output. Note that the current increase at state one is equal to the decrease in current during state two and state three of the same phase. The average series capacitor voltage v_Cs maintains its value at exactly half of the input voltage with a small voltage ripple, thus it can be regarded as a constant voltage source. A large magnitude difference in the inductor currents with 180^o out of phase can be seen during the initial transient. This magnitude difference decreases as the steady-state condition is attained. The duration of the transient time depends on dead time matching between the two phases and can be reduced using a soft start scheme with a pre-charged series capacitor. However, this will introduce a delay time to the circuit. The output voltage ripple can be controlled by the size of the output filter. The average charging and discharging currents for the series capacitor are similar, this verifies the steady-state operation of the 2-pscB converter. From this figure, the current ripple ($∆i_{L_1}$) through the phase inductor is greater than the total output current ripple ($∆i_L$).

Figure 10.

The main waveforms of 2-pscB topology.

State four is a repeat of state two with both inductors connected to the ground and supplying energy to the output capacitor. In state one, when the average inductor current of phase A is larger than the average inductor current of phase B, the series capacitor voltage v_Cs would slowly increase. For VRMs applications, most processors recommend low-output voltage ripple where these applications demand keeping the output current ripple low. This implies the need for a large inductor, the relationship expressed as follows:

$$V_{\mathit{\text{ripple}}}=I_{\mathit{\text{ripple}}}\ast r_{\mathit{Co}},I_{\mathit{\text{ripple}}}\propto \frac{1}{L}$$E41

On the contrary, as mentioned before, the other requirement is the fast-transient response. This justifies the need for a small inductor to allow the current through the supply to change quickly, but at the same time, this assumption conflicts directly with the need for a larger inductor to minimize output voltage ripple.

A mathematical representation of the 2-pscB converter with its internal current sharing mechanism resulting from the v_Cs.Figure 11 shows the average model of the 2-pscB converter, including the main parasitic components and the CSM using the internal series capacitor voltage feedback loop. This block diagram aims to generate a reference trajectory to be used by the controller model.

Figure 11.

The 2-pscB converter average model diagram of inductor currents and current sharing mechanism.

Where the two phases’ currents are:

$$i_{L1}\left(t\right)=\frac{1}{L_1}{\int }_0^{\infty }\left(V_{\mathit{\text{in}}}{D}_1-V_{\mathit{Cs}}{D}_1-V_o\left(t\right)\right)\mathit{dt}$$E42

$$i_{L2}\left(t\right)=\frac{1}{L_2}{\int }_0^{\infty }\left(V_{\mathit{Cs}}{D}_3-V_o\left(t\right)\right)\mathit{dt}$$E43

From current (Eqs. 42, 43), the first derivative of two-phase currents is:

At $D_1=D_3=D$ and $L_1=L_2=L$

$$\frac{d{i}_L}{\mathit{dt}}=\frac{d{i}_{L1}}{\mathit{dt}}+\frac{d{i}_{L2}}{\mathit{dt}}$$E44

$$=\frac{1}{L}{V}_{\mathit{\text{in}}}D-\frac{2}{L\mathit{Co}}{\int }_0^T\left(i_L-\frac{V_o\left(t\right)}{R}\right)\mathit{dt}$$E45

The second derivatives of two-phase inductor currents, where

$$\frac{d{i}_{L1}^2}{d{t}^2}=-i_{L1}\frac{1}{L}\left(\frac{D}{\mathit{Cs}}+\frac{1}{\mathit{Co}}\right)+i_{L2}\frac{1}{L}\left(\frac{D}{\mathit{Cs}}-\frac{1}{\mathit{Co}}\right)+\frac{V_o}{L\mathit{Co}R}=a_1{i}_{L1}+b_1{i}_{L2}+c_1$$E46

$$\frac{d{i}_{L2}^2}{d{t}^2}=i_{L1}\frac{1}{L}\left(\frac{D}{\mathit{Cs}}+\frac{1}{\mathit{Co}}\right)-i_{L2}\frac{1}{L}\left(\frac{D}{\mathit{Cs}}-\frac{1}{\mathit{Co}}\right)+\frac{V_o}{L\mathit{Co}R}=a_2{i}_{L1}+b_2{i}_{L2}+c_2$$E47

Using Laplace transform, we can derive the current time domain formulas as

$$\left[\genfrac{}{}{0pt}{}{i_{L1}^{″}}{i_{L2}^{″}}\right]=\left[\genfrac{}{}{0pt}{}{a_1}{a_2}\genfrac{}{}{0pt}{}{b_1}{b_2}\right]\left[\genfrac{}{}{0pt}{}{i_{L1}}{i_{L2}}\right]+\left[\genfrac{}{}{0pt}{}{c_1}{c_2}\right]$$E48

For initial conditions of i_L1(0) = 0, i_L2(0) = 0, and.

$\frac{d{i}_{L1}\left(0\right)}{\mathit{dt}}=\frac{v_{\mathit{\text{in}}}}{L}D$, $\frac{d{i}_{L2}\left(0\right)}{\mathit{dt}}=0$

$$\frac{d{i}_L^2}{d{t}^2}=\frac{2}{L\mathit{Co}}\left(\frac{V_o\left(t\right)}{R}-i_L\right)=-\frac{2}{L\mathit{Co}}{i}_{\mathit{Co}}$$E49

Since V_in = 0 for the second derivatives, the average output capacitor current equals zero.

< i_Co > = 0, Then

$$\frac{d{i}_L^2}{d{t}^2}=0.$$

5. Series capacitor damping behavior

To examine the damping oscillation of the current sharing of the two phases regarding inductor resistive parasitic variation. Back to Eq. (42), we can express its formula as:

$$L_1\frac{d{i}_{L1}\left(t\right)}{\mathit{dt}}=V_{\mathit{\text{in}}}{D}_1-i_L{r}_{\mathit{on}1}-V_{\mathit{Cs}}{D}_1-i_{L1}{r}_{\mathit{Cs}}-i_{L1}{r}_{L1}-V_o\left(t\right)$$E50

$$L_2\frac{d{i}_{L2}\left(t\right)}{\mathit{dt}}=-i_L{r}_{\mathit{on}2}+V_{\mathit{Cs}}{D}_3-i_{L2}{r}_{\mathit{Cs}}-i_{L2}{r}_{\mathit{on}3}-i_{L2}{r}_{L2}-V_o\left(t\right)$$E51

Where r_on1, r_on2, r_on3, and r_on4 represent converter switches on-state resistances, and and r_Cs represents the total series capacitor resistive parasitic component.

Where

$$V_{\mathit{Cs}}\left(t\right)=\frac{1}{\mathit{Cs}}{\int }_0^{\infty }\left(i_{L1}-i_{L2}\right)\mathit{dt}$$E52

Plugging Eq. (52) and substituting Eq. (50) into Eq. (51), the results at full current sharing (r_on = r_on1 = r_on2 = r_on3 = r_on4, and r_L = r_L1 = r_L2) will be,

$$\frac{d^2{i}_{\mathit{Cs}}\left(t\right)}{{\mathit{dt}}^2}+\frac{1}{L}\left(\frac{d{i}_{\mathit{Cs}}\left(t\right)}{\mathit{dt}}\left(r_L+r_{\mathit{on}}+r_{\mathit{Cs}}\right)+\frac{\left(D_1+D_3\right)}{\mathit{Cs}}{i}_{\mathit{Cs}}\right)=0$$E53

To analyze the effect of $r_L$, assume that other parasitic parameters are very small or zero (ideal conditions) to simplify the results also for homogeneous second-order differential equation,

$$\frac{d^2{i}_{\mathit{Cs}}\left(t\right)}{{\mathit{dt}}^2}+\frac{1}{L}\left(\frac{d{i}_{\mathit{Cs}}\left(t\right)}{\mathit{dt}}{r}_L+\frac{\left(D_1+D_3\right)}{\mathit{Cs}}{i}_{\mathit{Cs}}\right)=0$$E54

Eq. (54) can be rearranged to

$$\frac{d^2{i}_{\mathit{Cs}}\left(t\right)}{{\mathit{dt}}^2}+2\zeta {\omega }_{\mathit{Cs}}\frac{d{i}_{\mathit{Cs}}\left(t\right)}{\mathit{dt}}+{\omega }_{\mathit{Cs}}^2{i}_{\mathit{Cs}}=0$$E55

which is in the form of a second-order differential equation, representing the damped harmonic oscillator nature with attenuation ($\zeta {\omega }_{\mathit{Cs}}$) and the angular resonant frequency of (${\omega }_{\mathit{Cs}}$)

$$\zeta =\frac{r_L}{2}\sqrt{\frac{\mathit{Cs}}{L\left(D_1+D_3\right)}}, , ,{\omega }_{\mathit{Cs}}=\sqrt{\frac{\left(D_1+D_3\right)}{L\mathit{Cs}}},Q_{\mathit{Cs}}=\frac{1}{r_L}\sqrt{\frac{L\left(D_1+D_3\right)}{\mathit{Cs}}}$$E56

Setting initial values i_Cs ($0^{+}$) = 0, From Eq. (50)

$$\frac{d{i}_{\mathit{Cs}}\left(0\right)}{\mathit{dt}}=c_s\frac{d^2{v}_{\mathit{Cs}}\left(0\right)}{d{t}^2}=\frac{D}{L}\left(V_{\mathit{\text{in}}}-2v_{\mathit{Cs}}\left(0\right)\right)$$E57

thus,

$$v_{\mathit{Cs}}\left(0^{+}\right)=V_{\mathit{Cs}}-\frac{∆V_{\mathit{Cs}}}{2}$$E58

The damped harmonic oscillator can be translated as current perturbation representing the difference in phases average inductor currents. The effect of series capacitor ESR and switches internal on-state resistance is similar to the inductor DCR effect. For different parameters settings, to find the solution of second-order, linear, homogeneous differential equations with constant coefficients, there is a need to figure out the characteristic equation as.

$$a^2+P_{1}a+P_0=0$$E59

To solve equations With real coefficients, the complex roots are always distinct if they are not purely real. So, for complex roots $s_{1,2}=\alpha \mp \mathit{j\beta }$

$$i_{\mathit{Cs}}={\lambda }_1{e}^{\mathit{\alpha t}}\mathit{\text{cosβt}}+{\lambda }_2{e}^{\mathit{\beta t}}\mathit{\text{sinβt}}$$E60

Where λ₁ and λ₂ are arbitrary constants, Figure 12 depicts this type of solution.

Figure 12.

Series capacitor characteristic equation response of (a) the difference in average inductor currents due to current perturbation in inductor currents for varying values of lumped inductor resistance and (b) the difference in average series capacitor voltage.

6. Unbalanced series capacitor voltage

The 2-pscB converter current sharing mechanism tolerance will be discussed here, for many reasons, as the case of unmatched duty cycles, this topology has the ability to maintain adequate current sharing balance for a certain limit. This limit depends on the charging time of the series capacitor, which in general is affected by the quality of series capacitor material.

Since

$$\frac{V_{\mathit{Cs}}}{V_{\mathit{\text{in}}}}=\frac{D_1}{D_1+D_3}$$

$$V_{\mathit{sw}1}=V_{\mathit{\text{in}}}-V_{\mathit{Cs}}$$

$$V_{\mathit{sw}2}=V_{\mathit{Cs}}$$

$$\frac{V_{\mathit{sw}1}}{V_{\mathit{sw}2}}=\frac{D_3}{D_1}=\frac{d_3-d_2}{d_1}$$E61

It turns out that under phase unbalanced conditions (duty cycle mismatch, phase placement issues, etc.), the transient time is longer than the transient time under balanced conditions when D₁ = D₃. For unbalanced conditions, the areas of the switching voltage node pulses for both phases remain the same for a certain tolerance or boundary.

$${V_{\mathit{\text{sw1}}}}^{\ast }{D}_{\mathit{1}}={V_{\mathit{\text{sw2}}}}^{\ast }{D}_{\mathit{3}}=V_o$$E62

An example to present these conditions is, at D₁ = 0.2 and D₃ = 0.35 or opposite values, as shown in Figure 13,

Figure 13.

The 2-pscB converter current sharing mechanism tolerance at D₁ = 0.2, D₃ = 0.35.

$$\frac{V_{\mathit{sw}1}}{V_{\mathit{sw}2}}=\pm 1.75\text{and}{V}_{\mathit{sw}1}\ne V_{\mathit{sw}2}$$E63

Therefore, phase A switching node voltage$V_{\mathit{sw}1}$ increased to compensate for the reduction in the on-time of the phase. As shown in Figure 13, in both buck phases, when the high-side switch is turned off, the low-side (synchronous rectifier) switch is turned on, and the current is circulating through the lower switch. Since the inductor current cannot instantaneously stop, the “on-time” and “off-time” of the switch are unbalanced. Each phase inductance is large enough to ensure that it works in the continuous conduction mode (CCM). For certain limits, during steady-state operation, the series capacitor voltage can still manage to maintain the desired output voltage and stabilize current sharing among the two phases [7, 8, 9, 10, 11, 12]. The 2-pscB topology has been fully investigated using different Si MOSFETs and GaN switches. The theoretical and experimental testing specifications for the eGaN-based 48 V/5Vdc 2-pscB converter are listed in Table 1.

Description	Label	Parameter
Series capacitor	Cs	< 4.7$\mathrm{\mu F}$
Phase inductors	$L_1,L_2$	4.7$\mathrm{\mu H}$
Output capacitor	Co	>70$\mathrm{\mu F}$
Switching frequency	$f_{\mathit{sw}}$	250 kHz
Input voltage	$V_{\mathit{\text{in}}}$	48 V
Output voltage	$V_o$	5-5.5 V
$\mathit{Cs}$ stray component	$r_{\mathit{Cs}}$	10 m$\mathrm{\Omega }$
Switches stray components	$r_{\mathit{on}}$, $r_{L1}$, $r_{L2}$	< 20 m$\mathrm{\Omega }$

Table 1.

2-pscB converter evaluation parameters.

Figure 14 shows the main proposed prototypes and evaluation modules of GaN transistors and Si MOSFETs 2-pscB converters at different voltage rate (V_in < 120 V). Experimental results to examine the CSM for the phase-sensorless GaN-based 48 V/5 V 2-pscB converter with an efficiency of up to 94.9% are shown in Figure 15. To construct the converter GS61004B transistors with R_ds(on) of 15 mΩ are used. Despite the two-phase parasitic components’ layout unbalance, the waveform shows output voltage, series capacitor current, and the fully automatic current balancing (≈100%) between two phases.

Figure 14.

The proposed 2-pscB converter EVM prototypes using different switches at (V_in < 120 V).

Figure 15.

The 2-pscB converter typical waveforms of i_Cs (above), i_L1, i_L2 (middle), and V_o (below) at 48 V input and 250 kHz.

The output current ripple (I_L) is less than the phase ripple (i_L(rms) = i_L1(rms) + i_L2(rms)), which is one of the technical advantages of multi-phase that the combined output ripple (total ripple) is less than the ripple current in each phase. This occurs due to driving the phases out of phase. To achieve the complete current sharing balance between two phases, the switching nodes voltage must be the same. Also, for the voltage equations of phase inductors $v_{L1}$ and $v_{L2}$ (see Figure 1a), these voltages must equal each other. This equivalency gives the expression of the series capacitor voltage in terms of the topology parasitic values as follows:

$$v_{\mathit{Cs}}=v_{\mathit{\text{in}}}\frac{D_1}{D_1+D_3}+\frac{i_{L_1}{\in }_1+i_{L_2}{\in }_2}{D_1+D_3}$$E64

Where parasitic coefficients are

$${\in }_1=r_{\mathit{on}}(1+D_3-2D_1)-D_1{r}_{\mathit{Cs}}-r_{L1}$$

$${\in }_2=2D_3{r}_{\mathit{on}}+D_3{r}_{\mathit{Cs}}-r_{\mathit{on}}+r_{L2}$$

For small variations in topology duty cycles, parasitic coefficients can be neglected. The complete current sharing conditions can be reached at${\in }_1$ =${\in }_2\cong$ (0)

Analytical and experimental comparisons between the traditional buck topology and the 2-pscB topology show that the 2-pscB topology can reduce power losses by up to 31% at full load. Analytical estimates show that the maximum converter inductor size reduces by 55%, and inductor current ripple reduces by 30% compared with conventional bucks at the same switching frequency and duty cycle. This study concludes that the 2-pscB topology requires only 34% of the conventional buck capacitor [13, 14, 15, 16]. Please note that the efficiency of this topology increases with the size of the inductor, but at the cost of transient response performance.

7. Conclusion

The main purpose of this chapter is to provide a comprehensive overview of the 2-pscB topology current sharing mechanism starting from the model of the AC small-signal variation of the system to the characteristic equations response of balanced and unbalanced series capacitor voltage. This would help in the enhancement of the overall performance. Theoretical analysis of damping behavior of series capacitor current is formulated, and series capacitor voltage compensation mechanism of the topology current was presented. Detailed studies of the mathematical representation modeling and Laplacian matrices of the 2-pscB converter with an internal voltage feedback loop were presented to help build an efficient converter controller. Based on the above, this topology needs an additional control circuit that can limit the inrush current caused by series capacitance and output capacitor charging period at the beginning of the transient time. The duration of the transient time depends on dead time matching between the two phases and can be reduced using a soft start scheme with a pre-charged series capacitor. Since phase B has no series capacitor, for traditional half-bridge gate driving circuits, inserting a series capacitor between power switches of phase A increases loop parasitic inductance, introducing a time delay mismatch between the gate voltages of the phase switches. This mismatch can eventually cause interference with the synchronization of the dead time between phase A and B of 2-pscB converters. Using traditional half-bridge gate driving circuits in 2-pscB, the turn-off delay of phase A switches caused by its C_DS discharging period appears and amplifies by parasitic effects and the phases’ sinking path mismatch. Careful consideration has to be given to the specifications of the series capacitor to tackle parasitic and mismatch problems.

Conflicts of interest

The author declares that there are no conflicts of interest regarding the publication of this chapter.