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MRAM-Based FPGAs: A Survey

Written By

Peyton Chandarana, Mohammed Elbtity, Ronald F. DeMara and Ramtin Zand

Reviewed: 21 September 2022 Published: 21 December 2022

DOI: 10.5772/intechopen.108212

Computer Memory and Data Storage IntechOpen
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Computer Memory and Data Storage

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Abstract

Over the last decade, field programmable gate arrays (FPGAs) have embraced heterogeneity in a transformative way by leveraging emerging memory devices along with conventional CMOS-based devices to realize technology-specific benefits. Memristive device technologies exhibit desirable characteristics such as non-volatility, scalability, near-zero leakage, radiation hardness, and more, making them promising alternatives for SRAM cells found in conventional SRAM-based FPGAs. In recent years, a significant amount of research has been performed to take advantage of these emerging technologies to develop fundamental building blocks of FPGAs like hybrid CMOS-memristive look-up tables (LUTs) and configurable logic blocks (CLBs). In this chapter, we will provide a brief overview of the previous work on hybrid CMOS-memristive FPGAs and their corresponding opportunities and challenges.

Keywords

  • magnetoresistive random-access memory (MRAM)
  • non-volatile FPGA
  • MRAM-based look-up table
  • hybrid configurable logic block
  • heterogeneous technology reconfigurable fabric

1. Introduction

Since the advent of the first field programmable gate array (FPGAs), there has been a gradual transition from traditional homogeneous reconfigurable fabrics, designed with one type of logic block, to the now modern heterogeneous FPGAs with special-purpose co-processors to handle specific tasks such as floating point arithmetic [1, 2]. In recent years, a new type of heterogeneity has attracted the attention of both academia and industry which involves leveraging emerging logic and memory devices within FPGA fabrics to realize technology-specific advantages such as non-volatility, scalability, low leakage power, radiation hardness, etc. Some of the most promising technologies that have been proposed as alternatives for static random access memory (SRAM) cells in FPGAs are resistive random-access memory (RRAM) [3, 4, 5, 6], phase-change memory (PCM) [7, 8, 9], and magnetoresistive random-access memory (MRAM) [10, 11, 12, 13, 14]. In this chapter, we specifically focus on MRAM-based FPGAs, but the underlying circuits and architectures discussed can be readily utilized for other resistive memory technologies.

Magnetic tunnel junctions (MTJs) are considered to be the primary component of MRAM devices. Figure 1 shows an example of the MTJ stack structure [15], which includes two ferromagnetic (FM) layers (CoFeB), called the pinned and free layers, that are separated by a thin oxide layer (MgO). The magnetization direction of the electrons in the pinned layers is fixed, while that of the free layer can switch to the parallel (P) or anti-parallel (AP) states with reference to the fixed layer. The resistance of an MTJ (RMTJ) depends on the angle between the magnetization orientation of the FM layers (θ), as expressed in the below equation [16]:

Figure 1.

MTJ stack structure [15].

RMTJθ=2RStack1+TMR2+TMR1+cosθ=RP=RStack,θ=0RAP=RStack1+TMR,θ=πE1

where RStack=RAArea, in which the resistance-area product (RA) value is determined by the material composition of MTJ’s layers. Moreover, TMR is the tunneling magnetoresistance, which depends on the temperature (T) and bias voltage (Vb) as seen below [16]:

TMRTVb=2P21−αspT3/221−P21−αspT3/22.11+VbV02E2

where V0 is a fitting parameter, αsp is a material-dependent constant, and P is the spin polarization factor [16]. Table 1 lists the experimental parameters used herein to model the MTJ devices. Spin transfer torque (STT) [18] is the conventional approach to switch the resistance state of the MTJ, where a bidirectional charge current flows through the fixed layer of the MTJ. This, in turn, generates a spin-polarized current that switches the magnetization orientation of the electrons in the free layer. Recently, it has been shown that passing a charge current through a heavy metal can generate a spin-polarized current with a ratio greater than one [19]. This means the produced spin current can be larger than the applied charge current, and thus, lower energy switching can be achieved in the MRAM cells. Readers can refer to [20] for further details about the fundamentals and modeling of MRAM devices. Proceeding with this background information on MRAM cells, we can now introduce how MRAM technology can be used as an alternative for SRAM to realize the building blocks of FPGAs, such as look-up tables (LUTs) and configurable logic blocks (CLBs).

ParametersDescriptionValue
AreaMTJ surface65nm×65nm×π/4
RAMTJ resistance-area product5 Ω.μm2
TTemperature358 K
PPolarization0.52
V0Fitting parameter0.65
αspMaterial-dependent constant2e-5

Table 1.

Parameters of STT-MTJ device [16, 17].

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2. MRAM-based look-up table (LUT) circuits

Look-up tables (LUTs) are the main building blocks in FPGAs that allow combinational and sequential logic circuits to be realized. An n-input LUT circuit includes: (1) 2n memory cells, containing a truth table of an n-input Boolean logic function, and (2) a select tree used to return the value stored in a specific memory cell specified by an address passed into the LUT circuit. Conventional LUT circuits consist of memory cells implemented using SRAM technology. This, however, introduces multiple challenges with respect to:

  • High static power: Caused by the intrinsic leakage current which increases as the transistor size decreases.

  • Volatility: SRAM’s volatility limits the energy savings that could be achieved by power-gating in FPGAs. All functions must be reprogrammed upon each power-up, and therefore, external non-volatile memory is needed to reprogram all the functions upon each power-gating cycle.

  • Low logic density: Each SRAM cell consists of six transistors which increases logic and memory footprint at scale.

In recent years, various MRAM-based LUT circuits have been proposed, where MRAM technology replaces SRAM. Similar to conventional SRAM-based LUTs, MRAM-LUTs have two operation phases: (1) the configuration phase, during which the states of the MTJs in MRAM cells are adjusted based on the Boolean logic function being stored in the LUT, and (2) the read phase, which involves reading the state of the MTJ devices in the MRAM-LUT to realize a Boolean function. The configuration operation of the MRAM cell requires special write circuitry to generate a sufficiently large spin current to switch the state of the MTJs. Figure 2 Shows four well-known circuits introduced in the literature for the MRAM write operation.

Figure 2.

Various MRAM write circuits circuit structure. (a) Current mirror write circuit [21], (b) proposed in [21], (c) proposed in [22], (d) proposed in [23].

The LUT read operation, on the other hand, involves sensing the resistive states of MRAM cells and generating the corresponding Boolean outputs, that is, “0” and “1”. A commonly used circuit for reading the state of the MTJs is a pre-charge sense amplifier (PCSA) shown in Figure 3. The PCSA circuit reads the MTJ states in two steps that could be performed in one clock cycle: (1) the pre-charge step, in which the CLK signal is in a low state (GND) that leads to turning the MP0 and MP3 PMOS transistors on, and thus, the OUT and OUT’ nodes are charged to VDD, and (2) the discharge phase, where CLK signal is in a high state (VDD) which turns off all the PMOS transistors (MP0-MP3) and consequently disconnects the OUT and OUT’ nodes from the voltage source (VDD). Therefore, the pre-charged OUT and OUT’ nodes begin discharging. The discharge speed in each of the branches of the PCSA relies on the total resistance of each branch which, itself, depends on the resistance of the MRAM device connected to it. The branch of lower resistance discharges faster than the other and therefore turns on the PMOS transistor connected to the branch of higher resistance. This causes the opposite output node of the lower-resistance branch to connect to the VDD, while the output node connected to the lower-resistance branch discharges completely to GND. A comprehensive survey of various PCSA circuits designed for sensing MRAM cells is provided in [24].

Figure 3.

PCSA circuit schematic.

One of the pioneering works on MRAM-LUT circuit design belongs to Zhao et al. [25], in which one PCSA circuit is used to sense each bit of the LUT, as shown in Figure 4a. The write circuits store each bit of the Boolean function in one MRAM cell and its inverse in another as a reference resistive memory that is used by the PCSA circuit to read the cells. A select tree is then used to read the corresponding MRAM cell, based on the input of the LUT circuit. However, the use of one PCSA per cell in the LUT for reading has led to significant energy and area overheads. Therefore, in 2012, Suzuki et al. [26] proposed an optimized MRAM-LUT design, in which only one PCSA is used in the LUT architecture as shown in Figure 4b. One branch of the PCSA is connected to the select tree and LUT MRAM cells, while the other branch is connected to a reference tree and a combination of MRAM devices. Reference tree compensates for the resistance of the select tree and the reference MRAM cells provide a total resistance value between the high resistance (RAP) and low resistance (RP) of the LUT MRAM cells. With this modification in the circuit, Suzuki et al. [26] achieved a 44% reduction in active power compared to the MRAM-LUT designed in [25]. Another well-known MRAM-LUT circuit is proposed by Zand et al. in [27]. Instead of using multiple MRAM cells to form a reference MRAM cell, Zand et al. adjusted the area of a single MTJ such that its resistance in the parallel (P) state is between the high resistance (RAP) and low resistance (RP) of the main MRAM cells in the LUT circuit. This simple modification led to a 34% improvement in the power-delay-product (PDP) value compared to the MRAM-LUT design proposed by Suzuki et al. in [26].

Figure 4.

Basic MRAM-LUT circuit structure: (a) proposed in [25], and (b) proposed in [26].

2.1 Modern MRAM-LUT circuits

Most modern FPGAs utilize more versatile LUT structures in their architecture compared to the basic designs introduced in the previous subsection. Intel FPGAs, for example, the Arria®series, Cyclone®V, and Stratix®V, use adaptive logic modules (ALMs) as their building blocks. This can simultaneously realize various types of functions such as two independent 4-input functions, a 5-input and a 3-input function, two 5-input functions, which share two inputs, and so on [28]. Similarly, Xilinx FPGAs, for example, the Virtex-7 Family, employ fracturable 6-input LUTs in their design that can realize an independent 6-input function or two 5-input functions, if they share five inputs. Recently, there have been some efforts to design novel MRAM-LUT circuits that can support functionalities similar to those of modern LUT circuits. Here, we focus on two of the well-known designs in this area, that is, adaptive MRAM-LUT and fracturable MRAM-LUT proposed in [27, 29], respectively.

2.1.1 Adaptive MRAM-LUT design

Figure 5 shows a 4-input adaptive MRAM-LUT circuit proposed in [27], which can be configured to realize different functions. There are seven types of functions that can be implemented by the 4-input adaptive MRAM-LUT: four 2-input Boolean functions, two 3-input functions, and one 4-input function. The output of each configuration is individually connected to the PCSA circuit through a mode selector that includes pass transistors to choose between the different operational modes listed in Table 2. For example, in Mode 0, the adaptive MRAM-LUT is configured to operate as a 2-input LUT and realize the logic function stored in MRAM0 thru MRAM3.

Figure 5.

The circuit diagram of a 4-input adaptive MRAM-LUT [27].

ModeS21S22S23S24S31S32S4RS2RS3RS4MRAMsFunction
10000001000−32-input
01000001004−72-input
00100001008−112-input
000100010012−152-input
00001000100−73-input
00000100108−153-input
00000010010−154-input

Table 2.

Different operating modes in the 4-input adaptive MRAM-LUT.

2.1.2 Fracturable MRAM-LUT design

Figure 6 shows the structure of a six-input MRAM-LUT circuit proposed in [29], which includes MRAM-based storage cells, a select tree, a mode selector, and two PCSAs. The fracturable MRAM-LUT circuit is capable of implementing any six-input Boolean functions or two five-input Boolean functions if the inputs are shared. The M5 and M6 signals are used to select the 5-input or 6-input functional modes of the fracturable MRAM-LUT circuit, respectively. Zand and DeMara [30] have shown that fracturable MRAM-LUT circuits can achieve significant reductions in power consumption compared to their SRAM-based counterparts. However, they have also shown that MRAM-LUTs can be severely impacted by process variation (PV), while SRAM-LUTs exhibit no read errors in presence of PV.

Figure 6.

The circuit diagram of a six-input fracturable MRAM-LUT [30].

There have been several efforts to address the PV challenges of MRAM-LUTs including the proposal of modular redundancy-based MRAM-LUT and clock-less MRAM-LUT circuits proposed in [30, 31], respectively. In [30], the authors identified the PCSA circuit as the most susceptible component of the MRAM-LUT and as a result, proposed a triple modular redundancy method to alleviate the PV impacts. As shown in Figure 7, the proposed circuit includes three PCSAs and two voter circuits that determine the output of the LUT circuit based on the majority of the PCSA’s outputs. The modular redundancy-based MRAM-LUT could successfully decrease the PV-induced read errors by more than 30% at the cost of a 24% and 6% increase in power consumption and area occupation, respectively.

Figure 7.

The circuit diagram of a six-input modular redundancy-based fracturable MRAM-LUT [30].

In another effort to reduce the impact of PV on MRAM-LUT circuits, Salehi et al. [31] propose a fracturable MRAM-LUT design that uses two MRAM cells with differential magnetization polarities to represent each bit of the Boolean function stored in the LUT. This enables replacing the PCSA circuits, which are the main source of errors caused by PV in MRAM-LUTs, with a voltage divider circuit to read the states of the MTJs, as shown in Figure 8. Since the values stored in the MRAM cells are complementary, that is, one MRAM device is used to store the data value and the other as a reference, a wide read margin is realized, and this leads to a near zero error rate for the MRAM-LUT circuit in presence of various PV scenarios in both transistor and MRAM devices. However, as shown by Salehi et al. [31], PV-tolerance is achieved at the cost of increased power consumption compared to the PCSA-based MRAM-LUTs.

Figure 8.

The circuit diagram of a six-input fracturable MRAM-LUT that uses voltage divider circuits instead of PCSAs for the LUT’s read operation [31].

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3. MRAM-based FPGAs

Figure 9 shows the typical architecture of modern FPGAs, which include configurable logic blocks (CLBs), input–output blocks (IOBs), block RAMs, programmable switch matrices (SMs), and delay-locked loops (DLLs) for clock distribution. Bitstreams are used to store the logic functions in CLBs. Any new design of FPGAs that intend to use MRAM-LUT circuits in their structure is desired to have the highest compatibility with modern FPGAs such that similar routing structures, programming paradigms, and toolchains can still be leveraged with minimal modifications. In [12], Zand and DeMara propose a hybrid spin/charge-based FPGA (HSC-FPGA) which is based on the architecture of Xilinx FPGAs, such as the Virtex 7 family.

Figure 9.

A typical FPGA architecture.

Similar to the CLBs in modern Xilinx FPGAs, the CLBs in HSC-FPGA provide logic circuits including (1) six-input LUT circuit, (2) dual five-input LUTs with shared inputs, (3) distributed memory, (4) shift registers, and (5) dedicated carry logic for arithmetic operations. In particular, as shown in Figure 10, the HSC-FPGA’s CLB architecture includes two slices to implement sequential and combinational logic functions, called Slice-S and Slice-C, respectively. Slice-C consists of SRAM-based LUT circuits that can also be used as shift registers and distributed RAM. Slice-S includes six-input fracturable MRAM-LUTs as well as latch and flip-flop circuits to realize sequential logic. Suzuki and Hanyu [32] have designed an MRAM-LUT circuit that can also operate as a shift register, however, they consume significantly higher energy compared to SRAM-based shift registers due to the high switching energy required to change the state of the MRAM cells. Overall, the simulation results, in [12], show that the HSC-FPGA can achieve more than 18% reduction in area occupation, in addition to a 70% and 15% decrease in standby power and read power dissipation, respectively, compared to conventional SRAM-based FPGAs.

Figure 10.

The structure of the CLBs in hybrid spin-charge FPGA proposed in [12].

Besides the designs discussed in this chapter, there are several important efforts in this area at different levels of design abstraction, from circuit and architecture to the fabrication of FPGA chips, with different design objectives including but not limited to: increasing performance, reducing power, area, and improving reliability and security. Table 3 lists some of these efforts in the past two decades which have advanced the area of research, achieved promising results and set the foundation for future research and manufacturing of MRAM-based FPGAs.

PaperDesign levelDesign objective
CirArchFabSpeedAreaPowerReliabilitySecurity
[33]✓✓✓
[34]✓✓✓✓
[35]✓✓✓✓✓✓
[36]✓✓✓✓
[37]✓✓✓✓✓
[29]✓✓✓✓
[38]✓✓
[39]✓✓✓
[27]✓✓✓
[40]✓✓✓✓✓
[41]✓✓✓✓
[26]✓✓
[42]✓✓✓✓
[10]✓✓✓✓
[43]✓✓✓✓
[44]✓✓✓✓✓
[30]✓✓✓✓✓
[45]✓✓✓
[46]✓✓✓
[47]✓✓✓✓✓✓
[48]✓✓✓✓
[49]✓✓✓✓
[50]✓✓✓
[51]✓✓✓✓✓
[52]✓✓✓
[13]✓✓✓✓
[53]✓✓✓✓✓
[11]✓✓✓✓✓✓

Table 3.

An overview of the MRAM-based FPGA designs in the past two decades.

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4. Conclusions

In this chapter, we provided an overview of the recent efforts in developing the next generation of FPGA fabrics which take advantage of the cooperating strengths of CMOS technology, such as fast and energy-efficient switching, and MRAM technology to attain characteristics such as non-volatility and low standby power. The prior research in this area shows that MRAM-based FPGAs can achieve significant reductions in power consumption and chip area compared to conventional SRAM-based FPGAs. However, further research is required for addressing the reliability challenges of MRAM-based FPGAs including susceptibility to process variation, and endurance of memristive devices which can impact the reprogrammability of the FPGAs. Finally, this area of research provides several possibilities for future work, such as developing memristive-based in-memory computing co-processors to handle data-intensive applications such as machine learning and graph processing in hybrid memristive-CMOS FPGAs.

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Abbreviations

FPGAField programmable gate array
CMOSComplementary metal-oxide-semiconductor
SRAMStatic random-access memory
LUTLook-up table
CLBConfigurable logic blocks
RRAMResistive random-access memory
PCMPhase-change memory
MRAMMagnetoresistive random-access memory
MTJMagnetic tunnel junctions
FMFerro-magnetic
CoFeBCobalt-ferrous-foron
MgOMagnesium-oxide
PParallel
APAnti-parallel
RAResistance-area product
TMRTunneling magnetoresistance
STTSpin transfer torque
PCSAPre-charge sense amplifier
PMOSP-channel metal–oxide-semiconductor
PDPPower-delay-product
ALMAdaptive logic modules
PVProcess variation
IOBInput–output block
SMSwitch matrix
DLLDelay-locked loop
HSCHybrid spin/charge
EDAElectronic design automation

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Written By

Peyton Chandarana, Mohammed Elbtity, Ronald F. DeMara and Ramtin Zand

Reviewed: 21 September 2022 Published: 21 December 2022

© 2022 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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