Open access peer-reviewed chapter

Robust Control Based on Input-Output Feedback Linearization for Induction Motor Drive: Real Time Implementation

Written By

Saber Krim and Mohamed Faouzi Mimouni

Submitted: 04 February 2022 Reviewed: 23 March 2022 Published: 04 July 2022

DOI: 10.5772/intechopen.104645

From the Edited Volume

Production Engineering and Robust Control

Edited by Majid Tolouei-Rad, Pengzhong Li and Liang Luo

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Abstract

This chapter proposes a design of hardware architecture of an improved Direct Torque Control (DTC) for a real-time implementation on a Xilinx Field-Programmable Gate Array (FPGA). The first contribution in this chapter consists in combining the DTC with a Space Vector Modulation (SVM) technique and an Input-Output Feedback Linearization (IOFL) approach. In fact, the classical DTC has remarkable performance in terms of fast torque response and less dependence on the system parameters. Despite the cited advantages, the classical DTC is penalized by high torque ripples and inverter-switching-frequency variations. In this context, the SVM is added to the DTC structure in order to keep the switching frequency constant and to reduce ripples. Furthermore, the nonlinear IOFL is proposed to achieve a decoupled flux and torque control. The novel structure is named in this chapter as DTC-IOFL-SVM. Moreover, this chapter presents a hardware implementation of the suggested DTC-IOFL-SVM strategy utilization. The hardware implementation is chosen in order to reduce the sampling period of the system thanks to the parallel processing of the FPGA. In order to demonstrate the performance of the FPGA implementation of the proposed DTC-IOFL-SVM, numerous simulation results are presented using the Xilinx system generator under a Matlab/Simulink.

Keywords

  • induction motor
  • direct torque control
  • input–output feedback linearization
  • FPGA

1. Introduction

Recently, the Direct Torque Control (DTC) of electrical machines has taken the attention of several researchers, thanks to its interest and advantages, like the simple structure, the fast torque response, and the less dependence on machine parameters [1, 2, 3]. The structure of the classical DTC is mainly based on two hysteresis controllers and a lookup table to independently control the torque and the flux by selecting the optimal voltage vector in each sampling period. The classical DTC suffers from several problems like the torque ripples, the harmonics in the stator current waves, as well as the variation in the switching frequency. The fixed bands of the hysteresis controllers are the main cause of these problems [4, 5].

In the recent years, several methods have been put forward for overcoming the classical DTC problems, such as the use of intelligent techniques like the artificial neural networks and the fuzzy logic [6, 7]. However, the experimental implementation of the intelligent techniques requires powerful calculation processes due to their complexity. The torque and flux ripples, and the stator current waveform distortions can be reduced by fixing the switching frequency and selecting the more appropriate voltage vector for each commutation period. Indeed, in order to impose an operation with a fixed switching frequency, a combination between the DTC and the Space Vector Modulation (SVM) has been proposed by several research studies [8, 9, 10]. In fact, the DTC with a fixed switching frequency consists in introducing two Proportional Integral PI controllers and a SVM technique to achieve the best choice of the voltage vector in each sampling period [8, 9, 10]. However, the stability and dynamics of the system will be affected by the variation in machine parameters due to the existence of the PI controllers. In order to get rid of the drawbacks of the mentioned techniques, several robust control techniques have been proposed in order to guarantee the high performance control of induction motor drives. Among of these techniques we can cite the sliding mode control, the backstepping control and the Input–Output Feedback Linearization (IOFL) approach [11, 12, 13], which are the most popular control strategies. IOFL consists in transforming a nonlinear system into an equivalent linear one, which can be utilized for controlling the system [14]. IOFL is based on an inverse mathematical transformation for obtaining a suitable control law of the Induction Motor (IM).

The main first objective of this chapter consists in combining the IOFL technique and an SVM-DTC (SVM-DTC-IOFL) in order to design a novel DTC strategy featured by fast torque and speed responses, more robustness under stator resistance variations, reduced ripples and distortions, and a decoupled control between the torque and the flux. In this study, the stator flux and the electromagnetic torque are chosen as control states to develop the decoupled model of the IM.

For real time control of electrical machines, digital electronic boards like the STM32-microcontrollers [15, 16] and the Digital Signal Processor (DSP) are usually utilized [17, 18, 19, 20]. The digital circuits based on microprocessors are known by their sequential computation of the control algorithm which consequently increases the execution time and the sampling period when the complexity of the control algorithm increases. Indeed, if the sampling time raises, the delays in the control system goes up, this causes additional ripples and distortions in the torque and the current, respectively. Moreover, the DSP controllers are chosen for implanting the control algorithms of electrical systems [21, 22], which are based on processor cores with high performance and few peripherals to communicate with the external environment. In fact, the sampling period of the processor depends of the computational burden due to the parallel processing, which creates delays in the feedback loop and raises the stator current harmonics and the torque ripples [23, 24, 25].

With the target of overcoming the DSP limitation and minimizing the DSP computational burden, a combination between the DSP and the FPGA has been proposed in the literature [26, 27] with the purpose of distributing the computational burden between these two digital controllers. This solution offers better performance by reducing the sampling period, the ripples in the torque and the distortions in the stator current. However, the main limitations of this solution are the high cost and the complexity of circuit’s connections, which causes problems for commercialization. In order to overcome the limitations of the cited solutions, the FPGA can be used only for controlling the motor drives. Indeed, thanks to its hardware architecture, the FPGA offers good performance by reducing the execution time and consequently the delays in the retroaction loop. In the last few years, the DSP (DSPACE 1104) has been suggested and confirmed by several engineers and researchers for real time control of AC machines [24, 28, 29]. In the same context, the FPGA can overcome the software solution drawbacks by adopting parallel processing [30, 31, 32, 33]. In fact, the FPGA offers the designer the possibility of implementing in a low sampling period, control techniques with good performance and high algorithmic complexities. Indeed, in [32], the authors have implemented a control algorithm of an IM using an FPGA under a sampling period of 5 μs [32].

The second objective of this chapter consists in implementing the proposed SVM-DTC-IOFL on an FPGA board. For the hardware implementation on the FPGA, the SVM-DTC-IOFL must be transformed into VHDL or Verilog description languages. Indeed, VHDL or Verilog programming is a difficult task which raises the design time, the time to market and the system cost. In this chapter, a graphical programming method based on Xilinx System Generator (XSG) is utilized in order to reduce the prototyping time. In fact, the graphical architecture from the XSG under a Matlab/Simulink-tool makes it possible to generate the VHDL of the Verilog code, as well as the programming bitstream files [33, 34, 35]. The XSG is a toolbox created by the Xilinx engineers’ team, which operates between Matlab and Vivado tools, whose objective is to facilitate the programming tasks and reduce the time to market [35].

In this chapter, SVM-DTC-IOFL is theoretically developed, designed from the XSG tool, and verified by digital simulation utilizing a Xilinx Zynq FPGA.

This work is composed of five sections. In Section 2, the state mode of an induction motor drive, the SVM technique principle and the suggested IOFL theory are presented. In Section 3, designs from the XSG of the proposed SVM-DTC-IOFL and simulation results are shown. The implementation and synthesis results are given in Section 4. The conclusion is summarized in Section 5.

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2. Theory and modeling

In this chapter, a combination between the SVM technique, the DTC strategy and the IOFL technique is put forward. The SVM is suggested in order to prevent ripples and distortions, and it provides an operation with a fixed switching frequency. IOFL is used in order to achieve decoupled control between the torque and flux quantities. The principle of these techniques is detailed in the following subsections.

2.1 Model presentation

The IM model is presented as follows, which will be used to design the proposed IOFL approach.

ẋ=fx+gvsαβE1

with:

x=iiϕϕTE2
fx=1σ1Tr+1Tsiωmi+1σLsTrϕ+ωmσLsϕωmi1σ1Tr+1TsiωmσLsϕ+1σLsTrϕRsiRsiE3
g=1σLs01001σLs01E4

where:

ii:the stator current components,

vv:the voltage vectors components,

ϕϕ:the stator flux vector components,

RrRs: the rotor and stator resistance respectively,

LrLs: the rotor and stator inductance respectively,

TrTs: the rotor and stator time constants,

ωm(red/sec): the electric rotor speed.

σ=1Msr2LrLs: The Blondel coefficient, where Msr presents the mutual inductance.

2.2 Space vector modulation

The classical DTC based on fixed-bandwidth hysteresis controllers produces high ripples and distortions. Indeed, if a larger hysteresis-band of the torque is chosen, the torque ripples increase. For a smaller hysteresis band, the torque ripples are reduced and the switching frequency goes up, which consequently increases the commutation losses in the inverter IGBT transistors [36]. Thus, the SVM technique is proposed in this chapter in order to maintain a fixed switching frequency and reduce the ripples [37, 38]. The SVM principle consists in modulating reference voltage vector components in order to generate the more appropriate voltage vector that characterizes inverter control signals. As shown in Figure 1, the reference voltage vector can be determined by projecting it on the two vectors that bound the sector, using Eq. (5).

Figure 1.

Voltage vectors.

The time allowed for each voltage vector application can be determined by vector calculations. The rest of the sampling period can be filled by applying the null vector in order to grantee a fixed switching frequency [39, 40]. An example for the first section, by projection on vectors V1 and V2, the voltage vector application times T1 and T2 are given by Eq. (5):

VS=V+jV=T1TmV1+T2TmV2V1=23Udccos0+jsin0=23UdcV2=23Udccosπ3+jsinπ3Tm=T1+T2+T0T1=32V12VTmUdcT2=2VTmodUdcE5

where vv represents the components of the reference voltage vector, T1 and T2 denote the commutation time, Tm is the sampling time, and Udc is the DC voltage.

2.3 IOFL theory

This section illustrates the Feedback Linearization (FL) based DTC for an IM drive. The FL technique utilizes an inverse mathematical transformation in order to determine the desired control law for controlling the nonlinear system such as the IM. Furthermore, the FL technique is utilized to obtain decoupled control between the torque and flux. In this study, the suggested system outputs are the electromagnetic torque and the square root of the stator flux norm. Referring to the IOFL theory, the output variables are expressed as:

h1x=Tem=32Npiϕiϕh2x=ϕs2=ϕ2+ϕ2E6

where Tem is the estimated electromagnetic torque, and ϕs is the norm of the stator flux. Assuming the controller objectives y1 and y2 as, we get:

y1=h1xTem=TemTemy2=h2xϕs2=ϕs2ϕs2E7

where Tem and ϕs are the torque and flux references, respectively. Utilizing the presented equations, the time derivative of the controller objectives can be written as:

ẏ1ẏ2=g1xg2x+GxvvE8

with:

g1x=32Np1σ1Tr+1Tsϕi+ωmϕiωmσLsϕ2+1σ1Tr+1Tsϕi+ωmϕiωmσLsϕ2Temg2x=2Rsϕi2RsϕiϕsGx=2ϕ2ϕ32Npi1σLsϕ32Npi1σLsϕE9

Based on the IOFL technique, the control inputs can be expressed as follows [41].

vv=G1xg1x+v1g2x+v2E10

where v1 and v2 are assumed to be two auxiliary inputs with the purpose of ensuring more desired behavior and tracking accuracy for the torque and the stator flux, with:

v1=k1y1v2=k2y2E11

where k1 and k2 are positive constants. The SVM-DTC-IOFL performance strongly depends on the suitable choice of parameters k1 and k2. In fact, the high values of such parameters are able to cause the system instability. On the other hand, the small values will lead to a poor robustness and slow convergence. Finally, it is necessary to better choose such parameters for guarantying high control technique performance [13]. The combination between (8), (10) and (11) gives the following expression:

ẏ1ẏ2=k100k2y1y2E12

Utilizing the IM model, the relation between the rotor and the stator fluxes is given below:

ϕ=σLsLrMsr1σLsϕiϕ=σLsLrMsr1σLsϕiE13

Utilizing matrix G(x), defined in (9) and Eq. (13), the determinant of G(x) is given as follows:

Gx=3MsrσLsLrNpϕϕ+ϕϕE14

Referring to Eq. (14), it can be noticed that the product between the rotor flux and the stator flux cannot be zero, and matrix G(x) is nonsingular [42].

The FL control law is used in order to satisfy the stability condition defined by the Lyapunov approach. To study the stability of the control law, the Lyapunov function is given as:

V=12yTyE15

The time derivative of (15) is given as follows:

V̇=yTẏ=y1y2k100k2y1y2=k1y12k2y22<0E16

Parameters k1 and k2 are positive, so derivative V̇ is negative, which demonstrates the stability of the control system. The global diagram of the proposed SVM-DTC-IOFL is given by Figure 2.

Figure 2.

Global diagram of the proposed SVM-DTC-IOFL.

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3. Simulation results and discussion

In this section, the simulation studies of an IM controlled by two control strategies, named classical DTC and SVM-DTC-IOFL, have been carried out under a Matlab/Simulink environment. The hardware architecture of the two control strategies are designed using XSG tool. The different parameters of the IM model are provided in Table 1.

The XSG tool is developed by Xilinx to be integrated into a Matlab/Simulink environment. It is widely utilized for the design, verification and implementation of control algorithms architectures on FPGAs. When we get the desired design with good of simulation results, it will be possible for the XSG to automatically generate the VHDL code. As a matter of fact, the generated VHDL code will be used for generating the download. Bit file to be integrated into the FPGA. Figure 3 depicts the design flow through the use of the XSG. Figure 4 presents the SVM-DTC-IOFL architecture from the XSG.

Figure 3.

XSG design flow.

Figure 4.

Full architecture of SVM-DTC-IOFL using XSG.

3.1 First scenario

In this scenario, a comparative study between the classical DTC and the proposed SVM-DTC-IOFL is done under a rated load torque (10 Nm), a variable speed profile and a reversal of the direction of rotation. In order to show the effectiveness of the suggested SVM-DTC-IOFL, it is compared with the classical DTC in terms of torque ripples and stator current distortion. The performance analysis is carried out with a sampling period equal to 100 μs.

The IM starts with a reference speed equal to 100 rad/sec. At t = 1 sec the reference speed decreases slowly to reach −100 rad/sec at t = 2 sec. At t = 0.5 sec, a rated torque is applied.

Figure 5 presents the evolution of the rotor speed of the IM controlled by two control strategies. It can be noticed that the rotor speed converges to the reference speed for both control strategies. However, the proposed SVM-DTC-IOFL offers better performance in terms of ripples around the reference speed, as shown in Figure 5(b). As given in Figure 6(a), the suggested control strategy gives better performance in terms of ripples compared to the classical DTC (Figure 6(b)). Figure 7 presents the three phase stator current consumed by the IM control by both control strategies. It can be seen that the proposed control strategy offers better performance in terms current distortions. In fact, for the suggested SVM-DTC-IOFL, the stator current has a smooth waveform (Figure 7(a)). Figure 8 presents the evolution of the stator flux components for both control strategies. In can be seen that the real stator flux converges to its reference value. In addition, the proposed control strategy gives better performance in terms of flux-ripple reduction. More details are illustrated in Table 2.

Figure 5.

Speed response for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

Figure 6.

Torque response for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

Figure 7.

Three phase stator current for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

Figure 8.

Three phase stator current for: (a) suggested SVM-DTC-IOFL, (b) classical DTC.

ParameterValueParameterValue
power (kW)1.5Rotor resistance (Ω)4.282
Voltage (V)230/400Stator inductance (H)0.464
Frequency (Hz)50Rotor inductance (H)0.464
Pole pair2Mutual inductance (H)0.4417
Stator resistance (Ω)5.717Rated speed (rpm)1435

Table 1.

Induction machine parameters.

Classical DTCProposed SVM-DTC-IOFL
Speed ripplesMediumneglected
Torque ripples (%)40%20%
Current distortionHighMedium
Sampling period100 μs100 μs

Table 2.

Comparison between the both control strategies.

3.2 Second scenario

In this scenario we used the same simulation conditions of the first scenario, but the main deference consists in reducing the sampling period which is equal to 10 μs. In fact, when the control algorithm is implemented on software solutions like the microcontrollers or the DSP, the sampling time increased due to the serial processing of these solutions, which consequently raises the control loop delay, the torque ripples and the stator current distortions. In order to overcome the limitations of these solutions in terms of execution time, the FPGA is proposed thanks to its parallel processing and short execution time. In order to show the effects of the execution time on the simulation results, a sampling period of 10 μs is chosen. The obtained results in this scenario demonstrate that when the sampling period decreases, the torque and the stator flux ripples, as well as the stator current harmonics, are reduced, as shown in Tables 2 and 3.

Classical DTCProposed SVM-DTC-IOFL
Speed ripplesMediumneglected
Torque ripples (%)10%5%
Flux ripples (%)4.39%1.09%
Current distortionHighneagleted
Sampling period10 μs10 μs

Table 3.

Comparison between the both control strategies.

The IM starts with a reference speed equal to 100 rad/sec. At t = 1 sec, the reference speed falls slowly to reach −100 rad/sec at t = 2 sec. At t = 0.5 sec, a rated torque is applied.

Figure 9 depicts the evolution of the rotor speed of the IM controlled by two control strategies. It can be noticed that the rotor speed converges to the reference speed for both control strategies. However, the suggested SVM-DTC-IOFL offers better performance in terms of ripples around the reference speed, as shown in Figure 9(b). As given by Figure 10(a), the proposed control strategy provides better performance in terms of ripples compared to the classical DTC (Figure 10(b)). Figure 11 presents the three phase stator current consumed by the IM control by both control strategies. It can be seen that the suggested control strategy offers better performance in terms current distortions. In fact, for the proposed SVM-DTC-IOFL, the stator current has a smooth waveform (Figure 11(a)). Figure 12 presents the evolution of the extremity of the stator flux vector in the Concordia reference. It can be noticed that when the motor is controlled by the classical DTC, the stator flux vector trajectory presents high deviations and ripples (as shown by Figure 12(b)). Contrariwise, in the case of the proposed SVM-DTC-IOFL a smooth circular trajectory is obtained as illustrated in Figure 12(a). More details are given in Table 3.

Figure 9.

Speed response for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

Figure 10.

Torque response for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

Figure 11.

Three phase stator current for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

Figure 12.

Three phase stator flux for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

3.3 Third scenario

This section consists in testing the robustness of the proposed SVM-DTC-IOFL under stator resistance variations at a low speed region. In this study, the IM starts with a reference speed equal to 20 rad/sec. The sampling period is equal to 10 μs. At t = 4 sec, the stator resistance increases to reach 1.5 Rsn. Figure 13(a, b), presents the evolution of the rotor speed for both control strategies. As shown in Figure 13(a), it can be seen that the suggested SVM-DTC-IOFL offers better performance with a small deviation when the stator resistance goes up.

Figure 13.

Speed response for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

Figure 14(a, b) illustrates the evolution of the stator flux module for both control strategies. Referring to Figure 14(a), it can be noticed that when the stator resistance rises, the stator flux curve presents small deviations and then it converges quickly to its reference value. However, when the IM is controlled by the classical DTC, the actual stator flux diverges from its reference value due to the variation in the stator resistance.

Figure 14.

Speed response for: (a) proposed SVM-DTC-IOFL, (b) classical DTC.

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4. VHDL code generation and synthesize results

The VHDL code generation and synthesis steps can be validated after verifying the functionality of the XSG architecture of the proposed SVM-DTC-IOFL. The obtained simulation results of the section confirm the good functionality of the designed XSG architecture, which offers the possibility to generate the VHDL and determine the synthesis results utilizing the Xilinx Vivado. During the hardware implementation of the classical DTC and the proposed SVM-DTC-IOFL approaches, the used resources from the FPGA are depicted in Table 4.

Used with SVM-DTC-IOFLAvailable
LUT1436 (2.7%)53,200
LUTRAM104 (0.59%)17,400
FF2826 (2.65%)106,400
BUFG1 (3.12%)32
DSP10 (4%)220

Table 4.

Utilized resources from Xilinx Zynq FPGA.

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5. Conclusion

In this chapter, a performance improvement of the DTC of an IM drive utilizing the SVM technique and a nonlinear control technique named IOFL has been presented. In order to solve the classical DTC problems, like the torque ripples, the current distortion and the variation in the switching frequency, the SVM has been developed in this chapter. The proposed scheme is known as SVM-DTC. To increase the robustness of the suggested scheme under parameter variations, an IOFL approach has been combined with the SVM-DTC to generate the reference voltage vector. The real time implementation on the Xilinx Zynq FPGA has been put forward and investigated in this chapter so as to reduce the period of the system and eliminate the time delay in the control loop. The design of the proposed scheme has been carried out using the XSG toolbox. The flux and torque ripples have been considerably reduced thanks to the SVM technique. The nonlinear approach has given more performance, such as the robustness against the parameter variations, good and fast dynamic response and good tracking, and has reduced the complexity of the control scheme. Furthermore, the designed architecture of the control algorithm has been tested with two different sampling periods in order to demonstrate that if the sampling period rises, the ripples increase. Moreover, this controller has been featured by its simple design and implementation. The hardware FPGA implementation of the proposed SVM-DTC-IOFL can be considered as a good solution to control electrical motor drives.

For future work we are interested in the experimental validation of the proposed DTC-SVM-IOFL utilizing a real test bench.

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Conflict of interest

The authors declare no conflict of interest.

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Written By

Saber Krim and Mohamed Faouzi Mimouni

Submitted: 04 February 2022 Reviewed: 23 March 2022 Published: 04 July 2022