Open access peer-reviewed chapter

Fast Algorithm Designs of Multiple-Mode Discrete Integer Transforms with Cost-Effective and Hardware-Sharing Architectures for Multistandard Video Coding Applications

Written By

Chih-Peng Fan

Submitted: March 9th, 2016 Reviewed: July 21st, 2016 Published: November 23rd, 2016

DOI: 10.5772/64985

Chapter metrics overview

1,535 Chapter Downloads

View Full Metrics

Abstract

In this chapter, first we give a brief view of transform-based video coding. Second, the basic matrix decomposition scheme for fast algorithm and hardware-sharing-based integer transform design are described. Finally, two case studies for fast algorithm and hardware-sharing-based architecture designs of discrete integer transforms are presented, where one is for the single-standard multiple-mode video transform-coding application, and the other is for the multiple-standard multiple-mode video transform-coding application.

Keywords

  • video coding
  • transform coding
  • fast algorithm
  • matrix factorization
  • hardware sharing
  • multiple modes
  • multiple standards

1. Introduction

Video-coding system has generally utilized block-based transform-coding skills to shrink the data rates by joining quantization and entropy coding. Among some block-based transforms, the discrete cosine transform (DCT) [1] and integer transforms have extensively been used to still image and video-coding specifications, such as JPEG [2], MPEG-1/2 [3, 4], MPEG-4 [5], H.264/AVC [6, 7], AVS [8, 9], VC-1 [10], VP8 [11], and HEVC [12]. Because integer transforms perform the low complexity and effective coding performance, the advanced video coding (AVC) in ITU-T H.264 [6, 7, 13, 14], which is also known as MPEG-4 part 10, applies integer transforms for transform process. The 4 × 4 and 8 × 8 transforms in [13, 14] were calculated exactly to prevent non-adaptation issues of inverse transforms for high-quality moving visual images. The VC-1 specification [10, 15, 16] employed 4 × 4 and 8 × 8 integer transforms, and it was developed by Microsoft Corporation and standardized by the Society of Motion Picture and Television Engineers (SMPTE). The 8 × 8 integer transform is utilized to obtain the high-coding performance in the Audio Video Coding Standard (AVS) for China [8, 9]. In [11], the VP8 video-coding standard was developed for Internet browser applications. The Joint Collaborative Team on Video Coding proposed the high-efficiency video coding (HEVC) specification [12]. By HEVC, the compression efficiency was greatly better than that achieved using the H.264/AVC high-profile-coding specification.

To support the single-standard H.264/AVC video coding, several transform architectures in [1724] have been developed to approach the multiple transform modes in H.264. To support the single-standard H.265/HEVC video coding, several transform architectures in [2532] have been developed to approach the multiple transform modes in HEVC. Besides, supporting multiple-standard functions in video coding has been an important issue in multimedia applications recently, such as H.264/AVC, MPEG-1/2/4, VC-1, AVS, and VP8 standards, and several transform architectures in [3341] have also been developed to complete the multiple transform functions. Owing to the growth of multistandard video-coding applications, how to achieve low-computational complexities and implement by hardware-sharing-based cost-effective architectures simultaneously are interesting research topics for the VLSI design of video codecs.

Advertisement

2. Matrix decomposition preprocessing for fast algorithm and hardware-sharing-based designs

Based on the resemblance property, the 8 × 8 inverse integer transforms [41] in H.264/AVC, AVS, VC-1, VP8, MPEG-1/2/4, and HEVC specifications are revealed in Eq. (1), and Table 1 depicts the coefficient values in the transforms.

C8×8=[abfcadgeacgeabfdadgbaefcaefdacgbaefdacgbadgbaefcacgeabfdabfcadge]E1
Transform sizesVC-1AVSVP8MPEG-1/2/4H.264/AVCHEVC
4 × 4N/A
8 × 8N/A
16 × 16N/AN/AN/AN/AN/A
32 × 32N/AN/AN/AN/AN/A

Table 1.

The transform modes in several video-coding standards [41].

In Eq. (1), it is decomposed by Eq. (2) as

C8×8=P1A0Pr.E2

In Eq. (2), A0 is divided into two modules, U4 × 4 and D4 × 4, where P1=[1000000101000010001001000001100000011000001001000100001010000001], Pr=[1000000000100000000010000000001001000000000100000000010000000001], A0=[afag0000agaf0000agaf0000afag00000000edcb0000dbec0000cebd0000bcde].

Thus

A0=U4×4D4×4E3

and C8×8 becomes

C8×8=P1(U4×4D4×4)Pr.E4

In (3), “⊕ “ is the direct sum operator, and the two diagonal blocks U4 × 4 and D4 × 4 are processing in parallel. To cut down the computational operations and achieve effective hardware shares, the upper diagonal matrix U4 × 4 and the down diagonal matrix D4 × 4 are further decomposed into the cascaded multiplication form or the addition form of sparse matrices. After matrix factorizations, the chosen sparse matrices have the coefficients which are 1, −1, 0, or an integer, and an integer value can equal the combination of powers of two. Besides, zero factors in the chosen sparse matrices could be factorized as many as possible [42].

By Eq. (1), for VC-1 the values of the coefficient set {a, b, c, d, e, f, g} are {12, 16, 15, 9, 4, 16, 6}, and those for AVS are {8, 10, 9, 6, 2, 10, 4}. Next, those for MPEG-1/2/4 are {362, 502, 426, 284, 100, 473, 196}, and those for H.264/AVC are {8, 12, 10, 6, 3, 8, 4}. Finally, those for HEVC are {64, 89, 75, 50, 18, 83, 36}.

The general 4 × 4 inverse integer transform matrices [41] can be presented in Eq. (5) as

M4×4=[hihjhjhihjhihihj].E5

By Eq. (5), for VC-1 the values of the coefficient set {h, i, j} are {17, 22, 10}, and those for VP8 are {128, 167, 70}. Next, those for AVS-M are {2, 3, 1}, and those for H.264/AVC are {1, 1, 0.5}. Finally, those for HEVC are {64, 83, 36}.

Advertisement

3. Case study [32]: single-standard multiple-mode transform design

3.1. Hardware-sharing based 32 × 32 integer core transform for HEVC

The one-dimensional (1D) 32 × 32 inverse core transform for HEVC is described in [30]. By the symmetrical property, the 32 × 32 inverse core transform is presented as

Hi32=PACA1,E6

where CA1=[C11C12C21C22], PA=[I16x16I˜16x16I˜16x16I16x16], I˜16x16=[000100010001001000], and I16×16 is a 16 × 16 identity matrix. In Eq. (6), PAis the butterfly-like postprocessing, and CA1 is the sparse matrix. By swapping each column of CA1, it becomes

CA1=CA2PAr.E7

By Eqs. (6) and (7), Hi32 becomes

Hi32=PACA2PAr,E8

where PAr is the permutation matrix. In Eq. (7), CA2 is expressed by

CA2=[TA11016x16016x16TA22]=TA11TA22,E9

where “⊕” means the direct sum operation, and then TA11 and TA22 are 16 × 16 matrices, which are revealed in [32]. The matrix PAr in Eq. (8) is expressed as

 PAr=P(2,16),E10

where the permutation matrix P(m, n) is defined in [43], and the notation “⊗” means the Kronecker product. In Eq. (9), AA22 is presented as

TA22 = TM1+ TN1,E11

First, the lower half of CN1 is divided into sixteen 8 × 1 column vectors Xi, where i= 0, 1, 2, …, 15, and then TN1 becomes

TN1=[08 16X0X1X15].E12

Second, the coefficients in a single column vector can be shared. The vector coefficient computations are achieved by integrating several base coefficients [32]. After realizing the column vectors of TN1, the lower half of TN1 is factorized as an integration of eight 1 × 16 row vectors depicted as Yi, where i= 8, 9, …, and 15, and TN1 becomes

TN1 =[08x16Y8Y9Y15].E13

Adder tree structures are utilized to calculate the aggregate results for the row vectors Y8Y15 [32]. By the duplicate operations for TN1, TM1 is presented as

TM1=[X^0X^1508x16],E14

where X^iis an 8 × 1 column vector, where i= 0, 1, 2, …, and 15. Then, TM1 becomes

TM1=[Y0Y708x16],,E15

where Yiis a 16 × 1 row vector, where i= 0, 1, …, and 7. The realization of TM1 equals that of TN1. Finally, the operations of TM1 and TN1 are merged to TA22. The computational operations TA22 require 630 additions and 326 shift operations [32]. The matrix TA11 in Eq. (9), which is also denoted as Hi16, is the 1D 16 × 16 inverse core transform in HEVC [30].

3.2. Hardware-sharing-based 16 × 16 integer core transform for HEVC

The 16 × 16 integer core transform in [30] changes into

Hi16=PBCB1,E16

where PB= [I8x8I˜8x8I˜8x8I8x8], and CB1 is revealed in [32]. By swapping each column of CB1, it will be

CB1=CB2PBr,E17

where PBr = P(8,2). By Eqs. (16) and (17), Hi16 is expressed by

Hi16= TA11=PBCB2PBr.E18

In Eq. (18), CB2 is presented as

CB2=[TB1108x808x8TB22]=TB11TB22,E19

and TB22 becomes

TB22 = TM2 + TN2,E20

where  TM2=[9 2543 5770 8087 9025 7090 8043 9 578743 905725 8770 9 8057 80 2590 9 874370 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0],
     TN2=[ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 070 43 87 99025 80 5780 9 70 87 255790438757 9 43 80 90 70 2590878070574325 9].

By the duplicate processed of TN1 in Section 3.1, TN2 turns into

TN2=[04x8U0U7],E21

where Uiis an 8 × 1 column vector, where i= 0, 1, 2, …, and 7. Next, TN2 also is

TN2=[04x8V4V7],E22

where Viis a 1 × 8 row vector, where i= 4, 5, 6, and 7. Adder tree schemes are applied to compute the summed outcomes of V4V7 [32]. By the same processes of TM1 in Section 3.1, TM2 becomes

TM2=[U^0U^704x8],E23

where U^iis a 4 × 1 column vector, where i= 0, 1, 2, …, and 7. Next, TM2 also is

TM2=[V0V304x8],E24

where Viis a 1 × 8 row vector, where i= 0, 1, 2, and 3. Then, adder trees are used to treat the row vectors V0V3 [32]. Finally, the calculations of TM2 and TN2 are merged to TB22. The computational operations of TB22 are 164 additions and 106 shift operations [32]. Meantime, the TB11 in Eq. (19), which is also denoted as Hi8, is the 1D 8 × 8 inverse core transform in HEVC [30].

3.3. Hardware-sharing-based 8 × 8 integer core transform for HEVC

The 8 × 8 integer transform in [30] is described as

Hi8=PCCC1,E25

where PC= [I4x4I˜4x4I˜4x4I4x4], and CC1=[640 830 640 360640 360640830640360640 830640830 6403600180 500750 890500 890180750750 180 890 50089075050018]. After swapping each column in CC1, it changes into

CC8=CC2PCr,E26

where PCr=[1000000000100000000010000000001001000000000100000000010000000001]. Based on Eqs. (25) and (26), Hi8 is presented by

Hi8=TB11=PCCC2PCr,E27

In Eq. (27), CC2 becomes

CC2=[TC1104x404x4TC22]=TC11TC22,E28

where TC11=[64 83 64 3664 366483643664 836483 6436]and TC22=[18 5075 8950 89187575 18 89 5089755018].

In Eq. (28), TC22 is factorized as

TC22 = S1+ S2,E29

where S1=[1800 89089180018 890890018]. Moreover, S1 is expressed by

S1=Z1+(18Z2),E30

where Z1=[0001010000101000]and Z2=[10 0 5 051 0 01 5 050 01]. In Eq. (29), S2 is presented as

S2=25Z3,E31

where Z3=[0 23 02003300 2032 0]. By Eqs. (29)– (31), TC22 becomes

TC22=Z1+(18Z2)+(25Z3).E32

In Eq. (32), the computations of TC22 require 36 additions and 28 shift operations [32]. The matrix TC11 in Eq. (28) is also the 1D 4 × 4 inverse core transform matrix in HEVC.

3.4. Hardware-sharing-based 4 × 4 integer core transform for HEVC

The 4 × 4 integer core transform matrix is indicated as

Hi4=PDCD1,E33

where PD=[10 1 001 0 101 01101 0]and CD1=[640 6406406400360 83083036]. By swapping each column of CD1, it changes into

CD1=CD2PD2.E34

where PDr=[1000001001000001]. From Eqs. (33) and (34), Hi4 is described by

Hi4=TC11=PDCD2.PDr.E35

In Eq. (34), CD2 is rewritten as

CD2=TD11TD22.E36

In Eq. (36), TD11 becomes

TD11=64Z4,E37

where Z4=[1 111]. In Eq. (36), TD22 is indicated by Z5 and Z6 as

TD22=36Z5+11Z6,E38

where Z5=[2 112]and Z6=[1 001]. Thus, the computations of TD22 are 10 additions and 10 shift operations [32]. Based on Eqs. (35)– (38), Hi4 is changed into

Hi4=PD[(64Z4)(36Z5+11Z6)]PDr.E39

By the abovementioned discussions, the hardware modules of 4 × 4, 8 × 8, and 16 × 16 inverse core transforms are shared to implement Hi8, Hi16, and Hi32, respectively [32]. By sharing the hardware of Hi4 in Eq. (39), the cost-effective design of the 8 × 8, 16 × 16, and 32 × 32 inverse core transforms is obtained progressively. First, the hardware-sharing-based eight-point inverse transform is presented as

Hi8=PC{Hi4[Z1+(18Z2)+(25Z3)]}PCr.E40

Next, the hardware-sharing-based 16-point inverse transform is described as

Hi16=PB{Hi8[TM2+TN2]}PBr.E41

Finally, the hardware-sharing-based 32-point inverse transform is depicted as

Hi32=PA{Hi16[TM1+TN1]}PAr.E42

In this section, the hardware-sharing transform architecture cuts down the hardware cost because the same submodules and coefficients of the transforms are extracted to be shared. Figure 1 illustrates the architecture of the hardware-sharing-based inverse core transform design for 4 × 4/8 × 8/16 × 16/32 × 32 transforms [32].

3.5. Architecture comparison

The proposed 1D inverse core transform in [32] involves four inputs to sustain 4 × 4, 8 × 8, 16 × 16, and 32 × 32 transform modes. Several multiplexers are utilized to acquire the transform outputs of the 32 × 32 inverse core transform by the shared design of 4 × 4, 8 × 8, and 16 × 16 inverse core transforms [32]. Table 2 lists the number of adders and shifters needed to calculate four modes of the 1D inverse core transform for HEVC. The developed architecture in [32] does not require any multiplier, and the fixed-coefficient multiplications are replaced with simple additions and shift operations. Table 3 shows the comparison of three 16-point inverse transform designs. Compared with the previous works in [29] and [31], the applied architecture contains fewer adders. However, several more shifters are required. Compared with the cost of adders, the shifters need lower hardware expense. Thus, the used architecture decreases the hardware cost more efficiently than previous transform schemes do.

Figure 1.

The hardware-sharing-based inverse core transform structure for HEVC.

Transform sizes32 × 3216 × 168 × 84 × 4
No. of shifters256934011
No. of adders4611466410

Table 2.

The 1D inverse transform architecture at different transform modes [32].

DesignsNo. of shiftersNo. of adders
Ahmed [29]132232
Haggag [31]58242
Design in Section 3.293146

Table 3.

Hardware comparison of three 1D 16-point transform designs [32].

Advertisement

4. Case study [41]: multiple-standard multiple-mode transform design

4.1. Hardware-sharing design for 8 × 8 transforms mode

For H.264/AVC, the transform matrix is employed as a foundation matrix for the multistandard hardware-sharing scheme. Based on Eq. (3), the cost of the upper diagonal matrix in Eq. (43) is eight adders and two shifters.

U4×4_AVC=[8884848884888884]=8C1C2,E43

where C1=[1001011001101001], and C2=[101000.50110100100.5]. For AVS, the upper diagonal matrix U4×4_AVS in Eq. (44) costs 10 adders and four shifters.

U4×4_AVS=[81084848108481081084]=8C1(C2+C3),E44

where C3=[00000000.25000000.2500]. In Eq. (45), the upper diagonal matrix U4×4_VC1 for VC1 needs 14 adders and eight shifters.

U4×4_VC1=|1216126126121612612161216126|=8C1(C4+C5C2),E45

where and  C4=[00000000.5000000.500], and C5=[1.500001.500001.500001.5]. For HEVC, the 8 × 8 transform matrix is acquired by the AVS design in Eq. (44), and the design in Eq. (46) costs 16 adders and 12 shifters.

U4×4HEVC=[64836436643664836436648364836436]=2C1[32(C2+C3)U1],E46

where U1=[00000201.5000001.502]. For MPEG-1/2/4, the upper diagonal matrix is factorized by

U4×4_MPEG=[362473362196362196362473362196362473362473362196]=C1[256(C4+C5C2)(U2+U3)],E47

where U2=[22022000002202200000],and U3=[000004039000003904]. In Eq. (47), the parameter “22” of U2 is implemented by (C5 · C5 ≪ 4) – (C1 ≪ 1), where “≪1” is left shifting one bit, and the cost in Eq. (47) requires 28 adders and 26 shifters.

By Eq. (3), on the other side, the down diagonal matrix D4×4_AVC for H.264/AVC becomes Eq. (48), and it needs 17 adders and eight shifters.

D4×4_AVC=[361012612310103126121063]=8U4(D4+D5)(D2+U3),E48

where  U4=[1000010000100001], D4=[1110101111010111], D5=[0.5000000.5000.5000000.5], D2=[0.2500000.2500000.2500000.25], U3=[0001001001001000].

For AVS, the D4×4_AVS matrix becomes (49), and D4 and D5 are shared with the design in Eq. (48), and then U3 and U4 are also partially shared with the scheme in Eq. (48). In Eq. (49), it costs 24 adders and 12 shifters

D4×4_AVS=[26910610299210610962]=4U4(D4+D5)D3(D1+U3),E49

where U3=[0100000110000010], D3=[1000010000100001], and  D1=[1.500001.500001.500001.5].

For VC-1, the D4×4_VC1 matrix is factorized by Eq. (50), and the design requires 21 adders and 12 shifters

D4×4_VC1=[491516916415154169161594]=8U4(D4D6+D5)(D2+U3),E50

where D6=[1.500001.500001.500001.5]. For HEVC, the D4×4_HEVC matrix is expressed by Eq. (51), and it expends 44 adders and 20 shifters

D4×4_HEVC=[18507589508918757518895089755018]=D4×4_AVS9+[4(U5D1+U6)U7],E51

where  U5=[0010000110000100], U6=[0100100000010010], U7=[0001010000101000]. For MPEG-1/2/4, based on D4×4_AVS, the D4×4_MPEG matrix is presented by Eq. (52), and the design costs 48 adders and 32 shifters

D4×4_MPEG=[100284426502284502100426426100502284502426284100]=D4×4_AVS50+[16(U5D1+U6)+2U7].E52

4.2. Hardware-sharing design for 4 × 4 transforms mode

For AVS-M, the matrix M4×4_AVS is presented by (53), and it spends 10 adders and six shifters

M4×4_AVS=[2321212321232321]=C1(2C2+U8),E53

where U8=[0000000100000100]. For VC-1, M4×4_VC1 is expressed by Eq. (54), and the design requires 14 adders and 12 shifters

M4×4_VC1=[17221710171017221710172217221710]=C1(16C2+U9),E54

where  U9=[1010020610100602]. For VP8, all coefficients in 4 × 4 transform matrix are multiplied by 128 to get integer values, and it costs 18 adders and 14 shifters

M4×4_VP8=[12816712870128701281671287012816712816712870]=C1(128C2+U10),E55

where U10=[000006039000003906]. The matrix U4×4_AVC/8 equals the 4 × 4 inverse transform matrix in H.264/AVC. In addition, the matrix U4×4_HEVC equals the 4 × 4 inverse transform matrix in HEVC. Thus, several multiplexers are used to share the hardware between the submatrices to decrease hardware cost.

4.3. Architecture comparison

The applied hardware-sharing-based 1D multistandard inverse integer transform scheme has two inputs, which sustain 4 × 4 and 8 × 8 transform modes. The hardware blocks of processing the 4 × 4 inverse transforms are shared with that of the upper diagonal matrix U8×8. Thus, several multiplexers are utilized for U8×8 to compute the 4 × 4 inverse transforms without additional operations. For the multistandard applications, the hardware-sharing architecture of the fast 1D 4 × 4 and 8 × 8 inverse integer transforms is illustrated in [41]. The shifters are also realized by wiring. Compared with the individual designs without hardware shares, Table 4 depicts that the used scheme in [41] decreases the number of shifters and adders by 50 and 75%, respectively.

Different 1D inverse integer transform modesNo. of addersNo. of shifters
Individual designs without hardware shares336180
Hardware-sharing-based design in Section 48290
Reduction of cost75%50%

Table 4.

Hardware comparison between two architectures [41].

To implement the discussed architecture, a cell-based VLSI design flow is utilized to design, simulate, and verify the cost-effective hardware-sharing architecture. For fair comparisons among different transform structures, the normalized mode gain, which is required to normalize the gate counts, is described as follows: By matrix dimensions and without missing generality [40], the normalized mode gains defined for the 32 × 32, 16 × 16, 8 × 8, and 4 × 4 inverse integer transform matrices are 16, 4, 1, and 1/4, respectively.

The hardware-sharing-based design in Section 3 supports 4 × 4, 8 × 8, 16 × 16, and 32 × 32 inverse transform modes for HEVC. Thus, the normalized mode gain of the design is 21.25 (i.e., 16 + 4 + 1 + 0.25). Similarly, five 8 × 8 and five 4 × 4 inverse transform functions are provided by the hardware-shared design in Section 4. Therefore, the normalized mode gain is assigned by 6.25 (i.e., 5 + 1.25) [41]. Afterwards, the normalized gate counts are defined by [40, 41]

Normalized gate counts = Gate countsNormalized mode gain.E56

Table 5 shows the hardware cost comparisons among different 1D multiple transform architectures, which includes single-standard multiple-mode [32] and multiple-standard multiple-mode [41] transform designs.

ArchitectureAhmed et al. [29]Hardware-sharing based-design in Section 3Shen et. al.
[26]
Martuza
et. al. [28]
Qi et al. [36]Wang
et al. [38]
Hardware-sharing-based design in Section 4
Gate counts144.8K115.7 K134.8 K39.4 K18 K23.06 K27.4 K
Normalized mode gain21.2521.2525.7553.54.56.25
Normalized gate counts6.81 K5.44 K5.23 K7.88 K5.14 K5.12 K4.38 K
Supporting modesSingle-standard
Multiple-mode
Single-standard
Multiple-mode
Multiple-
standard
Multiple-
mode
Multiple-standard
Multiple-mode
Multiple-standard
Multiple-
mode
Multiple-
standard
Multiple-
mode
Multiple-standard
Multiple-mode
Supporting standards/TransformsHEVC:
4 × 4, 8 × 8, 16 × 16, 32
× 32 modes
HEVC:
4 × 4, 8 ×
8, 16 × 16, 32
× 32 modes
H.264/AVC,
VC-1:
4 × 4,8 × 8
modes
MPEG-1/2/4, AVS: 8 × 8
mode;
HEVC: 4 × 4,
8 × 8, 16 × 16,
32 × 32 modes
H.264/AVC,
VC-1,
AVS, HEVC:
4 × 4, 8 × 8 modes
H.264/AVC,
VC-1:
4 × 4, 8 × 8 modes;
MPEG-1/2/4:
8 × 8 mode
H.264/AVC;,
VC-1:
4 × 4,
8 × 8
modes;
MPEG-1/2/4,AVS:
8 × 8 mode
H.264/AVC,
VC-1, HEVC:
4 × 4, 8 × 8 modes;
MPEG-1/2/4, AVS: 8 × 8 mode;
VP8, AVS-M: 4 × 4 mode

Table 5.

Hardware cost comparisons among different 1D multiple transform architectures [32, 41].

Advertisement

5. Conclusion

For the single-standard multiple-mode transform design, this chapter discussed the 4 × 4, 8 × 8, 16 × 16, and 32 × 32 inverse core transforms in HEVC with a cost-effective and hardware-efficient design. By the symmetrical characteristics of the elements, the core transform matrices were factorized into several submatrices. Thus, the hardware of the (N/2) × (N/2) inverse core transform was shared with that of the N× Ninverse core transform for N= 32, 16, and 8. Compared with the direct design without hardware shares, the applied transform scheme in Section 3 decreased the hardware cost of adders and shifters by 32 and 36%, respectively. Besides, for VLSI implementation, the design in Section 3 requires less normalized gate counts than the design does in [29].

For the multiple-standard multiple-mode transform design, this chapter also discussed the fast algorithm and hardware-sharing-based design of 4 × 4 and/or 8 × 8 inverse transforms among H.264/AVC, VC-1, HEVC, MPEG-1/2/4, AVS, and VP8 for multistandard video decoders. By only shifters and adders, the decomposition scheme of matrices was used to develop the hardware-shared scheme. The used structure in Section 4 decreased the number of shifters and adders by 50 and 75% more than the individual fast algorithm-based implementation did. Besides, for VLSI implementation, the design in Section 4 requires less normalized gate counts than the designs do in [26, 28, 36, 38].

Advertisement

Acknowledgments

This work was supported by Ministry of Science and Technology, Taiwan, R.O.C. under Grant MOST 105-2221-E-005-078.

References

  1. 1. J. R. Rao and P. Yip, Discrete Cosine Transform: Algorithms, Advantage, Applications, New York, NY: Academic, 1990.
  2. 2. ISO/IEC JTC 1/SC 29/WG 1—Coding of Still Pictures, 2009.
  3. 3. ISO/IEC 11172-2 MPEG-1 Video Coding Standard, Information Technology—Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1,5 Mbit/s – Part 2: Video, 1993.
  4. 4. ISO/IEC 13818-2 MPEG-2 Video Coding Standard, Information Technology—Generic Coding of Moving Pictures and Associated Audio Information: Video, 1995.
  5. 5. ISO/IEC 14496-2 MPEG-4 Video Coding Standard, Information Technology—Coding of Audio-Visual Objects – Part 2: Visual, 2004.
  6. 6. T. Wiegand and G. Sullivan, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, (ITU-T rec. H.264/ISO/IEC 14496-10 AVC, presented at Joint Video Team (JVC) of ISO/IEC MPEG and ITU-T VCEG), 2003.
  7. 7. Iain E. G. Richardson, H.264 and MPEG-4 Video Compression—Video Coding for Next-generation Multimedia, John Wiley & Sons, 111 River Street, Hoboken NJ07030-5774, New Jersey, United States, 2003.
  8. 8. W. Gao, C. Reader, F. Wu, Y. He, L. Yu, H. Lu, S. Yang, T. Huang, and X. Pan, AVS—The Chinese Next-Generation Video Coding Standard, National Association of Broadcasters (NAB) Conference, 2004.
  9. 9. L. Yu, S. Chen, and J. Wang, Overview of AVS video coding standards, Signal Processing: Image Communication, vol. 24, issue 4, pp. 247–262, April 2009.
  10. 10. SMPTE, Standard for Television: VC-1 Compressed Video Bitstream Format and Decoding Process, SMPTE 421M-2006.
  11. 11. J. Bankoski, P. Wilkins, and Y. Xu, Technical overview of VP8, an open source video codec for the web, IEEE International Conference on Multimedia and Expo (ICME), pp. 1–6, July 11–15, 2011.
  12. 12. M. T. Pourazad, C. Doutre, M. Azimi, and P. Nasiopoulos, HEVC: the new gold standard for video compression: How does HEVC compare with H.264/AVC ?, IEEE Consumer Electronics Magazine, vol. 1, pp. 36–46, July 2012.
  13. 13. H. S. Malvar, A. Hallapuro, M. Karczewicz, and L. Kerofsky, Low-complexity transform and quantization in H.264/AVC, IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 598–603, July 2003.
  14. 14. S. Gordon, D. Marple, and T. Wiegand, Simplified use of 8x8 transforms—updated proposal and results, JVT-K028, 11th Meeting, Munich, Germany, March 2004.
  15. 15. S. Srinivasan, P. Hsu, T. Holcomb, K. Mukerjee, S. L. Regunathan, B. Lin, J. Liang, M. C. Lee, and J. Ribas-Corbera, Windows media video 9: overview and applications, Signal Processing: Image Communication, vol. 19, issue 9, pp. 851–875, October 2004.
  16. 16. S. Srinivasan and S. L. Regunathan, An overview of VC-1, Proceedings of the SPIE, Visual Communications and Image Processing (VCIP), Beijing, China, vol. 5960, pp. 720–728, July 2005.
  17. 17. T. C. Wang, Y. W. Huang, H. C. Fang, and L. G. Chen, Parallel 4x4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264, IEEE International Symposium on Circuits and Systems, vol. 2, pp. 800–803, 2003.
  18. 18. Z. Y. Cheng, C. H. Chen, B. D. Liu, and J. F. Yang, High throughput 2-D transform architectures for H.264 advanced video coders, IEEE Asia-Pacific Conference on Circuits and Systems, pp. 1141–1144, December 2004.
  19. 19. K. H. Chen, J. I. Guo, and J. S. Wang, A high-performance direct 2-D transform coding IP design for MPEG-4 AVC/H.264, IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 4, pp. 472–483, April 2006.
  20. 20. G. A. Su and C. P. Fan, Cost effective hardware sharing architecture for fast 1-D 8x8 forward and inverse integer transforms of H.264/AVC high profile, IEEE Asia Pacific Conference on Circuits and Systems, pp. 1332–1335, November 2008.
  21. 21. T. T. T. Do and T. M. Le, High throughput area-efficient SoC-based forward/inverse integer transform for H.264/AVC, IEEE International Symposium on Circuits and Systems, pp. 4113–4116, May 2010.
  22. 22. W. Hwangbo and C. M. Kyung, A multi-transform architecture for H.264/AVC high-profile coders, IEEE Transactions on Multimedia, vol. 12, no. 3, pp. 157–167, April 2010.
  23. 23. M. L. Hsia and Oscal T. C. Chen, Low-complexity inverse integer transform in H.264/AVC, IEEE International Conference on Multimedia & Expo, pp. 826–830, July 2010.
  24. 24. M. Nadeem, S. Wong, and G. Kuzmanov, Inverse integer transform in H.264/AVC intra-frame encoder, Sixth IEEE International Symposium on Electronic Design, Test and Application, pp. 228–233, 2011.
  25. 25. R. Jeske, J. C. de Souza, G. Wrege, R. Conceicao, M. Grellert, J. Mattos, and L. Agostini, Low cost and high throughput multiplierless design of a 16 point 1-D DCT of the new HEVC video coding standard, Conference on Programmable Logic (SPL), pp. 1–6, March 2012
  26. 26. S. Shen, W. Shen, Y. Fan, and Xiaoyang Zeng, A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards, IEEE International Conference on Multimedia and Expo (ICME), pp. 788–793, July 2012.
  27. 27. W. Zhao, T. Onoye, and T. Song, High-performance multiplierless transform architecture for HEVC, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1668–1671, 2013.
  28. 28. M. Martuza, K. A. Wahid, Implementation of a cost shared transform architecture for multiple video codecs, Journal of Real-Time Image Processing, vol. 10, no. 1, pp. 151–162, March 2015.
  29. 29. A. Ahmed, M. U. Shahid, and A. Rehman, N point DCT VLSI architecture for emerging HEVC standard, VLSI Design, volume 2012, Article ID 752024, pp. 1–13, 2012.
  30. 30. Joint Collaborative Team—Video Coding, CE10: Core transform design for HEVC, JCTVC-G495, Geneva, Switzerland, 21–30, November 2011.
  31. 31. M. N. Haggag, M. El-Sharkawy, and G. Fahmy, Efficient fast multiplication-free integer transformation for the 2-D DCT H.265 standard, IEEE International Conference on Image Processing, pp. 3769–3772, September 2010.
  32. 32. C. W. Chang, H. F. Hsu, C. P. Fan, C. B. Wu, and Robert C. H. Chang, A fast algorithm-based cost-effective and hardware-efficient unified architecture design of 4×4, 8×8, 16×16, and 32×32 inverse core transforms for HEVC, Journal of Signal Processing Systems, vol. 82, no. 1, pp. 69–89, 2016.
  33. 33. S. Lee and K. Cho, Architecture of transform circuit for video decoder supporting multiple standards, Electronics Letters, vol. 44, no. 4, pp. 274–275, February 2008.
  34. 34. C. P. Fan and G. A. Su, Efficient low cost sharing design of fast 1-D inverse integer transform algorithms for H.264/AVC and VC-1, IEEE Signal Processing Letters, vol. 15, pp. 926–929, December 2008.
  35. 35. G. A. Su and C. P. Fan, Low-cost hardware sharing architecture of fast 1-D inverse transforms for H.264/AVC and AVS applications, IEEE Transactions on Circuits and Systems, Part II, vol. 55, no. 12, pp. 1249–1253, December 2008.
  36. 36. H. Qi, Q. Huang, and W. Gao, A low-cost very large scale integration architecture for multistandard inverse transform, IEEE Transactions on Circuits and Systems, Part II, vol. 57, no. 7, pp. 551–555, July 2010.
  37. 37. Y. K. Lai and Y. F. Lai, A Reconfigurable IDCT architecture for universal video decoders, IEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. 1872–1879, August 2010.
  38. 38. K. Wang, J. Chen, W. Cao, Y. Wang, L. Wang, and J. Tong, A reconfigurable multi-transform VLSI architecture supporting video codec design, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 7, pp. 432–436, July 2011.
  39. 39. K. Wahid, M. Martuza, M. Das, and C. McCrosky, Resource shared architecture of multiple transforms for multiple video codecs, 24th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 000947–000950, 2011.
  40. 40. C. P. Fan, C. W. Chang, and S. J. Hsu, Cost effective hardware sharing design of fast algorithm based multiple forward and inverse transforms for H.264/AVC, MPEG-1/2/4, AVS, and VC-1 video encoding and decoding applications, IEEE Transactions on Circuits and Systems for Video Technology, vol. 24, no. 4, pp. 714–720, April 2014.
  41. 41. C. W. Chang, H. F. Hsu, and C. P. Fan, High-efficiency multiple 4x4 and 8x8 inverse transform design with a cost-effective unified architecture for multistandard video decoders, 2014 IEEE Asia Pacific Conference on Circuits & Systems, Okinawa, Japan, pp. 507–510, November 2014.
  42. 42. C. W. Chang, Fast algorithm based cost-effective and hardware-sharing architecture designs of multiple-mode discrete integer transforms for multi-standard video Codecs, Ph.D. dissertation, National Chung Hsing University, Taiwan, 2015.
  43. 43. http://en.wikipedia.org/wiki/Kronecker_product

Written By

Chih-Peng Fan

Submitted: March 9th, 2016 Reviewed: July 21st, 2016 Published: November 23rd, 2016