Open access peer-reviewed chapter

Open-End Winding Induction Motor Drive Based on Indirect Matrix Converter

Written By

Javier Riedemann, Rubén Peña and Ramón Blasco-Giménez

Submitted: November 3rd, 2014 Reviewed: July 2nd, 2015 Published: November 18th, 2015

DOI: 10.5772/61157

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Abstract

Open-end winding induction machines fed from two standard two-level voltage source inverters (VSI) provide an attractive arrangement for AC drives. An alternative approach is to use a dual output indirect matrix converter (IMC). It is well known that IMC provides fully bidirectional power flow operation, with small input size filter requirements. Whilst a standard IMC consists of an AC–DC matrix converter input stage followed by a single VSI output stage, it is possible to replicate the VSI to produce multiple outputs. In this chapter, an open-end winding induction machine fed by an IMC with two output stages is presented. Different modulation strategies for the power converter are analyzed and discussed.

Keywords

  • Open-end winding
  • Electrical drive
  • Matrix converter
  • Pulse width modulation (PWM)

1. Introduction

An open-end winding induction machine, fed by two 2-level VSIs, offers several advantages when compared to a standard wye or delta connected induction machine drive. The main features of an open-end winding induction machine drive can be summarized as [1, 2]: equal power input from both sides of each winding, thus each VSI is rated at half the machine power rating; each phase stator current can be controlled independently; possibility to have twice the effective switching frequency (depending on the modulation strategy); extensibility to more phases, therefore multiphase induction machines can be considered if current reduction is required; possibility of reducing common-mode voltage; and certain degree of fault tolerance, as there is voltage space vector redundancy.

However, an open-end winding induction machine drive can have some drawbacks, such as [1]: possibility of zero sequence current flowing in the machine because of the occurrence of zero sequence voltage; increased conduction losses; more complex power converter requirements, i.e., more power devices, circuit gate drives, etc.

To supply energy to an open-end winding machine, different power converter topologies have been developed; for instance, [36] propose an open-end winding induction machine drive based on two 2-level VSIs fed from isolated DC sources. This topology has the advantage of avoiding the circulation of zero sequence current; however, two isolation transformers are needed. On the other hand, [711] present a topology based on two 2-level VSIs fed by a single DC source. In this case, a zero sequence current could circulate in the machine windings (depending on the modulation strategy used), but just one transformer is needed, reducing the volume and cost of the drive.

Multilevel topologies for open-end winding AC drives are presented in [12–16] where different voltage levels can be achieved in the machine phase windings with certain power converter configurations, then reducing the output voltage distortion but increasing the system cost and complexity.

In the past decades, significant research effort has been focused on direct frequency changing power converters, such as the matrix converter (MC) [17] or the indirect matrix converter [18]. It is known that these power converter topologies offer a suitable solution for direct AC–AC conversion, achieving sinusoidal input and output currents, bidirectional power flow capability and controllable input power factor, without using bulky energy storage elements [18]. Matrix converters have been utilized to supply open-end winding AC machines such as reported in [1921].

In this chapter, the application of an IMC with two output stages to supply energy to an open-end winding induction machine is described [2224]. For evaluation purposes, simulations and experimental results are presented.

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2. Power converter topologies for open-end winding induction machine drives

An open-end winding induction machine drive can be supplied by different configurations of power converters. Some of the most common topologies will be reviewed in this chapter.

2.1. Two 2-level voltage source inverters fed by isolated DC sources

This is the basic power converter for open-end winding AC drives. The circuit configuration is shown in Figure 1 where a standard two-level VSI is connected at each side of the machine stator winding [3]. The VSIs are supplied by isolated DC power sources.

Figure 1.

Two 2-level VSIs fed by isolated DC sources for an open-end winding AC machine drive.

The voltage vectors for inverter 1 are shown in Table 1; the same space vectors are valid for inverter 2, but with superscript 2. As each VSI can produce eight voltage space vector locations independent of the other, there are 64 voltage vector combinations of the full converter, resulting in a vector locus similar to a three-level neutral point clamped (NPC) inverter [6].

States of inverter 1 [SA1SB1SC1]
V11=[1 0 0] V21=[1 1 0] V31=[0 1 0] V71=[1 1 1]
V41=[0 1 1] V51=[0 0 1] V61=[1 0 1] V81=[0 0 0]

Table 1.

Switching states of the individual inverters

Let Vij=[Vi1Vj2] with i,j=1...8 be the phase voltage vector combination of the dual-inverter output. A representation of the vector locations is shown in Figure 2 [6].

Figure 2.

Space vector locations of the dual-inverter scheme.

2.2. Two 2-level voltage source inverters fed by a single DC source

This topology is basically the same described in Section 2.1, but now just one DC supply is considered for the drive, as shown in Figure 3. The disadvantage of this converter is that zero sequence current could circulate in the machine windings because of the generation of output zero sequence voltage; however, this issue can be addressed with an appropriate modulation strategy for the inverters [7].

Figure 3.

Two 2-level VSIs fed by a single DC source for an open-end winding AC machine drive.

2.3. Multilevel topologies

Several multilevel power converters have been developed for open-end winding induction motor drives. For example, Figure 4a shows a three-level inverter [12] and Figure 4b shows a five-level inverter [16]. The main advantage of the multilevel topologies is that the machine phase voltage presents lower voltage distortion, increasing the performance of the drive; but on the other hand, the complexity and cost of the system are also increased.

Figure 4.

(a) Three-level inverter and (b) five-level inverter for open-end winding AC machine drives.

2.4. Direct power converters

Modern direct power converters consider matrix converter and indirect matrix converters. A matrix converter [17] is a direct frequency converter consisting of nine bidirectional switches (three switches per phase) allowing to connect any of the output terminals to any of the input voltages. For an open-end winding induction motor drive, two MCs are required, connected in the arrangement shown in Figure 5. The main features of a matrix converter are: bidirectional power flow capability, sinusoidal input and output currents without bulky energy storage elements, and controllable input power factor. For a standard matrix converter, a total of 36 IGBTs and diodes are required in this topology.

Figure 5.

Open-end winding induction motor drive based on matrix converters.

An indirect matrix converter [18] is also a direct frequency converter having the same features of an MC, but now a DC stage is clearly identified in the topology. The IMC consists of an input rectifier, an AC–DC matrix converter, built of six bidirectional switches; this rectifier produces the DC voltage to supply the converter output stage which is a standard two-level VSI. To supply an open-end winding AC machine, two output inverters are required as can be seen in Figure 6. Considering the six bidirectional switches of the input stage and the two output stages, a total of 24 discrete IGBTs and diodes are required in this topology.

Figure 6.

Open-end winding induction motor drive based on indirect matrix converter.

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3. Model of the open-end winding induction motor drive based on IMC

The complete drive of Figure 6 can be modeled by state equations which describe the dynamic behavior of the system. The effects of power devices dead-times on zero sequence voltages are neglected. All the equations derived below are written in fixed abc coordinates.

The differential equations for the input side are:

vs=Rfis+Lfdisdt+viE1
is=Cfdvidt+iiE2

where

vs=[vsavsbvsc]T,is=[isaisbisc]TE3
vi=[viavibvic]T,ii=[iiaiibiic]TE4

are the source voltage and current (3), and the rectifier input voltage and current (4).

The DC link voltage can be obtained as:

vDC=SrTviE5

with the rectifier switching matrix:

Sr=[SapSanSbpSbnScpScn]E6

where Sxp, Sxn{0,1} with x=a,b,c. The output pole voltage of Inverter 1 (vo1) and Inverter 2 (vo2), with respect to the negative DC link rail, are defined in (7).

vo1=Si1vDC,vo2=Si2vDCE7

where the switching matrices of Inverter 1 (Si1) and Inverter 2 (Si2) are:

Si1=[SA1SB1SC1]=[SAp1SAn1SBp1SBn1SCp1SCn1],Si2=[SA2SB2SC2]=[SAp2SAn2SBp2SBn2SCp2SCn2]E8

and Sxpk=S¯xnk{0,1} with x=a,b,c , k=1,2. The output phase voltage corresponds to the difference of both inverters pole voltages:

vph,o=[vph,oavph,obvph,oc]T=vo1vo2=(Si1Si2)vDCE9

Considering a model of the AC machine with Rs the stator resistance, the output phase voltage can be written as:

vph,o=Rsio+dΨs(io,ir,θr)dtE10

where Ψs is the stator flux linkage vector given by:

Ψs=[ΨsaΨsbΨsc]TE11

The rotor angle is θr and the output (stator) current vector io and rotor current vector ir are given by (12):

io=[ioaiobioc]T,ir=[irairbirc]TE12

As Ψs is an implicit function of t, (10) can be rewritten by using the chain rule for the derivative:

vph,o=Rsio+Ψsiodiodt+ψ2(t)E13

where

ψ2(t)=Ψsirdirdt+ΨsθrdθrdtE14

Assuming Ψs/io is a bijective function of t, it can be defined as:

Ψsio=ψ11(t)E15

and (13) can be redefined by:

vph,o=Rsio+ψ11(t)diodt+ψ2(t)E16

The DC link current is:

iDC=(Si1+Si2)TioE17

and the rectifier input current:

ii=SriDCE18

Taking into account (1) – (18), the state space model of the drive is given by (19) –(21):

disdt=RfLfis1Lfvi+1LfvsE19
dvidt=1Cfis1CfSr(Si1+Si2)TioE20
diodt=ψ1(t)Rsioψ1(t)ψ2(t)+ψ1(t)(Si1Si2)SrTviE21
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4. Zero sequence voltage

As mentioned before, the dual-inverter fed open-ended winding induction motor drive may suffer from zero sequence current caused by zero sequence voltage. This zero sequence voltage is produced because of the asymmetry of the instantaneous phase voltages applied to the machine windings (due to the voltage space vectors used). In general, zero sequence currents may give rise to increased RMS phase current, thus increasing the system losses, high current/voltage THD, and machine over-heating and vibrations. The zero sequence voltage is given by [11]:

vzs=vA1A2+vB1B2+vC1C23E22

The zero sequence voltage contributions from the 64 space vector combinations are shown in Table 2. As can be noted, there are twenty voltage space vectors that do not produce zero sequence voltage; thus in order to avoid the circulation of zero sequence current in the machine windings, only these space vector combinations could be used in the modulation strategy for the dual inverter [9].

Vzs Voltage vector combinations
VDC/2 V87
VDC/3 V84 , V86 , V82 , V57 , V37 , V17
VDC/6 V85 , V83 , V54 , V34 , V81 , V56 , V52 , V36
V32 , V47 , V14 , V16 , V12 , V67 , V27
0 V88 , V55 , V53 , V35 , V33 , V44 , V51 , V31 , V46 , V42
V15 , V13 , V64 , V24 , V11 , V66 , V62 , V26 , V22 , V77
+VDC/6 V58 , V38 , V45 , V43 , V18 , V65 , V25 , V63
V23 , V74 , V41 , V61 , V21 , V76 , V72
+VDC/3 V48 , V68 , V82 , V75 , V73 , V71
+VDC/2 V78

Table 2.

Zero sequence voltage contributions from different space vector combinations

Moreover, from Table 2 and Figure 2, it can be noted that there are two different but equivalent sets of active vectors producing null zero sequence voltage (see Table 3), which could be used along with the zero vectors: V11, V22, V33, V44, V55, V66, V77, and V88.

Set 1 V15 V35 V31 V51 V53 V13
Set 2 V24 V26 V46 V42 V62 V64

Table 3.

Active space vectors producing null zero sequence voltage

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5. Common-mode voltage

Conventional PWM inverters generate alternating common-mode voltages relative to ground which generate currents through the motor parasitic capacitances to the rotor iron [25]. These currents find their way via the motor bearings back to the grounded stator case. The so-called bearing currents have been found to be a major cause of premature bearing failure in PWM inverter motor drives [26].

One of the main features of an open-end winding induction machine drive is the possibility of reducing the common-mode voltage by using certain space vector combinations of the dual-inverter topology (Figure 2). In general, for an open-end winding machine, the common-mode voltage is given by [8]:

vcm=16(vA1+vB1+vC1+vA2+vB2+vC2)E23

where vAi, vBi, vCi, with i=1,2, are the pole voltages of each inverter with respect to a common point of the drive (usually ground).

For the topology depicted in Figure 6, the common-mode voltage is given by:

vcm=16(vA1G+vB1G+vC1G+vA2G+vB2G+vC2G)E24

where the common point G is the grounded neutral point of the source. These voltages can also be expressed as:

vAiG=SApivpG+SAnivnGvBiG=SBpivpG+SBnivnGvCiG=SCpivpG+SCnivnGE25

where vpG and vnG are the voltages of the positive and negative rail of the DC link with respect to the grounded neutral point of the source, respectively; Sxpi, Sxni{0, 1} with x=A, B, C, i=1, 2 are the switching functions of the inverter devices (0: switch opened, 1: switch closed) and Sxni=1Sxpi (because of the complementary operation of the upper and lower switches of each inverter leg). Therefore,

vcm=16[(SAp1+SBp1+SCp1+SAp2+SBp2+SCp2)vpG+(SAn1+SBn1+SCn1+SAn2+SBn2+SCn2)vnG]E26

Let Nsw=SAp1+SBp1+SCp1+SAp2+SBp2+SCp2, thus

vcm=16[NswvpG+(6Nsw)vnG]E27

where Nsw is the number of upper inverter switches closed. The squared RMS value of the common-mode voltage is:

vcmRMS2=136T0T[NswvpG+(6Nsw)vnG]2dtE28

where T is the period of vpG (equals the period of vnG). Further expansion yields:

36vcmRMS2=Nsw21T0TvpG2dt+2Nsw(6Nsw)1T0TvpGvnGdt+(6Nsw)21T0TvnG2dtE29

The voltages of the DC link rails are given by:

vpG=Sapvra+Sbpvrb+ScpvrcvnG=Sanvra+Sbnvrb+ScnvrcE30

wherevra, vrb, and vrc are the converter input phase voltages and Sxp, Sxn with x=a, b, c are the switching functions of the rectifier. Accordingly, vpG and vnG will always be segments of different input phase voltages and

|vpG(t)|=|vnG(tto)| , toE31

thus

0TvpG2dt=0TvnG2dtE32

Differentiating (29) with respect to Nsw and equating to zero, it can be found that vcmRMS2 (and implicitly vcmRMS) achieves a minimum value at Nsw=3, which means that in order to reduce the RMS common-mode voltage at the machine terminals, only three upper inverter switches should be closed at each switching period.

This can be further investigated by considering a virtual midpoint of the DC link as a reference point (see point 0 in Figure 6). Then, (24) can be rewritten as:

vcm=16(vA10+vB10+vC10+vA20+vB20+vC20)+v0G=vcm0+v0GE33

where the contributions of the input and output stages to the overall common-mode voltage have been separated (v0G and vcm0, respectively). The voltage v0G is the voltage between the reference point 0 and the grounded neutral point of the source. This voltage can be calculated as:

v0G=12[(Sap+San)vra+(Sbp+Sbn)vrb+(Scp+Scn)vrc]E34

It can be seen in (34) that v0G depends on the modulation of the input stage, which is totally defined by the duty cycles of the rectifier stage. On the other hand, the voltage vcm0 can be rewritten as:

vcm0=16[NswvDC2+(6Nsw)(vDC2)]=16[NswvDC3vDC]E35

Therefore, it can be seen in (35) that by using Nsw=3, the contribution of the output inverters to the common-mode voltage is eliminated [8]. Table 4 shows the voltage space vector combinations of the dual-inverter topology which do not produce common-mode voltage.

As can be noted from Table 4 and Figure 2, there are larger and lower active vectors available which produce zero common-mode voltage. Any of them could be considered in the modulation strategy for the dual-inverter system depending on the machine voltage requirement. However, from Table 2 and Table 4, it can be appreciated that the space vectors which reduce the common-mode voltage are not the same vectors which reduce the zero sequence voltage; thus, if a common-mode voltage is required, a compensation should be done for the zero sequence voltage; in other case, large zero sequence current components will circulate in the machine windings; a type of compensation will be reviewed in the following section.

Space vector combinations
[SAp1SBp1SCp1SAp2 SBp2SCp2]
V14=[1 0 0 0 1 1] V56=[0 0 1 1 0 1]
V25=[1 1 0 0 0 1] V61=[1 0 1 1 0 0]
V36=[0 1 0 1 0 1] V43=[0 1 1 0 1 0]
V41=[0 1 1 1 0 0] V12=[1 0 0 1 1 0]
V52=[0 0 1 1 1 0] V16=[1 0 0 1 0 1]
V63=[1 0 1 0 1 0] V65=[1 0 1 0 0 1]
V23=[1 1 0 0 1 0] V54=[0 0 1 1 1 0]
V34=[0 1 0 0 1 1] V32=[0 1 0 1 1 0]
V45=[0 1 1 0 0 1] V21=[1 1 0 1 0 0]
V78=[1 1 1 0 0 0] V87=[0 0 0 1 1 1]

Table 4.

Space vectors with zero common mode

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6. Pulse width modulation strategies

In this section, PWM strategies for an open-end winding induction motor drive based on a two-output IMC are described.

6.1. Modulation strategies for the input stage of the IMC

The modulation for the input (rectifier) stage of the converter aims to obtain a positive DC link voltage in each sampling period and unity displacement factor at the input [27]. Two different space vector modulation (SVM) strategies can be used for the rectifier [28]. One modulation maximizes the DC voltage by commutating between the largest and the second largest positive line input voltage (Figure 7). The other modulation produces a reduced DC voltage commutating between the lowest and the second lowest input line voltage (Figure 8).

Figure 7.

(a) Space vector locations for maximum DC voltage. (b) Maximum DC voltage

If θref,i is the angle of the voltage reference vector; the γδ duty cycles for both modulation strategies are given in (36)–(38). Further details about the modulations for the input stage can be found in [27, 28].

dγR=dγdγ+dδ , dδR=dδdγ+dδE36

with

dγ=sin(π3θref,i) , dδ=sin(θref,i)E37

the duty cycles for maximum DC voltage and

dγ=cos(θref,i) , dδ=cos(π3θref,i)E38

the duty cycles for reduced DC voltage. Figure 9a shows the transition from reduced DC voltage to maximum DC voltage and Figure 9b shows the opposite situation.

Figure 8.

(a) Space vector locations for reduced DC voltage. (b) Reduced DC voltage.

Figure 9.

Transition between both rectifier modulation strategies.

The rectifier SVM for reduced DC link voltage decreases the voltage gain by 3. Thus, the transition between reduced and maximum DC link voltage should take place when the output voltage reference is higher than 1.53Vph, input=0.866Vph, input.

6.2. Modulation strategies for the output stages of the IMC

6.2.1. Carrier-based modulation strategy

In a PWM strategy based on a triangular carrier (SPWM), the duty cycles for each leg of inverter 1 are [29]:

da=12(m(t)cos(2πmfk)+1)E39
db=12(m(t)cos(2πmfk2π3)+1)E40
dc=12(m(t)cos(2πmfk+2π3)+1)E41

In this case, It is necessary a variable modulation index given by m(t)=mo(dγ+dδ) to compensate the fluctuations of the DC link voltage, mo is the final modulation index (0mo1), mf=fs/fois the frequency index (fo: output frequency, fs: switching frequency) and 0kmf. Duty cycles of inverter 2 are obtained using (39)–(41), but considering a phase shift of 180° for the cosine functions. For implementation purposes, the duty cycles da, db, and dc are transformed into equivalent αβ0 duty cycles. Thus, considering Figure 10, the αβ0 duty cycles are:

d0=1dmaxE42
dα=dmaxdmidE43
dβ=dmiddminE44
d7=dminE45

Figure 10.

A single inverter stage duty cycles.

To obtain a correct balance of the input currents and the output voltages in a switching period, the modulation pattern should produce all combinations of the rectification and the inversion switching states [27], resulting in the following duty cycles for the active vectors:

dαγ=dαdγR,dβγ=dβdγR,dαδ=dαdδR, dβδ=dβdδR E46

The duty cycle corresponding to the switching state [SApSBpSCp]=[0 0 0] is:

d00=d0,totdminE47

and the combined zero vectors duty cycles are:

d0γ=d00dγR,d0δ=d00dδRE48

The output stages duty cycles are different for each inverter and are represented in Figure 11 [23] for inverter i (i=1,2).

Figure 11.

Inverters duty cycles.

6.2.2. Space vector modulation strategy for zero sequence reduction

As mentioned in Section 4, in an open-end winding induction machine drive, the zero sequence voltage can be reduced by using the active space vectors given in Table 3. The zero vectors are mapped depending on the sector information [9]. The mapping is shown in Table 5.

Sector I II III IV V VI
Set 1 zero vectors V55 V33 V11 V55 V33 V11
Set 2 zero vectors V22 V66 V44 V22 V66 V44

Table 5.

Mapping of zero vectors

The duty cycles for the output stages are calculated as:

dα=m(t)sin(π3θref,o), dβ=m(t)sin(θref,o) and d0=1dαdβE49

where m(t)=mo(dγ+dδ) and 0mo1. θref,o is the angle of the output reference voltage space vector. As in the carrier-based modulation strategy, the duty cycles of the rectifier and the inverters should be combined; thus the active vector duty cycles are given in (46).

The combined zero vectors duty cycles are:

d0γ=d0dγR,d0δ=d0dδRE50

Thus, the switching sequence, which is the same for both output stages, is shown in Figure 12, commutating the input stage with zero DC current [27].

Figure 12.

Standard switching sequence for IMCs.

6.2.3. Space vector modulation strategy for common-mode voltage reduction

If only the voltage space vectors shown in Table 4 are used in the modulation strategy for the output stages of the IMC, the contribution of the dual-inverter to the overall common-mode voltage can be eliminated. The duty cycles for the IMC outputs are calculated as in (49) – (50). However, as mentioned in Section 5, the space vectors producing null vcm0 are not the same vectors producing null zero sequence voltage. Hence, as in this SVM strategy, the vectors used to modulate the converter output stages will eliminate the common-mode voltage; a compensation must be performed to avoid the circulation of zero sequence current in the machine.

The average zero sequence voltage within a sampling interval can be eliminated by forcing the zero sequence volt-seconds to zero [11] by applying the null voltage vectors with unequal times. Accordingly, the standard switching sequence used in the IMC [27] is modified in order to reduce/eliminate the average zero sequence voltage within a sampling period. For the modulation strategy presented, the duty cycles for both output VSIs are the same, which can be noted in Figure 13.

Figure 13.

Modified switching sequence for the IMC with two outputs.

Taking into account that the same space vectors sequence applied in γR interval is applied in the δR interval but in reverse order, then the value of x, which causes the cancellation of the zero sequence volt-seconds, is calculated at every sampling period to satisfy [11]:

vzs1x(0γ+0δ)+vzs2(αγ+αδ)+vzs3(βγ+βδ)+vzs4(1x)(0γ+0δ)=0E51

where vzsk with k=1, 2, 3, 4, is the zero sequence voltage value at intervals x0γ, αγ, βγ, and (1x)0γ, respectively. The value of vzsk can be calculated by using (22) and considering the space vectors used in the modulation strategy.

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7. Open-end winding induction machine drive

In this section, the application of a two-output IMC supplying an open-end winding induction machine will be presented. The performance of the drive by using some of the modulation strategies discussed above will be shown and analyzed via simulation and experimental results. The simulations are carried out in a PSIM/MATLAB simulation platform. On the other hand, experimental results are obtained using the setup shown in Figure 14. The IMC has been designed and built at the Power Electronics, Machines and Control lab facilities, University of Nottingham, UK. A six-pole induction machine rated at 7.5 kW is used. A DSP board, based on the TMS320C6713 processor, is used as the control platform. The calculation of duty cycles is carried out on the DSP among several other tasks. An FPGA interface board, designed at Nottingham University, is used to implement the modulation strategies and data acquisition. Communication between the DSP and a PC is achieved using a DSK6713HPI (Host Port Interface) daughter card. The converter input stage uses SK60GM123 modules and the output stages use SK35GD126 modules. The switching frequency is 10 kHz and voltages and currents are also sampled at 10 kHz. The load used in the experimental system is a DC generator, supplying a resistive load, coupled with the induction motor shaft.

Figure 14.

Experimental setup.

7.1. SVM strategy for zero sequence voltage reduction and changing DC voltage

The modulation strategies, presented in Section 6.1 and 6.2.2, are used to implement a standard feedforward vector control scheme [30] for the machine currents (Figure 15). Simulation and experimental results are shown in Sections 7.1.1 and 7.1.2, respectively.

Figure 15.

Feedforward vector control scheme of induction machine.

7.1.1. Simulation results

The performance of the vector control scheme is verified by applying step changes in the dq-axis reference currents. Figure 16 shows the waveforms obtained by applying a step change in the q-axis reference current from 7.7 to 10 A at t=0.16 s, while d-axis current is kept constant at 6 A. Figure 16a shows dq reference currents and their corresponding responses. A good tracking of the reference currents is obtained. The motor currents and phase a voltage are shown in Figure 16b. The step change in q-axis current is followed with changes in the magnitude and phase of the instantaneous machine currents. Moreover, a transition between reduced virtual DC voltage to maximum virtual DC voltage can be noticed in the output phase voltage of Figure 16b (bottom).

Figure 16.

q-axis current step change. (a) Motor q-axis current (top) and d-axis current (bottom). (b) Motor currents (top) and phase voltage (bottom).

Figure 17a shows the performance of the control scheme when a step change from 6 to 8 A is applied in d-axis reference current while q-axis current is kept constant at 7.7 A. The motor currents and phase- a voltage are shown in Figure 17b. Again, the transition between both modulation strategies for the input rectifier can be noticed.

Figure 17.

d-axis current step change. (a) Motor q-axis current (top) and d-axis current (bottom). (b) Motor currents (top) and phase voltage (bottom).

Figure 18 (top) shows the converter input phase voltage and current; the unity input displacement factor can be noted. Figure 18 (bottom) shows the output zero sequence voltage that has been obtained from the voltage across the load in each phase and then applying (22). As can be seen, the zero sequence voltage has been eliminated due to the modulation strategy used for the output stages.

Figure 18.

Input phase voltage and current (top) and zero sequence voltage (bottom).

7.1.2. Experimental results

The dq-axis currents are shown in Figure 19a. As the speed controller saturates when a step change in the speed reference takes place, a step change in q-axis current reference is applied. The d-axis current reference is kept constant at 6 A. A good performance of the control scheme can be appreciated agreeing with the simulated results. The instantaneous motor currents and phase a voltage are shown in Figure 19b. Again, the transition between both rectifier modulation strategies can be noted in the output phase voltage (Figure 19b bottom) when the change in q-axis reference current is applied.

Figure 19.

q-axis current step change. (a) Motor q-axis current (top) and d-axis current (bottom). (b) Motor currents (top) and phase voltage (bottom).

Figure 20a shows the dq machine currents when a step change in d-axis reference current is applied while q-axis current is kept constant at 7.7 A. The motor currents and phase- a voltage are shown in Figure 20b. A good correspondence with the simulation results can be noted.

Figure 20.

q-axis current step change. (a) Motor q-axis current (top) and d-axis current (bottom). (b) Motor currents (top) and phase voltage (bottom).

Finally, Figure 21 (top) shows the input phase voltage and current. The zero sequence voltage shown in Figure 21 (bottom) is not exactly zero, but this is probably due to the measurement procedure because not all of the channels are sampled at the same time and because in Figure 18 the input switches are ideal.

Figure 21.

Input rectifier voltage and current (top) and zero sequence voltage (bottom).

7.2. SVM strategy for common-mode voltage reduction and zero sequence voltage compensation

Simulation and experimental results for the modulation strategy presented in Section 6.2.2 will be shown in this section. The rectifier is modulated to maximize the DC link voltage (Figure 7) and the full drive is tested in open-loop v/f operation.

7.2.1. Simulation results

The DC link voltage and phase- a machine voltage are shown in Figure 22a, top and bottom, respectively. The reference output voltage and frequency were set to 150 V and 50 Hz, respectively. The machine currents for 25 Hz operation are shown in Figure 22b (top), while Figure 22b (bottom) shows machine currents for 50 Hz operation.

Figure 22.

(a) DC link voltage (top) and output phase voltage (bottom). (b) Machine currents for 25 Hz output (top) and 50 Hz output (bottom).

Small disturbances, occurring every 60°, can be noted in the motor currents shown in Figure 22b. These current disturbances are due to the application of zero voltage vectors to machine windings, see PWM pattern in Figure 13, aiming to reduce the zero sequence voltage. During the application of zero voltage vectors, each machine phase winding is supplied with a voltage of VDC or +VDC. When VDC voltage is applied to the machine windings, the current decreases according to the zero vector duty cycle. Figure 23 shows the current disturbance along with the corresponding DC link voltage and output phase voltage.

The input (supply) currents are shown in Figure 24 (top) while Figure 24 (bottom) shows the converter input phase voltage (blue) and current (green) for an output reference of 150 V and 50 Hz. The unity displacement factor is evident in Figure 24 (bottom).

The low-order harmonics of the machine currents are presented in Table 6.

Figure 23.

Phase a machine current (top), DC link voltage (middle), and machine phase- a voltage (bottom).

Current Harmonic RMS Value (A)
Fundamental 14.400
2nd 0.250
3rd 0.184
4th 0.112
5th 0.025
6th 0.815

Table 6.

Harmonic content of the machine currents

Figure 24.

Input currents (top) and input phase voltage and current (bottom).

Figure 25a shows the common-mode voltage separated into v0G and vcm0 as defined in (33)–(35). Due to absence of the reference point 0 in the real (and also simulated) converter, the common-mode voltages v0G and vcm0 shown in Figure 25a top and bottom, respectively, are obtained as:

v0G=vnG+vDC2vcm0=16(vA1n+vB1n+vC1n+vA2n+vB2n+vC2n)vDC2E52

where n is the negative rail of the DC link.

It can be seen in the simulation results that the contribution of the output inverters to the common-mode voltage is completely eliminated due to the modulation strategy used. Figure 25b shows the zero sequence voltage (top) and its frequency spectrum (bottom). It can be noted that the low-order zero sequence harmonics are reduced because of the asymmetry of the null vector duty cycles used in the switching sequence for each output stage.

Figure 25.

(a) Common-mode voltages v0G (top) and vcm0 (bottom). (b) Zero sequence voltage (top) and its frequency spectrum (bottom).

7.2.2. Experimental results

Figure 26a (top) shows the DC link voltage while Figure 26a (bottom) shows the voltage across the machine phase- a winding. The output phase voltage presents a fundamental component of 141 V, 50 Hz, slightly less than the voltage reference (150 V) because of the device voltage drops. As can be seen, the modulation strategy used results in a bipolar pulse width modulated voltage at the converter output. The machine currents for 25 Hz and 50 Hz operation are shown in Figure 26b (top and bottom), respectively. The reference output voltages are set to 75 and 150 V, respectively. Correspondence between the simulation and the experimental result can be observed.

In Figure 26b, the effect of the zero voltage vectors in the PWM pattern shown in Figure 13 is also observed. The supply currents are shown in Figure 27 (top), again with good correspondence with the simulation study. Figure 27 (bottom) shows the input phase voltage and current.

Figure 28a shows the common-mode voltages v0G (top) and vcm0 (bottom). The voltage v0G follows very closely the simulation results shown in Figure 25. The voltage vcm0 is not exactly zero, but this is probably due to the measurement procedure because not all of the channels are sampled at the same time and because in Figure 25 the input switches are ideal. Finally, Figure 28b shows the zero sequence voltage (top) and its frequency spectrum (bottom), agreeing closely with the simulation results.

Figure 26.

(a) DC link voltage (top) and output phase voltage (bottom). (b) Machine currents for 25 Hz output (top) and 50 Hz output (bottom).

Figure 27.

Input currents (top) and input phase voltage and current (bottom).

Figure 28.

a) Common-mode voltages v0G (top) and vcm0. (bottom). (b) Zero sequence voltage (top) and its frequency spectrum (bottom).

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8. Conclusion

The open-end winding induction machine has been presented in this chapter. Different power converter topologies for this type of machine connection have been shown and briefly discussed. Because of the advantages of indirect matrix converter, emphasis has been done in the application of this converter to control the machine. Therefore, an indirect matrix converter with two outputs stages has been proposed to supply energy to the open-end winding induction motor. This topology has been thoroughly modeled and pulse width modulation strategies for the input and output stages of the proposed topology have been shown. Issues such as zero sequence voltage and common-mode voltage, presented in the dual-inverter configuration, have been analyzed and strategies to eliminate and/or reduce such effects have been presented. The control and modulation strategies have been simulated and experimentally tested in a prototype rig. Results for open and closed-loop operation of the open-end winding topology based on IMC have been shown.

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Acknowledgments

This work was funded by Fondecyt Chile under Grant 1151325. The financial support of CONICYT/FONDAP/15110019 is also acknowledged.

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Written By

Javier Riedemann, Rubén Peña and Ramón Blasco-Giménez

Submitted: November 3rd, 2014 Reviewed: July 2nd, 2015 Published: November 18th, 2015