Open access

RFID Readers for the HDX Protocol - A Designer’s Perspective

Written By

Dan Tudor Vuza and Reinhold Frosch

Submitted: October 15th, 2010 Published: July 20th, 2011

DOI: 10.5772/16760

Chapter metrics overview

3,238 Chapter Downloads

View Full Metrics

1. Introduction

Previous work (Gelinotte et al., 2006; Vuza et al., 2007; Vuza et al., 2009) presented the contribution of the present authors to the development of readers for communication with tags according to the FDX protocol. Readers produced so far by Frosch Electronics were classified as voltage-driven and current-driven (Vuza et al., 2009), according to which circuit variable is controlled by the reader and which is controlled by the tag (and sensed by the reader). A voltage-driven reader powers the antenna with an AC voltage of constant amplitude. The FDX tag transmits data by load modulation, which causes the variation of the voltage at the tap point (the junction between the antenna coil and the tuning capacitor). The reader senses the latter voltage and extracts the baseband signal that contains the data. A current-driven reader powers the antenna with an AC current of constant amplitude. Again, the FDX tag transmits data by load modulation, which this time modulates the voltage across the whole antenna circuit. The reader extracts the data from the latter voltage, the tap point connection being not needed in this case. Recently, Frosch Electronics decided to add a new feature to the existing readers, providing them with the possibility of communicating with tags that use the HDX protocol, of interest in applications such as animal identification, so that the same reader could cover a larger variety of applications. In FDX, the tag is continuously powered by the reader. In HDX, the tag is first charged by an RF pulse of limited duration from the reader, and then it transmits the data using the energy stored during the first step, by driving its coil with an AC voltage whose frequency toggles between two values fC = 134.2 KHz and fLOW = 123.7 KHz prescribed by the HDX standard.

After a brief reminder on the two types of FDX readers in section 2, we present in sections 3 and 6 circuit topologies achieving the HDX extension for each of the mentioned classes of readers. The topologies are different for the two classes according to whether the tap point is accessible or not. For voltage-driven readers, the schematic is based on the usage of the TMS3705 circuit as a bit decoder. For current-driven readers, we consider the option of bit decoding by either a dedicated IC or by building a custom decoder from discrete hardware components supplemented by a software component, which could in principle offer more control over the decoding process.

In section 4 we discuss the important issue of transients, which has to be taken into account when striving for data integrity, and hence reliability. Transient effects have been discussed in (Vuza et al., 2009) for FDX load modulation and have to be discussed again in the HDX setting, since transients manifest themselves when the tag changes the frequency and may have deleterious effects on data integrity if their duration is too long. The results obtained here are compared with those previously obtained for FDX and recommendations for reader design are drawn.

In section 5 we expose the principle of low coupling approximation that allows, in the case of low coupling between tag and reader antenna which is usually the case in real situations, to replace the tag with a voltage source in series with the reader antenna for the purpose of circuit analysis. We will make use of this principle in the analysis of transients and of the procedure of bit equalization.

Because the reader antenna circuit is tuned to the nominal frequency fC, the two signaling frequencies used by the tag may induce voltages in the reader circuits whose amplitudes differ in a significant way. Such an inequality in amplification may increase the probability of bit error, especially at higher reading distances when the signal is weak. We present in section 7 a method for equalizing the bit amplification based on the one-pole model of the opamp and the related gain-bandwidth product, which does not require any additional component in order to achieve the required effect.

The material discussed so far has emphasized the importance of the correct choice of the components in the antenna and amplifier circuits in order to ensure that the duration of transients agrees with the bit time and that equalization of bit amplification is achieved as much as possible. The choice is to be made in the design phase and fine-tuning will be needed in the test phase. Both mentioned phenomena are connected to the transitions between the two signaling frequencies employed by the tag. One needs therefore means for generating such transitions in a reproducible and convenient way. Using real tags for testing does not provide the most convenient way. Observing the frequency transition is not easy on a scope, as the frequency difference is rather small. The transition is gradual because of transients, making difficult to estimate when the transition actually started. For this reason it is preferably to rely on simulators. In section 8 we propose a hardware tag simulator for tuning and testing. In order to be able to estimate the parameters of transients, it is necessary to know precisely the moment of transition onset, which cannot be deduced from the gradual system response. The simulator provides the means for generating transitions together with a signal for the transition onset that can be used as a trigger for the scope on which the system response is recorded. The transient is hidden in the signal and only its negative effects on the latter are immediately visible. Displaying the transient itself require an indirect method. We propose in section 9 two such methods aiming at providing a graphical display of transients, allowing thus to estimate their parameters such as duration and magnitude and to assess their effects on the received signal: a software simulation procedure based on PSpice, which can be used in the design phase, and a method based on the usage of the simulator that can be used in the testing and tuning phases.


2. Voltage-driven and current-driven readers for FDX tags

A voltage-driven reader (figure 1) powers the antenna with an AC voltage of constant amplitude at a carrier frequency fC of 125 KHz or 134.2 KHz. The FDX tag transmits data by opening and closing the switch SW, which, due to the magnetic coupling M, modulates the current through the antenna. The variation of the current antenna causes the variation of the voltage VTAP at the tap point (the junction between the antenna coil and the tuning capacitor). The reader senses the latter voltage and extracts the baseband signal that contains the data.

Figure 1.

Voltage-driven reader

A current-driven reader (figure 2) powers the antenna with an AC current of constant amplitude. Again, the FDX tag transmits data by opening and closing the switch SW, which this time modulates the voltage across the whole antenna circuit. The reader extracts the data from the latter voltage, the tap point connection being not needed in this case.

Figure 2.

Current-driven reader

It is to be observed that for the voltage-driven reader, the drivers that provide the amplified voltage to the antenna can be set into high Z mode via the tristate input during the interval when the antenna is not driven. This will be of importance for the extension to HDX tags. The high Z mode is implicit for the current-driven reader, as the (near) ideal current source presents high impedance to the antenna.

The formulas to be presented in the next sections are derived from the following general circuit model of the interaction between reader and tag.

Figure 3.

Model of coupling reader-tag

Consider the circuit of figure 3, in which the two coils are linked by the magnetic couplingM=kL1L2. Let I1 be the current sourced by voltage source V1 and let I2 be the current flowing into impedance Z2. Elementary circuit analysis gives the results below, in which s denotes the Laplace variable.


3. Adding the HDX protocol to the FDX voltage-driven reader

In FDX, the tag is continuously powered by the reader and transmits data by load modulation. In HDX, the tag is first charged by an RF pulse of limited duration from the reader, and then it transmits the data using the energy stored during the first step. The tag drives its coil with an AC voltage whose frequency toggles between two values: according to the standard (International Organization for Standardization, 2007), each data bit comprises 16 cycles of the AC voltage, the nominal frequency fC = 134.2 KHz being used for a zero bit and the frequency fLOW = 123.7 KHz for a one bit.

For the voltage-driven reader (figures 4, 5) we consider the usage of a dedicated integrated circuit (IC) such as TMS3705 produced by Texas Instruments (Texas Instruments, 2003). The manufacturer provided the IC with its own antenna drivers so that a minimal design of an HDX reader could consist of only the IC and a micro-controller. However, in our design we continue to use the drivers of the existing reader in order to keep the FDX functionality. In

Figure 4.

Adding the HDX protocol to the voltage-driven reader

the schematic of figure 4, we first observe the MOS transistor MS with low on-resistance that is used as a switch. When the reader is used in FDX mode, MS is cut off allowing the antenna to be powered by the reader drivers. The same is true during the charge phase of the communication with an HDX tag. After the charge phase, the reader stops driving the antenna and the drivers are tristated. The reader micro-controller (uC) then turns on MS, establishing thus a low resistance path through which the antenna circuit is closed. The resistor RA includes the AC resistance of the antenna as well as any additional resistor added in order to limit the antenna current and to damp the transients during transmission/reception; more on this topic in the next section. There is a resistor RMS in series with MS, the role of which will also be explained later. It is to be observed that only positive voltages are present at the drain of MS when cut off, which avoids any unwanted conduction through the parasitic diode of the transistor, represented here explicitly in parallel with the latter.

Figure 5.

The voltage-driven FDX reader produced by Frosch Electronics (left) and the reader with the plug-in for the HDX extension (right).

The tag starts the transmission a short delay after the interruption of the power flow from the reader. Meanwhile the uC has informed the decoder IC via the command line that a new decoding cycle is to begin. In our schematic, the tag is represented as a voltage source VT with output impedance ZT that drives the tag coil LT. The voltage source produces an AC voltage of constant amplitude whose frequency toggles between the nominal frequency fC to which the reader antenna is tuned and the frequency fLOW. The current in the tag coil induces a frequency-modulated voltage in the reader antenna circuit that is sensed at the tap point by the decoder IC. The tap voltage is amplified by an opamp internal to the IC, which is part of an inverting amplifier configuration together with two external resistors provided by the user. The IC extracts the bit information from the frequency modulation and transmits it serially to uC via the data line.


4. Effect of transients on data reception

The effect of transients for the FDX protocol has been discussed in (Vuza et al., 2009). A similar analysis may be carried for the HDX protocol. Consider a circuit described by the linear system


where X(t) is the state vector and Y(t) is a periodic input. In most cases we may assume that Y is continuous but we may also allow for a discontinuous input such as a square wave. In the latter case we shall assume that Y is integrable on each finite interval, that X is continuous and almost everywhere derivable, and that (3) holds almost everywhere; the periodicity of Y will be understood in the sense that there is T > 0 such that Y(t + T) = Y(t) almost everywhere in t, each such number T being called a period of Y. Assume that the circuit is stable, that is, the characteristic roots of matrix S have strictly negative real parts. There is a unique periodic solution XP(t) for (3), which we shall call the periodic solution for input Y. The general solution of (3) is the sum between XP and a solution of the homogeneous system


The existence and uniqueness of the periodic solution are readily established. We consider here only the case when Y is not constant, the proof being easily adapted to the other case. Since Y is periodic and not constant, it has a smallest period T such that any other of its periods is a multiple of T. Let X be any solution of (3); such a solution always exists, for instance the one given byX(t)=exp(St)0texp(Sτ)Y(τ)dτ. The matrix exp(ST) – I is invertible as S is stable (I being the identity matrix). The function


is also a solution of (3) satisfying XP(0) = XP(T). As Y has the period T, the function X2(t) = XP(t+T) is again a solution of (3). Hence X3(t) = X2(t) – XP(t) is a solution of (4) that vanishes at t = 0. But such a solution must vanish everywhere; hence XP must admit T as a period. Let now XP2 be another periodic solution of (3) and let T2 be its period. Since T2 is also a period for the derivative of XP2, it follows from (3) that it is a period for Y; hence T2 must be a multiple of T and therefore a period for XP. Consequently XP2(t) – XP(t) is a solution of (4) with period T2. But since S is stable, all solutions of (4) must approach 0 as t goes to infinity, implying that the mentioned periodic solution must vanish identically and hence XP2 = XP.

Consider now two periodic inputs Y1, Y2 (possibly with different periods) and let XP1, XP2 be the respective periodic solutions. Suppose that up to moment t0, the circuit received input Y1 and its state vector evolved according XP1. At t0, the input changes from Y1 to Y2. How the state vector will change? After t0, the state vector can be written as the sum of the periodic part XP2(t) and a transient part TR(t) that is a solution of (4) uniquely determined by its initial value at t0. The latter value is in turn determined by imposing the continuity of the state vector at t0, expressed by the equality XP1(t0) = XP2(t0) + TR(t0). Since, because of stability, every solution of (4) tends to 0 for large values of t, it follows that as times goes past t0, the state vector will approach the periodic solution XP2 for input Y2. Thus, the change of input at moment t0 results in changing the evolution of the system from one periodic solution to another, but has also the side effect that a transient solution will manifest itself for some time after the change. The time constants of these transients are determined by the characteristic roots of S. As well known from Laplace transform theory, if one is interested in the time constants of the transients that affect an output of the system, one has to look for the roots of the denominator of the transfer function from the driving input to that output and take the inverses of the real parts of those roots, provided that the degree of the denominator equals the order of the system.

Figure 6.

Model for studying the effect of transients

We apply the above remarks to the case of the HDX reader of section 3. The inverting input of the opamp internal to the decoder IC is a virtual ground. Hence one may use the simplified schematic of figure 6 for analyzing the transients that are induced whenever the tag switches from a frequency to another during data transmission to reader. In this schematic, RS is the total resistance in series with the antenna, which in this case is the series combination of RA and RMS in figure 4. Let ZA be the impedance seen by the reader antenna. According to (2), the antenna current is given by


We consider the case of weak coupling, as in real situations values around 0.01 for k are common. It is therefore reasonable to approximate the above formula by


The tap voltage equals the above current multiplied by the parallel impedance of CA and RP. Define the series quality factor QS = LAωC/RS and the parallel quality factor QP = RPCAωC, where ωC = 2πfC and fC is the nominal frequency to which the antenna is tuned. Introducing also the normalized Laplace variable x = sC, we have for the tap voltage




When the tag changes frequency, VTAP will be affected by transients whose time constants are computed by finding the roots of the denominator of the transfer function in (7). Specifically, for any such root s0, 1/Res0will be the time constant for a transient. In the limit of weak coupling, the denominator is the product of two factors, one of them depending exclusively on the tag and the other depending only on the reader antenna circuit. The reader designer has no control over the first factor and may only assume that the time constants related to it have been taken care of in the adequate way by the tag producer. The reader designer shall therefore take care of the time constants related to PA(x) and ensure that the corresponding transients will be short enough in order not to disturb the data decoding. Provided that |QP1QS1|2,which is usually the case, the roots of PA(x) will be complex conjugated and will produce the time constant 2(QP1+QS1)1/ωC.It is reasonable to ask that the 90% - 10% decrease time of the corresponding transient, equal to 2.2 times its time constant, should be less than half of the shortest duration TB of a bit. It results that the following inequality should be imposed on the quality factors:


During the charge phase, the opamp of the decoder IC will be saturated because of the high voltage at the tap point and its inverting input will no longer function as a virtual ground. Protection diodes at the inverting input prevent the opamp to be damaged by the high voltage. In order not to exceed the current rating of the diodes, it is advisable to choose a high value for RP, resulting in a high QP. Inequality (8) will then be satisfied if we impose πfCTB/4.4 as an upper bound for QS. In the case of HDX protocol, TB equals 16/fC so 11.4 is an upper bound for QS.

Let us compare the above situation with the case of the reader in figure 4 working in FDX mode. Now the voltage source VR is on the reader side as in figure 1 and the tag transmits data by modulating the load ZT. The voltage at the tap point is obtained with the aid of (1):


where PA(x) is as above. In the limit of weak coupling, the denominator is again approximated by the product of two factors, one determined by the tag and the other by the reader. Transients occur when the tag changes the value of ZT. Similar considerations as above lead to the upper bound πfCTB/4.4 for QS, where this time TB is the shortest bit duration for the FDX protocol. The latter is in general two times larger than the bit duration for HDX, resulting in a two times higher upper bound for QS.

The current for a tuned antenna circuit is given by


A higher antenna current means that the tag can be at a larger distance from the antenna and still receive the amount of power required for the activation of its internal circuits. Higher QS means a higher antenna current. Since the upper bound on QS is higher for FDX compared with HDX, it makes sense to use a lower RS for FDX. This is the reason for using the resistor RMS in figure 4. When the reader works in FDX mode, transistor MS is cut off, RMS does not play any role and QS is determined by RA, adjusted to fulfill the upper bound for QS in the FDX case. In the charge phase of HDX, MS is also cut off and the current is again determined by RA. Choosing the minimal allowed value for the latter would ensure the largest possible activation distance for the HDX tag. Finally, during reception of HDX data, MS is turned on and RMS is now in series with RA, lowering thus QS in order to agree with the upper bound for HDX. A mean for increasing the antenna current without exceeding the upper bound for QS is to decrease LA, with simultaneous decrease of RA (to maintain the same QS) and increase of CA (to maintain the tuning). However, the reader designer should be aware that, as shown by (7), decreasing LA while maintaining the quality factors constant would decrease the tap voltage and hence reduce the signal received by the decoder. It is to be observed that in the FDX case, the modification in question does not change the tap voltage and the signal received from the tag at all, as proved by (9).


5. The principle of low coupling approximation

We have seen above in passing from (5) to (6) that, in the limit of low coupling k, the transfer functions conveniently factor into a product of three terms, namely a transfer function that depends only on tag parameters, a transfer function that depends only on reader parameters, and the constantkLALT. This is in fact a consequence of a general principle that we state and derive in this section. In section 7 we shall have another opportunity to apply it.

Consider the interaction between the reader antenna and an HDX tag as represented in the upper left side of figure 7. The principle of low coupling approximation states that in the limit of low coupling k, the tag may be replaced with a voltage source in series with the reader antenna coil, the Laplace transform of the voltage produced by that source being given by


For the derivation we start by replacing the coupled coils LA and LT by the equivalent circuit consisting of the leakage inductance (1 – k2)LA, the magnetizing inductance k2LA and the ideal transformer with voltage ratiokLA/LT:1.

Figure 7.

Steps in deriving the principle of low coupling approximation

In the second step we reflect to the left of the transformer everything found to its right. In this way the voltage source VT gets multiplied by the transformer voltage ratio, the impedance ZT gets multiplied by the square of the latter ratio, and we get rid of the transformer. In the third step we replace that part of the circuit enclosed in the rectangle by its Thevenin equivalent, consisting of a voltage source in series with an output impedance. In the original circuit we had a voltage source in series with a voltage divider formed by two impedances k2LA and k2(LA/LT)ZT. The new voltage source produces the voltage at the open-circuited output of the voltage divider, while the new output impedance is the parallel combination of the impedances forming the divider, and hence equals k2 times the parallel combination ZP of LA and (LA/LT)ZT.

All transformations so far were equivalent transformations and no approximation was made. The low coupling approximation comes at this final step, and consists in replacing, for low k, (1 – k2)LA by LA and ignoring k2ZP. In this way we arrive at the approximate circuit in the lower left side of figure 7.


6. Adding the HDX protocol to the FDX current-driven reader

As already mentioned, the tap point connection is no longer available in the current-driven reader. The voltage-driven reader is connected via a three-wire cable to the end points and to the tap point of the antenna circuit, while the current-driven reader is connected via a two-wire cable only to the end points of the antenna circuit. Consequently, a different HDX topology is needed for the current-driven reader, which is presented in figure 8.

Figure 8.

Adding the HDX protocol to the current-driven reader

One remarks first that the newly added part of the schematics is connected to the existing part via two MOS transistors with low on-resistance. The transistors have their sources tied together with their parasitic diodes back-to-back so that the unwanted conduction through them is eliminated. The reader is powered from a positive source VCC and a negative source VSS. The voltage present on the antenna, which is sensed by the reader for decoding the data sent by the tag, is confined to the range from VSS to VCC. Therefore, in order to cut off both transistors, it is enough to apply the most negative voltage VSS to their gates tied together. For this reason, unlike to the voltage-driven reader where the gate of the MOS switch can be driven directly by uC, a gate driver is needed here to provide the positive voltage for turn on and the negative voltage for cut off. When the reader works in FDX mode, the transistors are cut off so that the HDX part of the schematic is isolated and plays no part. The transistors are also cut off during the charge phase of the HDX protocol, when the reader drives the constant amplitude current at the nominal frequency fC through the antenna. At the end of the charge phase, the reader stops driving the antenna and turns on the MOS transistors; since the current source presents high impedance to the antenna circuit, the latter is now closed through the transistors. The voltage induced by the tag on the antenna is amplified by the opamp connected in the inverting configuration, with a much higher gain than in the voltage-driven case since now we lack the amplification that was provided by the tap point. There is a high pass filter at the output of the opamp, with the purpose of eliminating any DC component in the signal; such a DC component may occur because the high gain that is used may amplify any non-ideal characteristic of the opamp such as input offset voltage.

There are now two options for decoding the amplified and filtered signal. One of them is to use the same decoder IC as in figure 4.

Figure 9.

Analog to digital interface for a bit decoder

Another option is to build a custom decoder that splits the task of data retrieving between a hardware part, built with discrete components as in figure 9, and a software part, included in the uC program. The input is limited by diodes D1 and D2 and then shifted by the high pass filter formed by RFILT and CFILT to an AC voltage with a DC component equal to the reference provided by voltage source VCC/2. The output of the filter together with the reference voltage is applied to the comparator. Shifting the AC voltage is necessary since the comparator admits only positive voltages at its inputs. The output of the comparator is a square wave whose frequency toggles between two values, as determined by the tag. This signal goes to an input line of uC, which is connected to an internal timer. The timer is programmed to run at a certain frequency, 24 MHz in our case. Each raising transition on the input line causes the value of the running counter of the timer be stored in a register and then the counter be reset. At the same time, the transition triggers an interrupt to uC. The uC interrupt routine reads the value of the register and stores it in memory. After the whole record is stored, the uC uses the stored values as estimates of the period of the signal coming from the tag and divides the record into intervals of high, respectively low frequency, according to whether the values are below, respectively above a certain threshold. Ideally, an interval of high frequency containing N values should correspond to a sequence of exactly N/16 zero bits in the tag response. In practice, there are errors caused by noise, so that correction algorithms should be used. The performance of these algorithms is one of the factors on which the reading distance depends. This is one reason for preferring the custom-built decoder to the decoder IC: the latter is a black box to the reader designer and one has no control over its internal decoding algorithms.


7. Using the gain-bandwidth product in the equalization of HDX bit amplification

Because the reader antenna circuit is tuned to the resonant frequency fC, the two signaling frequencies used by the tag may induce voltages whose amplitudes differ in a significant way. Consider the transition between a zero bit and a one bit. The zero bit is transmitted at the resonant frequency fC of the antenna circuit and hence the resulted signal at the reader is of high amplitude. The tag then shifts to the lower frequency fLOW that is outside resonance, resulting in a signal of lower amplitude. The transients that are triggered by the transition have a frequency close to fC and in general start with an amplitude close to that of the signal before the transition. If the signal after the transition has significantly lower amplitude, the transients will have a greater chance to disturb the decoding of the latter signal (figure 12); this effect is especially manifest at higher reading distances when the whole signal is weak, imposing thus a limitation on the reading distance if not taken care of properly.

We present a method for equalizing the bit amplification based on the one-pole model of the opamp and the related gain-bandwidth product (Gray & Meyer, 1993). The one-pole model assumes that the transfer function between the differential voltage at the input and the voltage at the output of the opamp is given by


By definition, the gain-bandwidth product is the product between the DC gain A0 and the 3 dB frequency p1/2π. Consider the opamp in the inverting configuration as in figure 10.

Figure 10.

Inverting amplifier

Assuming that there is no current into the inverting input, the current law gives (VIVX)/Z1 = (VX + A(s)VX)/Z2. Solving for VO = –A(s)VX gives, taking into account (11),


Because A0 is in general high, we may neglect 1/A0 in the above formula. Using the notation ωGB for A0p1, that is, 2π times the gain-bandwidth product, we obtain


Let us again consider interaction between reader and tag represented in the left side of figure 11 in the limit of weak coupling, in which situation we may apply the approximation principle of section 5 and replace the tag by a voltage source with Laplace function (10) in series with the reader antenna, as in the right side of figure 11. We may then use (12) in which we set Z1 = LAs + RS + 1/CAs and Z2 = R2, where RS denotes the total resistance in series with the antenna, that is, RA in series with R1 in figure 8.

Figure 11.

Replacing the tag by the equivalent source in the limit of weak coupling

The output voltage VOUT can be written as the product between the voltage VT of the source in the tag and the gain functions GT and GR, with the remark that the dependence of s = jω had been moved from the numerator of (10) to the numerator of GR:


We want VOUT to have the same amplitude for ω = ωC and ω = ωLOW (= 2πfLOW), which translates into the equality of absolute values |VOUTC)| = |VOUTLOW)|. We assume that VT keeps constant its amplitude when switching between ωC and ωLOW, hence |VTC)| = |VTLOW)|. We also assume that by design, the quality factor of the tag is low enough to neglect the variation of the absolute value of GT when ω varies around ωC; however, we still have to consider the variation with frequency of the factor s = jω in the numerator of (10) whose presence accounts for the magnetic coupling and for this reason we have moved it to the numerator of GR. We now make the following approximations for GR. First, since ω takes values around ωC and we shall assume ωGB much larger than ωC, we may neglect the term LAjω/ωGB in comparison with LA. Second, the required high gain asks for a resistance R2 much higher than RS, so that we may neglect RS in the sum RS + R2. We arrive at following approximation of the gain GR


in which the inductance LA appears as augmented by the quantity R2GB, RS as augmented by 1/CAωGB while the capacitive term 1/CAjω is not changed. Consequently, the resonant frequency of the compound circuit antenna plus amplifier appears as diminished with respect to the nominal resonant frequency fC of the antenna circuit. We now have to determine R2 so that the two signaling frequencies fC and fLOW employed by the tag are equally amplified by the above transfer function. This brings us to the general problem that given a transfer function of the form jω/Z(jω), where Z(jω) = j(Lω – 1/Cω) + R is the impedance of a series LRC circuit, find the condition for two frequencies ω1, ω2 to be equally amplified by the function, that is, |ω1/Z(jω1)| = |ω2/Z(jω2)|. If we had not jω in the numerator, the condition would be, as well-known, ω1ω2 = ωr = 1/LC, ωr being the resonant frequency of the LRC circuit. However, because of that numerator, the condition is here different and to find it we start by squaring the moduli and inverting the fractions, which leads us to


Then some straightforward algebra gives the required condition as


where Q = Lωr/R is the quality factor. Applying the above condition to (13) yields for the choice of R2


where QS = LAωC/RS is the quality factor of the antenna circuit. For the present choice, the amplifier gain is reduced from its maximal value of R2/RS corresponding to an infinite gain-bandwidth product, to the value


where RS = RS + 1/CAωGB. In our design we use the LT1224 opamp for which a gain-bandwidth product of 45 MHz is specified. For LA = 1 mH and QS = 21, (14) gives a resistance of 25.4 KOhms and an amplification of 294. The results in figure 12, based on a simulation to be described in section 9.1, make use of these values and confirm the theoretical prediction; truly the employed QS is in excess of that recommended by (8) but it was nevertheless used in order to clearly display the effect of inequal bit amplification that is magnified by a higher QS.

Figure 12.

Left: unequal amplification of bits. Right: equalization of bit amplification. Upper traces show voltages VOUT, lower traces show transients. Frequency transition at 500 us.


8. A simulator for FDX and HDX tags

Why do we need simulators? Because, during the development of a reader, we may need to generate in a systematic and reproducible way situations that with real transponders occur only randomly and unpredictably. Such a need may arise in connection with the following tasks: testing the system response (antenna plus reader) to signals from tags; testing the behavior of demodulation hardware and decoding software of the reader; generating test data for the information system in which the reader is to be integrated.

The first author’s work on simulators started in collaboration with Frosch Electronics (Vuza & Frosch, 2008; Vuza et al., 2009) and responded to the need of simulating a forthcoming tag not yet available by the time when a reader had to be developed. It continued with the work (Vuza et al., 2010a) that presented the general principles of a multifunction simulator intended for both FDX and HDX tags and realized as a stand-alone PC-configurable device. The simulator covered the case of “transponder talks first” (TTF) tags, meaning tags that transmit data as soon as they are powered by the reader, which is opposed to the “reader talks first” mode, where the tag transmits only in response to a command from the reader. The simulator described here was presented in (Vuza et al., 2010b) as a further elaboration of the preceding one. It is based on the AT91SAM7S64 micro-controller (uC), which provides the signal and data processing capabilities for the communication both with the reader to which it simulates the tag, and with a standard PC for the purpose of configuration. In our application, the software programmed into uC addresses the simulation of tags compatible with the FDX transponder EM4102 (EM Microelectronic-Marin SA, 2005) and the HDX transponder TIRIS (Texas Instruments, 2003). Of course, many other cases can be addressed by programming the adequate software. We start by describing the functioning of the analog part. With reference to figure 13, FDX/HDX, FREQMOD and LOADMOD are inputs from uC while CLOCK is an output to uC. As it will be indicated below, the antenna circuit should be tuned to the nominal FDX frequency in order to achieve the maximal amplitude of the baseband signal decoded by the reader. One sees that the resonance capacitor CS is not connected directly to ground but to inverters INV1 and INV2. Their role will be explained in section 8.2 on simulation of HDX transponders.

Figure 13.

Schematic of the analog part of the simulator

The output of INV1 is tristateable and the input and tristate pins are connected together. For load modulation, RM is switched in and out by transistor Q1. D1 prevents inverse current through Q1. Attached to the antenna circuit is the circuit that converts the RF signal from the reader into a digital clock. When the reader antenna is powered, an RF voltage is induced in the simulator antenna circuit. This voltage, which has a zero DC component, is limited by diodes D2 and D3 and then shifted by the high pass filter formed by RFILT and CFILT to an RF voltage with a DC component equal to the reference voltage provided by R2, R3 and Q2. The output of the filter together with the reference voltage is applied to the comparator. Shifting the RF voltage is necessary in order to use a single power supply: if the original voltage was fed to the comparator, the latter would have needed a positive and a negative supply. The comparator converts the shifted RF voltage into a square wave, which is fed to an internal counter of uC; R5 is a pull-up resistor needed by the comparator. An internal timer based on the uC clock generator is used for measuring the frequency of the square wave. If the latter matches, with a certain tolerance, the frequency imposed by the standard (either 125 KHz or 134.2 KHz), an optical indicator is activated for signaling the presence of RF power from the reader. The square wave is also used by uC as a clock for synchronizing the data transmission with the reader RF signal, as described in the next section.

8.1. Simulation of FDX tags

When simulating FDX tags, the lines FDX/HDX and FREQMOD are driven high by uC. In this situation, the output of INV1 is active and, through it, the pin of the resonance capacitor is connected to ground. The uC waits for the RF signal from the reader that is supposed to power the tag. As soon as this signal is detected by the procedure explained above, the simulator starts the data transmission, which lasts as long as RF power from reader is maintained.

Transmission is achieved with the aid of load modulation and uC can be programmed to use one of several bit-encoding schemes, among of which Manchester and Biphase (figure 14). As an example, let us explain how data is transmitted using Manchester encoding. A bit consists of 64 cycles of the reader RF signal. As we have seen, the latter is converted to a digital signal that clocks an internal counter of uC. The counter is programmed to reset automatically after each 64 clocks. The hardware is also programmed to do two things when the counter reaches the 32-th clock after each reset. First, it toggles the LOADMOD line, creating thus the transition in the middle of the Manchester bit. Second, it triggers an interrupt to the uC program. The interrupt routine will program the hardware to either set or reset the LOADMOD line by the time when the counter would reach the 64-th clock, according to whether the next bit to be sent is one or zero.

Figure 14.

Methods of bit encoding. Traces show the digital signal on the LOADMOD line.

Figure 15.

Interaction between current-driven reader and simulator

We indicate now why it is necessary to tune the antenna circuit to the frequency fC. In figure 15 we show in a simplified way the interaction between a current-driven reader and the simulator in FDX mode. Load modulation is achieved by switching in and out resistor RM. L, R and C are the parameters of the antenna circuit of the simulator, M is the magnetic coupling between the reader and simulator coils and RI denotes the lumped input resistance of other circuits attached to the antenna circuit. It was shown in (Vuza et al., 2010a) that the maximal signal amplitude that can be achieved at the reader by synchronous demodulation of the load modulation is given by


where we have setΔ=1LCωC2, R1 = RI and R2 = RI||RM. We see that a higher amplitude is achieved when Δ = 0, that is, when the antenna circuit of the simulator is tuned at fC.

Figure 16 shows the baseband signal decoded by the reader and representing a sequence of Manchester encoded bits sent by the simulator. For comparison the baseband signal received from a real tag is shown. One may remark the similarity between them.

Figure 16.

Upper: baseband signal from simulator in FDX mode retrieved by reader. Middle: digital signal on simulator LOADMOD line that generated the upper trace. Lower: baseband signal retrieved from an FDX tag.

8.2. Simulation of HDX tags

For HDX tags the simulator has to reproduce the two steps of the process: charge and transmission. For the charge step, the simulator only has to detect the start and the end of the reader RF pulse, as it has its own supply and does not need to store energy from the reader. The detection is accomplished with the procedure described in the introduction to section 8. During this procedure, the FDX/HDX and FREQMOD lines are set as in section 8.1. As soon as the end of the charging pulse is detected, the FDX/HDX line is driven low by uC. This has the effect of putting the output of INV1 in the high Z state. The antenna resonant circuit is now driven by the output of INV2 and becomes a transmission circuit. RLIM has the role of limiting the current supplied by INV2. The value of RLIM is typically ten times that of RS. This explains why INV1 had to be used: if current limitation would be achieved with RS instead of RLIM, then the amplitude of the baseband signal decoded by a reader when receiving from the simulator in FDX mode would be substantially reduced as one may see from (15). Hence RLIM is shorted out by INV1 when the simulator works in FDX mode and the only resistance left in the antenna circuit is represented by the resistance of the antenna coil together with RS. The latter is added in order to damp the transients that otherwise could have deleterious effects on the data decoding at the reader, as discussed in (Vuza et al., 2009). Data is transmitted with the aid of frequency modulation. The FREQMOD line is driven by an internal uC timer that generates a digital signal of programmable frequency. Besides driving the FREQMOD line, the timer is also programmed to clock a uC counter. The latter is set to trigger an interrupt every 16 clocks. The interrupt routine programs the frequency (fC or fLOW) of the timer that will be in effect during the next 16 clocks, according to the value (0 or 1) of the next bit to be sent. In agreement with the description in (Texas Instruments, 2003), the uC has to use the following data format in order to simulate a HDX tag of TIRIS type: 16 leading zero bits, a start byte equal to 0x7F, 64 data bits, 16 CRC bits, a stop byte equal to 0x7F, 16 trailing zero bits.

8.3. Connectivity

The data to be transmitted to the reader is stored in the internal non-volatile memory of uC. Therefore the simulator is a stand-alone device. However, for the purpose of configuration, the simulator can be connected to a PC. The configuration process allows the modification of the data to be sent to the reader, the choice of protocol (FDX or HDX) and, in the FDX case, the choice of bit encoding (Manchester or Biphase). The communication between the simulator and the PC is achieved either via the RS232 serial link or the USB link. The latter takes advantage of the USB transceiver embedded into the uC. The simulator may be powered from a battery or from the USB port when connected to a PC.

8.4. Applications

The simulator is a useful device for the process of customization and tuning the RFID hardware and software as it allows doing things that would be difficult or even not possible with real tags.

The two kinds of tags considered here, FDX and HDX, are typically used in access control and animal identification. They transmit to the reader data consisting of several fields that will be used as keys in databases containing information about the identified subject. The simulator offers a quick way to test the functioning of the database system for arbitrary values of the data fields, without the need of disposing of large collections of pre-programmed tags.

Another application is simulating anomalous tag behavior. During the realization of their joint work, the authors of (Vuza & Frosch, 2008) observed that some FDX tags have the tendency to skip some cycles of the reader RF signal during data transmission. A Manchester bit would then appear to the reader as containing, for instance, 65 RF cycles instead of the nominal 64. A well-designed decoding algorithm in the reader should be able to handle this situation. The simulator may be programmed to skip cycles on purpose in order to test the behavior of the reader decoding algorithms.

Finally there are the important applications of the simulator to the study of transient effects and of equality of bit amplification, to which we dedicate the next section.


9. Usage of simulators in studying the effects of transients in the HDX protocol

In testing a HDX system, it is important to find the behavior of the combined system reader plus antenna in response to the transition from one frequency to another. Consider the interaction between reader and HDX tags as presented in figure 11. The schematic is that of a linear system whose input is the voltage source VT internal to the tag and the output is the analog signal VOUT that is to be taken by the reader for further processing. Assume that up to moment t0, VT produced a square wave of frequency f1, to which the system responded with a steady-state periodic signal of the same frequency at the output. At t0, VT switches to a new frequency f2. Recalling the discussion in section 4, the output will be the sum of two parts after the transition: the new steady-state response corresponding to the new input and the transients induced by the frequency change. The transients vanish gradually so that the output is evolving towards the steady-state response. The problem for the reader designer is to ensure that the transients would vanish quickly enough in order not to disturb the bit decoding. Observing the frequency transition is not easy on a scope, as the frequency difference is rather small compared to the nominal frequency. Generated transients make the transition gradual and because of this it is difficult to estimate when the transition actually started; not having access to the interior of the tag implies not knowing the moment when the tag changed the frequency. For these reasons it is more convenient to use simulators rather than tags in assessing the effects of transients in the reader design. The method we propose for visualizing the transient relies on the following considerations. Let VIN12 be the input consisting of a square wave of frequency f1 before t0 and of a square wave of frequency f2 and of same amplitude after t0. Let VIN2 be the input consisting of a square wave of frequency f2 and of same amplitude as VIN12 and let VOUT12, VOUT2 be the respective outputs of the system corresponding to the defined inputs. Then the transient in the system response induced by the frequency change can be obtained as the difference between VOUT12 and VOUT2, provided one condition holds: VIN12 and VIN2 must be aligned so that they overlap after t0, that is, VIN12(t) = VIN2(t) for tt0 (figure 17).

Figure 17.

Alignment of input signals VIN12 (upper) and VIN2 (lower) fed simultaneously to identical copies of the system

9.1. Watching transients with the aid of a PSpice simulation

We may dispose of two identical copies of the system, which are fed simultaneously with the inputs VIN12 and VIN2. This is the principle on which relies the PSpice simulation that we propose as a CAD tool to be used during reader design. Its aim is to provide a graphical display of transients, allowing thus to estimate their duration and magnitude and to assess their effects on the received signal. The two copies of the system are produced with the aid of PSpice hierarchical blocks in order to avoid duplication of the schematic: any modification to the schematic is automatically reflected in both copies. The blocks are fed with the inputs VIN12 and VIN2. The outputs go into a difference block that isolates the transient from the output VOUT12 by subtracting the steady-state response VOUT2. We illustrate the above method with the simulation that was used for producing the results on equalization of amplification of HDX bits presented in section 7. Figure 18 shows the schematic of the composite system reader plus tag. The tag is represented on the right side as a tuned antenna circuit driven by the voltage present at the input port. A current-driven reader is represented on the left side and consists of the tuned antenna circuit and the amplifier, which produces the signal available at the output port.

Figure 18.

Schematic of the composite system reader-tag used in simulation

Figure 19.

Simulation of transients in the composite system

The amplifier is based on an opamp connected in the inverting configuration. Two gain blocks and an RC low-pass filter are used for simulating an opamp with a DC gain of 100000 and a gain-bandwidth product of 45 MHz. The reader and tag antennas are magnetically coupled, with a coupling constant k = 0.01. Figure 19 shows the schematic of the simulation. The two copies of the system are represented by the hierarchical blocks RT1 and RT2. The input to RT1 consists of a square wave of frequency fC up to time t0 and of a square wave of frequency fLOW after t0; the two square waves are combined into a single signal with a summing block. The input to RT2 consists of a square wave of constant frequency fLOW. Delays TD are used in order to properly align inputs RT1 and RT2 as in figure 17. The difference block used for isolating the transient is followed by a multiplication block. The purpose of the latter is to eliminate the part of the graphical display of the transient that precedes the transition time t0, as it has no meaning for the simulation. The equal bit amplification seen in figure 12 is achieved by choosing R2 according to formula (14). If the RC filter is removed from the opamp schematic, the gain of the amplifier does no longer depend on frequency and the frequency dependence of the overall gain is set by the antenna circuit. In this situation one obtain the unequal amplification seen in figure 12.

9.2. Watching transients with the aid of the tag simulator

In practice we may not always dispose of copies of the system and much less of identical copies. We may however successively feed the inputs VIN12 and VIN2 to the same system and make use of time invariance. Suppose that we first feed VIN12 that was described above and with the aid of a recording device such a scope, we take a record of VOUT12(t) in the interval from t0a to t0 + b. Then at a later time we feed VIN2 and we take a record of VOUT2(t) in the interval from t1a to t1 + b. We do not assume that the alignment condition of figure 17 holds, which was meaningful for the case of inputs fed at the same time to identical systems. Instead, we assume the equality VIN12(t) = VIN2(t + t1t0) is satisfied for each tt0 (figure 20). If we define the time displaced input VIN2D(t) = VIN2(t + t1t0), then VIN12 and VIN2D satisfy the alignment condition of figure 17 and hence the difference of the corresponding outputs VOUT12 and VOUT2D would produce the transient we look for. By time invariance, VOUT2D(t) = VOUT2(t + t1t0). Consequently, the transient is obtained as the difference VOUT12(t) – VOUT2(t + t1t0) between the records taken by the recording device.

Figure 20.

Upper: input signals VIN12 and VIN2 fed one after the other to the same system. The traces above the signals show the trigger provided by the simulator. Lower: signals superimposed for displaying overlap condition

One has still to ensure that the device would use the recording intervals (t0a, t0 + b) and (t1a, t1 + b) which are properly aligned with respect to t0 and t1. For this purpose, our simulator provides a separate output line that may be used as a trigger by the recording device. In the first step of the recording process, the simulator produces the signal VIN12 together with a raising transition on the trigger line at the moment t0 when the frequency changes. In the second step, the simulator produces the signal VIN2 together with a raising transition on the trigger line at some moment t1 corresponding to a raising edge in VIN2. If the recording device allows computations with stored waveforms, one may use it for displaying the transient as the difference between the records of VOUT12 and VOUT2. Or one may transfer the records on a PC and use CAD tools such as PSpice for displaying the difference. Assuming that one uses a scope with memory and arithmetic capabilities and that one wishes to visualize the transient at the transition between fC and fLOW, the algorithm for displaying the transient would be the following.

  • Set up the scope for displaying the difference between channel 1 and memory record on the math channel.

  • Set up the scope in single sequence (one shot) mode with trigger on channel 2 that records the trigger signal provided by the simulator.

  • Generate with the simulator a signal of constant frequency fLOW, record the reader response and store it to scope memory.

  • Generate with the simulator a signal of that changes frequency from fC to fLOW and record the reader response on channel 1.

  • The transient shows on the math channel.

Figure 21.

Effect on transients on bit decoding. Upper traces: signal amplified by reader. Middle traces: transient induced by transition (note that only the part that follows the transition represents the transient). Lower traces: trigger at transition provided by simulator.

In figure 21 we show the result of the application of the described algorithm to the study of the effects of transients on data decoding. The onset of the frequency change is marked by the raising transition on the trigger line provided by the simulator. Knowing the start time of the new bit, one may precisely demarcate the bit interval which here is shown enclosed between the vertical cursor lines. In the left side was recorded a transient of normal duration and the bit was correctly decoded by the decoder IC. The right side shows a transient of abnormally long duration produced by a reader antenna with a too high Q, which resulted into incorrect decoding by the bit decoder IC. In figure 22 we show how the simulator may be used for assessing the amount of equalization of bit amplification by the procedure described in section 7.

9.3. A Low cost alternative for the tag simulator

In the case of readers that achieve bit decoding with a dedicated IC, a low-cost alternative for the simulator is available, that may be used for testing system response and bit decoding. The only hardware of the simulator consists of just a resonant antenna circuit to be plugged in an output port of the reader (figure 23). In this case, the AT91SAM7S64 uC already existent in the reader provides the software component (program) and hardware

Figure 22.

Scope visualization of frequency transition generated with the tag simulator, after application of equalization of bit amplification. Traces have same meaning as in figure 21.

components (timers and interrupts) needed by the simulator simultaneously with the function of receiving the data from an IC specialized in decoding the answer of an HDX tag. In other words, the reader is receiving the data simulated by itself, which saves the cost of a stand-alone board for the simulator with its own controller, power and communication components. Other hardware components such as the carrier detector are no longer needed, as the reader knows of course the moment when the charge phase ends. In fact the only purpose of such a “charge phase” is to inform the decoder IC that a new decoding phase is to be started. Subsequently the reader uC starts driving the simulator antenna with a preloaded bit pattern. As the simulator and reader antennas are magnetically coupled, the bit pattern transmitted by the reader uC is received by the decoder IC, which sends the decoded bits back to the reader uC. Thus, two tasks are simultaneously performed by the reader uC – driving the simulator antenna and receiving the decoded bits, which is possible by using the system of prioritized interrupts.

Figure 23.

Simulation plug-in added for test purposes to the current-driven reader


10. Conclusion

We presented two procedures for adding HDX functionality to an existing FDX reader, together with some design issues that influence the reader performance. All these originated in our joint work of developing and producing new readers. We applied the proposed design procedures and tools to the development of an expanded version of the portable voltage-driven proximity reader that is now able to read HDX tags up to 16 cm and of an expanded version of the current-driven long-range reader that can read HDX tags up to 60 cm. In both cases, it was the tag activation, not the reception, which limited the reading distance. The simulator here described, intended to assist the reader developer and the system integrator, allowed us to conveniently perform test and tuning procedures that would have been difficult or nearly impossible with real transponders.


  1. 1. EM Microelectronic - Marin SA 2005 Read Only Contactless Identification Device. Available from
  2. 2. GelinotteE.FroschR.VuzaD. T.PascuL. 2006 An RFID Reader Based on the Atmel AT91SAM7S64 Micro-Controller, Proceedings of the 1st Electronics Systemintegration Technology Conference, 11581165 , 1-42440-552-1 Germany, September 2006
  3. 3. GrayP. R.MeyerR. G. 1993 Analysis and Design of Analog Integrated Circuits, 3rd ed. John Wiley & Sons Ltd, 0-47157-495-3 York, USA
  4. 4. International Organization for Standardization 2007 Radio Frequency Identification of Animals, ISO/DIS 142231 , Part 1: Air Interface
  5. 5. Texas Instruments 2003 TMS3705A Transponder Base Station IC, Rev. 1.1. Available from:
  6. 6. VuzaD. T.FroschR.KoeberlH. 2007 A Long Range RFID Reader Based on the Atmel AT91SAM7S64 Micro-Controller, 30th ISSE 2007 Conference Proceedings, 445450 , 1-42441-218-8 Romania, May 2007
  7. 7. VuzaD. T.FroschR. 2008 Simulation of Multiple ISO/IEC 18000-2:2004 Transponders with the AT91SAM7S64 Controller, SIITME 2008 Conference Proceedings, 4145 , 1843-5122 Predeal, Romania, September 2008
  8. 8. VuzaD. T.FroschR.KoeberlH.BoissatD. 2009 A Low Cost Anticollision Reader, In: Development and Implementation of RFID Technology, C. Turcu, (Ed.), 201216 , I-Tech, 978-3-90261-354-7 Vienna, Austria
  9. 9. VuzaD. T.ChiţuS.SvastaP. 2010a An RFID Tag Simulator Based on the Atmel AT91SAM7S64 Micro-Controller, 33rd ISSE Conference Proceedings, 229234 , 978-8-37207-874-2 Warsaw, Poland, May 2010
  10. 10. VuzaD. T.ChiţuS.SvastaP. 2010b An RFID Tag Simulator for the FDX and HDX Protocols, 16th SIITME 2010 Conference Proceedings, 5358 , 978-6-06551-013-5 Piteşti, Romania, September 2010
  11. 11. VuzaD. T.FroschR. 2010 RFID Readers for the HDX Protocol- Design, Simulation and Testing, 16th SIITME 2010 Conference Proceedings, 4752 , 978-6-06551-013-5 Piteşti, Romania, September 2010

Written By

Dan Tudor Vuza and Reinhold Frosch

Submitted: October 15th, 2010 Published: July 20th, 2011