Voltage distortion limits.

## Abstract

With the growing use of DC voltage for power transmission (HVDC) and DC links for efficient AC motor drives, the R&D efforts are directed to the increase of DC/AC converter’s efficiency and reliability. Commonly used DC/AC converters, based on the carrier-frequency pulse-width modulation (PWM) to form a sinusoidal output voltage with a low level of higher harmonics, have switching time and switching loss issues. The use of multimodule multilevel converters (MMC), operating with the fundamental switching frequency and phase-shift control to form the ladder-style output voltage, reduces switching losses to minimum while keeping the low level of higher harmonics in the output voltage. The discussed sequential harmonic elimination method for MMC, using identical power modules operating with 50% duty cycle and fundamental frequency, is based on the combination of the multiple fixed phase shifts to form a ladder-style sinusoidal voltage with low total harmonic distortion (THD) and symmetrical variable phase shifts to control the output voltage amplitude. The principles of the sequential selective harmonic elimination for MMC topology and amplitude control are described with two examples. The first example is the industrial-frequency DC/AC converter complying with THD requirements of IEEE 519 2014 standard without the output filter. The second example is a high-frequency converter, used as a transmitter, loaded with the resonant antenna, where the evaluation criteria are decreasing of the transmitter losses and increasing of the reliability or life expectancy at elevated temperature.

### Keywords

- amplitude control
- selective harmonic elimination
- staircase modulation
- Chireix-Doherty amplitude modulation
- DC/AC converter
- high temperature
- multimodule multilevel converter (MMC)
- multivector control
- outphasing
- phase-shift modulation
- reliability
- life expectancy

## 1. Introduction

The conversion of DC voltage into sinusoidal AC voltage at power levels from kilowatts to megawatts with low power losses and low higher harmonics in the output voltage is a common task for modern power engineering. Multimodule multilevel converter is the best approach to generate the high-power sinusoidal voltage from HVDC bus for electrical grid consumers, propulsion electrical motor drives, etc. High-efficiency switch-mode modules, used to synthesize sinusoidal output voltage, may operate at the fundamental frequency of the sine voltage, required for the load, or at higher frequencies (the carrier frequency) using the pulse-width modulation to reduce higher harmonics of the fundamental frequency. In the last case, the output filters, required for reducing total harmonic distortion (THD) of the output voltage to the acceptable level, are significantly smaller [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20].

The biggest problem with the phase-shift pulse-width modulation, providing the highest quality of the output sinusoidal voltage with minimum switching losses, is its control methodology, which requires complicated calculation of the necessary phase shifts in real time [8, 21, 22].

In this paper a simple method of the sequential selective harmonic elimination and amplitude control is discussed. It is based on the combination of the fixed precalculated phase shifts/delays for harmonic elimination and variable phase shift for amplitude control. Application of this method is illustrated using two examples—the industrial-frequency DC/AC converter and the high-frequency converter used as a transmitter for the nuclear magnetic resonance (NMR) oil/gas well logging tool, operating in harsh conditions. LTspice was used for simulation in time and frequency domains. A simple expression is provided for the resulting THD vs. the number of eliminated harmonics to comply with industrial grid voltage of THD standards without the output filter. For the NMR transmitter, decreasing of conductive losses due to the harmonic elimination reduces operating temperature and increases the reliability. Improvement of the life expectancy is calculated according to the Arrhenius equation for three transmitter cases with the same number of switches but with different harmonic contents.

## 2. Full-bridge module operation and spectrum of the output voltage

The building block or module for multimodule multilevel converter (MMC) is a full-bridge DC/AC converter utilizing maximum voltage and current ratings of the power switches S1–S4 (Figure 1), powered from bus V_{0}, producing rectangular voltage pulses with 50% duty cycle for maximum output power. The bridge load Z is connected directly to the bridge outputs or via the output transformer TX. For the industrial frequency 50 Hz–60 Hz and other low-frequency high-power applications, fully controlled thyristors are the best choice, while for the frequency range over few kilohertz, IGBTs are the preferred ones. Operation in the frequency range over 100 kHz requires fast-switching power MOSFETs. To simplify analysis of the following circuits, the switches are assumed to be ideal and have zero-switching time and zero internal losses.

The Fourier analysis provides the expression for the full-bridge symmetrical 50% duty cycle output voltage *V*_{out(t)} (Figure 1) as the sum of only odd harmonics *V*_{n} (n = 1, 3, 5, 7, etc.):

where *n* is the harmonic number (only odd harmonics 1, 3, 5, etc.), ω is the angular frequency, *V*_{0} is the full-bridge inverter DC bus voltage and *t* is time.

Each harmonic *n* has its amplitude *V*_{n} decreasing with the harmonic number *n*:

Spectrum of the bridge output voltage with amplitude of 1 V and frequency of 1 kHz is shown on Figure 2. The vertical axis represents the RMS values of each harmonic starting with the first one equal to 0.9Vrms (or 1.273 V peak value). Horizontal axis is frequency.

Converter output current *I*_{out(t)} is a combination of the fundamental harmonic and higher harmonics, each of them being a product of the harmonic voltage *V*_{n(t)} and load admittance *Y*_{n} for this harmonic:

Several load types such as resistive, inductive, capacitive and resonant ones have different current vs. frequency characteristics as shown in Figure 3, which is obtained in LTspice environment under 1 V sinusoidal test signal.

Only resistive load current replicates the spectrum of the input voltage. Inductive load decreases high-frequency current components, but capacitive and resonant loads significantly increase relative values of the high-frequency current harmonics compared to the spectrum of the applied voltage. Voltage harmonics and resulting currents affect both load and voltage sources (converter) in different ways. Excessive current harmonics increase power losses and create electrical noise (EMI) affecting electronic equipment.

Maximum voltage harmonic content for the industrial AC lines is regulated by IEEE 519 2014 standard [23, 24]. Limits for total harmonic distortion (THD) and maximum amplitude of the highest harmonic are provided in Table 1.

Bus voltage (V) at PCC | Individual harmonic (%) | Total harmonic distortion (THD) (%) |
---|---|---|

V ≤ 1.0 kV | 5.0 | 8.0 |

1 kV < V ≤ 69 kV | 3.0 | 5.0 |

69 kV < V ≤ 161 kV | 1.5 | 2.5 |

161 kV < V | 1.0 | 1.5 |

THD and individual harmonic maximum values are different for different line voltages. The power distributor should keep total harmonic distortion (THD) for voltages <1 kV under 8% and individual harmonic value less than 5% of the fundamental one at the point of consumer connection (PCC). In the process of conversion of HVDC bus voltage into lower-level AC, the switch-mode converters create higher harmonics as unwanted byproduct. For full-bridge DC/AC converter output voltage spectrum (Figure 2) of THD is 0.483 or 48.3% [25]. To comply with THD limits, the simple DC/AC converters include the output filters reducing higher harmonics to the acceptable level. Those filters introduce additional losses and have significant size, weight and cost especially if the filter has to remove harmonics starting with the third one, which is 150 Hz and 180 Hz for the EU and USA, respectively. Eliminating the most powerful higher harmonics from the output voltage in the process of DC to AC conversion and reducing the highest-frequency harmonic leftovers with a simple output filters are the most efficient ways to comply with THD standard.

For the high-frequency converters operating as transmitter with the resonant loads at elevated temperature, the output current’s higher harmonics cause additional heating, which results in the reliability problems. In this case the effectiveness of the harmonic elimination is reducing the power component temperature and increasing the converter life expectancy.

## 3. Multimodule converters and synthesis of the quasi-sinusoidal output voltage

Multimodule multilevel converters (Figure 4) have their outputs connected in series to produce the so-called modified sinusoidal voltage or ladder-style voltage (Figure 5). DC inputs may be connected in parallel with the transformer combining the output voltages or in series for HVDC converters or be floating, for example, powered from the photovoltaic batteries, depending upon the application. Each module operates with high efficiency producing rectangular pulses with controlled timing. The control algorithm for timing calculations is a subject of this analysis.

Commonly used control algorithms are based on the pulse-width modulated signals to control multiple modules. The module output voltages are added in series to form the ladder-style voltage with optimized width of each pulse to eliminate harmonics and to regulate output voltage as shown in Figure 5 (left). The discussed method was developed to operate the identical modules, producing 50% duty cycle pulses with the fundamental frequency and equal amplitude, combining their outputs in series and controlled by the phase shift only (Figure 5, right).

Equal ON and OFF time operation of all power switches has the following advantages:

Equal conductive losses

Guaranteed time to reset snubbers (if used to reduce switching losses)

Guaranteed time to build up the lagging current for soft switching (if needed)

Guaranteed time to recharge gate drivers (if needed)

## 4. Harmonic elimination based on the phase shift

Minimal configuration of the DC/AC multimodule converter includes two basic full-bridge modules with the output voltages connected in series. Their DC inputs may be connected in parallel to the same bus V_{0} or in series (this is used for HVDC lines to share input DC voltage according to the module maximum voltage rating).

To simplify analysis two identical modules are connected to the same DC bus, and their outputs are connected in series using two ideal output transformers TX1 and TX2 with transformer ratio 1:1 (Figure 6). The output voltages have identical amplitude and 50% duty cycle, and their relative position in time domain (delay or phase shift) is defined by the controller (not shown).

The relative phase shift (relative to the fundamental harmonic) equal to π/3 or 1/6 of the module operation period is shown in Figure 7. For the third harmonic, the relative phase shift is π, and combined output signal has the third harmonics subtracted or eliminated. All other odd harmonics like 9th, 15th, 21st, 27th, etc., which are multiples of three, are eliminated too.

Two identical periodic signals being combined with the phase shift *Φ* have eliminated harmonics *n* satisfying the following requirement:

Two module output voltages shifted π/3 and combined output without 3rd, 9th, etc. harmonics are shown in Figure 8. When two signals with eliminated 3rd harmonic are added with phase shift π/5, their combined voltage has eliminated the 5th harmonic and also 15th, 25th, etc. To eliminate the fifth and seventh harmonics, this process should be repeated as shown in Figure 9 where control signals to a set of eight modules are getting additional delay starting from sync pulse. This process may be continued to eliminate enough harmonics to comply with THD requirements or other special conditions [26, 27, 28, 29, 30, 31].

Total delays (or phase shift) *α*_{m} per module *m* of a set of modules *M* (Figure 9) may be calculated as scalar product of matrix *C* formed by assigned to each module *m* binary numbers (c = m-1) of the modules and set *Φ* of harmonic canceling delays *φ* = π/n:

Examples of delay/phase-shift calculation for the eight modules of MMC are provided in Table 2.

Module number (m) | Module’s assigned binary code (c _{m} = m-1) | nth harmonic phase shift in module (ϕ _{n} = π/n) | Total module phase shift (α _{m} = c_{m}·Φ) | Total module phase shift (α _{m)} | ||
---|---|---|---|---|---|---|

n = 7 | n = 5 | n = 3 | ||||

1 | 0 0 0 | 0 | 0 | 0 | 0 | 0 |

2 | 0 0 1 | 0 | 0 | ϕ_{3} | ϕ_{3} | π/3 |

3 | 0 1 0 | 0 | ϕ_{5} | 0 | ϕ_{5} | π/5 |

4 | 0 1 1 | 0 | ϕ_{5} | ϕ_{3} | ϕ_{5} + ϕ_{3} | π/5 + π/3 |

5 | 1 0 0 | ϕ_{7} | 0 | 0 | ϕ_{7} | π/7 |

6 | 1 0 1 | ϕ_{7} | 0 | ϕ_{3} | ϕ_{7} + ϕ_{3} | π/7 + π/3 |

7 | 1 1 0 | ϕ_{7} | ϕ_{5} | 0 | ϕ_{7} + ϕ_{5} | π/7 + π/5 |

8 | 1 1 1 | ϕ_{7} | ϕ_{5} | ϕ_{3} | ϕ_{7} + ϕ_{5} + ϕ_{3} | π/7 + π/5+ π/3 |

Number *M* of modules, needed for eliminating *K* harmonics

To find THD dependence on the sequential selective harmonic elimination using phase shift, seven harmonic elimination circuitries with different numbers of modules, marked A to G, were simulated. Example of circuitry topology marked as A, B, C and D, reference A full-spectrum single module and with eliminated third (B-2 modules), third and fifth (C-4 modules) and third, fifth and seventh (D-8 modules) harmonics are provided in Figure 10. More complicated circuits (E-16 modules, F-32 modules and G-64 modules) were also simulated.

THD for each simulated case (A to G) was calculated based on the RMS value of the simulated output ladder-style voltage *V*_{out} and RMS value of the fundamental harmonic *V*_{1} [25]:

The drawback of any kind of modulation is decreasing of the resulting fundamental harmonic *V*_{1}. Table 3 provides not only THD and maximum value of the biggest voltage harmonic left after multiple harmonic eliminations but also a change of the fundamental harmonic compared to expected value in case of all phase shifts, which were zero, and combined output voltage replicates 50% duty cycle output voltage of the single module multiplied by the number of modules.

Configuration | A | B | C | D | E | F | G |
---|---|---|---|---|---|---|---|

Number of modules | 1 | 2 | 4 | 8 | 16 | 32 | 64 |

Harmonics canceled + | 0 | 3 | 5 | 7 | 11 | 13 | 17 |

Phase shift per next module set | 0 | π/3 | π/5 | π/7 | π/11 | π/13 | π/17 |

Relative change of the first harmonic | 1.0000 | 0.8660 | 0.9511 | 0.9749 | 0.9898 | 0.9927 | 0.9957 |

Combined output value (Vrms) | 1.0000 | 0.8165 | 0.7528 | 0.7278 | 0.7167 | 0.7108 | 0.7076 |

First harmonic k value V_{1} (Vrms) | 0.9003 | 0.7798 | 0.7415 | 0.7229 | 0.7156 | 0.7103 | 0.7074 |

THD | 0.4834 | 0.3103 | 0.1752 | 0.1166 | 0.0575 | 0.0360 | 0.0238 |

Max higher harmonic number | 3 | 5 | 7 | 11 | 17 | 29 | 29 |

Max harmonic value (Vrms) | 0.3001 | 0.1559 | 0.0658 | 0.0526 | 0.0160 | 0.0127 | 0.0113 |

Max harmonic relative to the first harmonic | 0.3333 | 0.1999 | 0.0887 | 0.0728 | 0.0224 | 0.0179 | 0.0160 |

THD value vs. the number of eliminated harmonics starting from the third from Cases A to G is presented in Figure 11. The relative amplitude of the fundamental harmonic *V*_{1,k} after the first *k* higher harmonics are eliminated is calculated as

Multimodule converter with eliminated the first four harmonics (Case E, 16 modules) complies with IEEE 519 2014 [23] requirements for voltage <1 kV, with five eliminated harmonics (Case F) for 1 kV to 69 kV and with six eliminated harmonics (Case G) from 69 kV to 161 kV without using any output power line filters. Eq. (9) may be useful for approximate calculation of THD of the MMC output voltage after canceling the first *k* harmonics using this method:

Due to the buildup of the module output voltage phase shifts, the resulting quasi-sinusoidal voltage fundamental harmonic is shifted to ϕ_{ref} as shown in Figure 12 which should be taken into consideration and if necessary added to the carrier signal.

The additional phase-shift value ϕ_{ref} is calculated for MMC with M modules as

## 5. Amplitude control

MMC with fixed phase shifts produces low THD sinusoidal output voltage with the amplitude proportion to the DC bus voltage. To regulate the output voltage amplitude from zero to maximum without affecting the harmonic elimination results, two identical voltages V1 and V2 have to be combined with the variable symmetrical phase shift [32, 33] (Figure 13).

The variable phase-shift symmetry maintains stable phase of the resulting output voltage at the load during the amplitude regulation. This method (also known as outphasing) was originally developed for AM transmitters and assumed two sinusoidal combining voltages, now widely used for high-efficiency communication transmitters [34]. The amplitude of the combined output voltage *V*c depends upon the phase shift ϕ as shown on phasor diagram (Figure 13):

For the high-power applications, the switch-mode converters are used instead of the sine generators (Figure 14) where two sets of power modules Mod A and Mod B are controlled from two multiple outputs of fixed delay modules A and B. Delay modules may be shift registers or digital delay lines (for RF transmitters). Inputs of delay lines controlling leading vector A and lagging vector B are connected to the outputs of symmetrical phase-shift modulator with amplitude control voltage and sinusoidal carrier voltage inputs. The shown output transformers are the simplest way to combine output voltages and to form regulated output. For power conversion with the strict requirements to the harmonic content of the regulated sinusoidal voltage at the output, each of two DC/AC converters shall comply with those requirements, and the number of modules is chosen based in Figure 11 data.

Sinusoidal carrier voltage (not triangular or sawtooth voltage) provides linear modulation characteristic for the resulting fundamental harmonic, which allows direct control of the RF output pulses restored at the resonant antenna without the real-time negative feedback. In some cases the correction of the total system gain depending on the DC bus voltage may be done between RF pulses [29].

## 6. RF transmitter current harmonics and life expectancy

The simplified schematic of the two module switch-mode outphasing transmitters is shown in Figure 15 [35]. Two full-bridge converters, named leading and lagging, have their output voltages combined using their output transformers TX1 and TX2. The load is a resonant antenna consisting of the antenna inductor La, parallel-tuned capacitor Ca and resistor Ra representing antenna losses and defying antenna Q. The load impedance has its maximum at the operating frequency of the parallel resonance equal to Ra. For the higher harmonics of the output voltage, antenna impedance is capacitive and drops at higher frequency. Higher harmonics of the transmitter output current are limited by the output filters Lf and Cf. This filter is tuned to the series resonance at the operating frequency to introduce minimum output filter voltage drop which is proportional to the output current.

The transferring function transmitter output voltage to the antenna voltage is shown in Figure 16. The “saddle characteristic” has two poles reflecting two resonances at lower and higher frequencies than the operating frequency. The amplitude of those peaks depends upon the antenna and filter losses as shown for Q = 10 and Q = 100. The box at the operational frequency 0.5 MHz sets the acceptable system bandwidth which is necessary for correct restoring of the envelope of RF pulses used in NMR tools for the proton excitation. For RF pulses with Hann envelope with duration of 25us minimum bandwidth to correctly recover amplified antenna pulses, the bandwidth of the system output filter plus antenna should be 40 kHz minimum; with reliable margin for wide temperature range, it should be 80 kHz with flatness 5% or 0.5db (Figure 17).

Increase of the system bandwidth benefits the metrological parameters of the tool and accuracy in the replication of the shortest RF pulses, used for the hydrogen nuclei excitation, and makes possible to use the same filter for more than one frequency without the filter capacitor switched. But there is another drawback: the higher-frequency resonance (the right pole) amplifies higher harmonics of the output current due to the drop of the filter/antenna input impedance (Figure 18). The biggest harmonic in the 50% duty cycle module output voltage is the third harmonic, and the third harmonic of the output current may significantly exceed the amplitude of the fundamental harmonic. The smaller is output filter inductance the higher are values of the unwanted higher harmonics in the output current and the higher are conductive losses resulting in the component temperature rise. The output filter design is a compromise between the bandwidth and accuracy vs. losses and reliability. Higher harmonic elimination removes the cause of the excessive output current and significantly reduces power losses for the same number of switches [28].

To assess the advantage of the discussed harmonic elimination method, three 500 kHz transmitters operating identical loads (2uH, 52 nF output filter and 1uH, 100 nF, 90ohm, Q 30 antenna) and using the same number of power MOSFET switches (32 total) but different topologies and control signals corresponding to Case A, Case B and Case C configurations (Figure 10) were simulated for the standard for NMR pulse train with 25us and 50us Hann envelope, 1000Vmax and 20% duty cycle (Figure 19) [29].

Standard NMR excitation pulse sequence consists of the multiple identical pulses with the equal period and the first pulse with half duration and the same amplitude Vp =1000 V as shown on Figure 19.

The harmonics of the transmitter output current depend upon the voltage harmonics in the transmitter output signal. Figure 20 shows the values of the first seven most important harmonics of the output current for transmitters based on the simplest two module Case A configurations [35], four module-enhanced transmitter Case B with eliminated the 3rd harmonic [30] and eight module transmitter Case C with eliminated the 3rd and 5th harmonics. Proper waveforms of the leading or lagging voltages marked as A, B and C are provided in Figure 12. Elimination of higher harmonics decreases the total output RMS current *I*_{out} per switch and resulting conductive power dissipation *P*_{s}:

where *P*_{s} is the power switch total power dissipation, *P*_{sw} is the power of switching losses, *I*_{out} is the RMS value of switch current and *R*_{dson} is the switch resistance drain to source, which for silicon MOSFET is the function of the temperature and current [36].

Additional temperature rise *∆T*_{j} of the switch die over the ambient temperature *T*_{A} depends on the thermal resistance *R*_{th} from the switch die to the ambient temperature *T*_{A} and current *I*_{out}:

The die temperature *T*_{j} affects the switch life expectancy *t*_{v} according to the Arrhenius law:

where *t*_{v} is the switch life expectancy in time units, years or hours; *T* is the absolute temperature; *E*_{A} is the apparent activation energy in general depending on *T*, recommended value 0.8 eV [37]; *C* is a constant and *k* is the Boltzmann constant [38].

Additional temperature rise *∆T*_{j} decreases life expectancy at *T*_{j} by the accelerator factor (AF) compared to the life expectancy at *T*_{A}:

Implementation of the sequential harmonic elimination decreases output current and related temperature rise, which results into the improvement of the transmitter reliability in terms of the life expectancy. The life expectancy (shown in Figure 21) changes from 1000 h at 175°C, taken as a reference point, down to 296 h for Case A, to 770 h for Case B and to 788 h for Case C. All transmitters use 32 power MOSFET switches; the difference is in the topology, control method and number of the additional RF output transformers, which easily fit the pressure housing and do not generate significant amount of heat.

Switching from classic transmitter topology Case A to Case B increases life expectancy 2.6 times, from Case A to Case C—2.66 times. It is clear that Case B transmitter is the best solution in terms of reliability improvement vs. extra cost and complexity. The benefits include not only increases of the life expectancy but also increases of tool accuracy, improving EMI conditions in the confined space of the power train placed in the high-pressure housing due to the spread in time switch operation [29].

## 7. Conclusion

The sequential harmonic elimination provides a simple method of removing higher harmonics from the output voltage of the multimodule multilevel converters operating with the fundamental switching frequency and using identical modules, generating 50% duty cycle output voltages. A simple algorithm for the control circuitries used to eliminate harmonics and regulate output voltage from zero to maximum maintaining stable phase is discussed. A simple expression for THD of the output voltage vs. the number of eliminated harmonics, derived from simulation results, is provided for design evaluation against IEEE 519 standard requirements. The application of this method to the NMR transmitters operating in the high-temperature environment eliminates the most dangerous output current harmonics and shows more than twice the gain in the life expectancy. This method was validated for NMR downhole logging equipment, and two patents were granted.