Summary of device dimensions

## 1. Introduction

The analytical model and simulation numerical of semiconductor devices is one of the important steps for Integrate Circuit fabrication, veriﬁcation and characterization. Each semiconductor device has models that satisﬁes the requirements to the device under different operating conditions. GaAs MESFET is a promising semiconductor device used in many applications in the microwave domain. The elements which compose the MESFET transistors can be gathered in two distinct categories. There are extrinsic and intrinsic elements; the first category represents the different structures of access like the side resistances *Rs* and *Rd*. The intrinsic elements like the transconductance *gm* and drain conductance *gd* translate by their nature and their behavior localized of the device physical structure. Our main aim in these sheets related on the one hand to the optimization of a two dimensional (2D) analytical model for the static characteristics of short gate-length GaAs MESFET’s, this model takes into account the different physical specific phenomena of the device, and on the other hand to calculate the variation of some intrinsic elements (transconductance and drain conductance) as a function of the biasing voltages. The model suggested has enables to us to calculate and trace the different series from curves. The results obtained are well represented and interpreted.

## 2. General characteristics of the model

The major features of this study are:

To solve the system of the two dimensional partial differential equations, we based for the works of Chin and Wu (1992, 1993), the Green’s function technique is used in these references to solved the two dimensional Poisson's equation, this technique gives an acceptable distribution of the space charge and a form of the depletion area in agreement with the physical phenomena specific to this device.

To determine the depletion-layer width, we have considered first the one-dimensional approximation (Sze and Ng, 2007), then we add the corrective which results from the two-dimensional analysis.

To determine the electron mobility law in the semiconductor, we have considered that described by Chang and Day (1989).

To calculate the drain current expression as a function of the drain-source and gate-source voltages, we divided the channel under the gate in regions (linear, non-linear and saturated) according to the electric field.

In order to simplify the mathematical study and consequently the numerical simulation, we used some assumptions and approximations.

To determine the *I-V* extrinsic characteristics in different operations regimes, we used the iterative method.

To determine the transconductance and drain conductance as a function of the drain-source and gate-source voltages in different operations regimes, we based also for the numerical simulation methods.

## 3. Analytical model

### 3.1. Determination of the potential under the gate

The potential distribution in the active layer under the gate is modeled by solving the Poisson’s equation with proper boundary conditions, in two-dimensions this equation is given by:

where *ψ(x, y)* is the potential in the active-layer.

*ρ (x, y)* is the density of the majority carriers in the channel.

*ε* is the dielectric permittivity of semiconductor.

If the channel doping is homogeneous, the activity area density is written

where *Nd(y)* is the doping profile in semiconductor.

To simplify the study, one considers that this equation is a superposition of two simple equations. In this connection, one can write:

where

In such a way, according to formula (3 – 5) the process of solving the initial Poisson's equation consists of looking-for of solution to one-dimensional equation (Eq. 4) and solving the two-dimensional equation (Eq. 5).

### 3.2. Boundary conditions

The above solution of the Poisson’s equation has to verify the equations and boundary conditions expressed as:

where *Vg* is the intrinsic gate-source voltage, *Vd* is the intrinsic drain-source voltage and *Vb* is the built-in voltage of the Schottky barrier.

If the drain voltage is equal to zero, the symmetry between the two gate-sides leads to the following condition:

At the first point of the pinch-off, the electron velocity attains its maximum and the electric field with drain side’s corresponds to the saturation field *ES*.

The electric field must vanish in the depletion-layer edges at both gate-sides; this field may cause a large current flow. Therefore, it may be written:

### 3.3. 1D approximation

By integrating the equation (4) from *0* to *h (x)*, we determine the term *U (y)*, and one obtains:

The one-dimensional depletion layer width *hX* at any *x* coordinate is given by the one-sided abrupt junction depletion approximation (Sze and Ng, 2007).

where *V(x)* is the potential of the neutral channel with *V(0) = 0* at the source-end and *V(L) = Vd* at the drain-end. So that the one-dimensional depletion widths at the source and drain ends given respectively by:

### 3.4. 2D analytical model

To determine the second term, we based for the works Chin and Wu (1992, 1993), Jit et al. (2003, 2011) and Morarka and Mishra. (2005), these studies are used the Green’s functions and superposition techniques. In the homogeneous medium, the solution suggested is written in the following form:

where

*AS1* and* AD1* are the first term of Fourier coefficient for the excess sidewall potential at the source and drain sides of the gate respectively.

*a1*, *b1* and *c1* are constants related to the device structure.

From (13) and (17), one obtains the expression of total tension *ψ (x, y)*:

### 3.5. Depletion-layer width

To calculate the two dimensional width of the depletion layer formed by the Schottky barrier* WX* at any *x* coordinate, we have considered firstly the one-dimensional approximation *hX* then we have added the corrective which results with the two-dimensional analysis. So the Eqs. (14 ~ 16) becomes respectively as follows:

where the correctives are determinate by:

and the pinch-off voltage:

### 3.6. The electron mobility law

For gallium arsenide GaAs, the analytical expression of the electron mobility dependence of the electric field which used in this study is a simplified mathematical relation (Chang and Day, 1989; Shin and Klemer 1992) given as follows:

For the feeble electric fields where *E E0*, the electrons are in thermodynamic balance with their mobility, the later is constant and independent of the electric field, in this connection:

As the electric field becomes more growth where *E E0* the interactions of the carriers with the vibrations of the network involve a reduction in the mobility of the electrons. The law of this mobility in this case is given by:

where

### 3.7. I-V caractéristics

In general, it is possible that the channel current is expressed as a function of the intrinsic grille-source and drain-source voltages in terms of physical dimensions. The basic equation used to derive the *I-V* relationship (Sze and Ng, 2007) is given by:

By simple integration, Id becomes as:

where

uD and uS are the normalized dimensionless units.

The mobility law makes it possible to obtain the different expressions of the drain-current in the different operation regimes (linear, non-linear and saturated). Fig. 1 shows the structure of a MESFET with the channel under the gate. It can be divided in general into three regions (*LA*, *LB* and *LC*) depending upon the magnitude of the electric field (Shin and Klemer, 1992; Khemissi et al. 2004, 2006). In the region *LA* the electric field is below *E0*, and the electron mobility is given by equation (29), region *LB* correspond the electric field is between *E0* and *ES* and the electron mobility is given by equation (30), the last *LC* is the high field region in which the electric field exceeds *ES* and the mobility is given by equation (30).

### 3.8. Linear regime

This regime exists when the applied drain-source voltage is sufficiently low such that the electrical field under the gate is both smaller than *E0*, the mobility is equal to *µ0* and the channel is described by *LA*. The expression of the drain current in this regime is given by:

where

### 3.9. Pinch-off regime

As the drain-source voltage increases, the electric field in the channel is not entirely below *E0*. For this case, the channel under the gate consists of two regions: One of the lengths *LA* with the field is below *E0* and the mobility is equal to *µ0*. The other region of the length *LB* with *E* is between *E0* and *ES* and the mobility is given by equation (30). The expression of the current in this regime can be obtained by:

where

and *uA* is the normalized dimensionless unit which corresponds to the drain bias equal to (*E0.L*).

### 3.10. Saturation regime

As the electric field at the drain side becomes larger than *ES*, the channel is divided into three regions: The first of the length *LA*, the second of the length *LB* and the last of the length *LC* in which the depletion-layer reaches the interface between the activate area and the semi-insulator substrate. The expression of the current in this regime can be obtained by

where

### 3.11. Effect of parasitic resistances

The characteristics which we have calculated are those of the intrinsic values (*Vg, Vd* and *Id*). To obtain the extrinsic characteristics (*Vgs, Vds,* and* Ids,*) of the device it is necessary to take into account the effect of parasitic resistances (*Rs, Rd* and *Rp*) and substitute the intrinsic terms by the extrinsic terms in all the previous expressions. In this case *Vgs, Vds* and* Ids* can be respectively expressed as

where *Rs* is the resistance of the region from the source contact to the source side of the gate, *Rd* is the resistance of the drain region outside the gate and *Rp* is the parallel resistance associated with the buffer layer.

It is obviously necessary to implement an iterative technique to obtain the extrinsic drain current *Ids* for given values of the gate-source and drain-source voltages *Vgs* and *Vds* respectively.

### 3.12. Transconductance and drain conductance

The expression of the intrinsic drain current “*Id*” makes it possible to determine the mathematical expressions of the transconductance and the drain conductance. When the transistor is polarized at a point of operation given by the biasing, the expression of the current “*Id*” can be written as follows:

The expression of the transconductance is defined by the equation:

And the expression of the drain conductance is given by the equation:

After simple derivations of the current drain expressions in the different operation regimes, one obtains the expressions of the transconductance and the drain conductance.

## 4. Numerical methods

### 4.1. Calculation of the drain current

To calculate the extrinsic characteristics *Ids (Vds, Vgs)*, one needs to put in consideration the effect of parasitic resistances, this effect which is not negligible, is very significant for the exactitude of the analytical model, but the problem of this type of models (model analytical) is that, the effect of parasitic resistances in the hand is requires to calculate the expressions of the drain current and on the other hand the mathematical relations which express this effect are determined also by the drain current. To solve this problem, are thus needed used a sophistical numerical methods. In this study, we used the iterative method represented by the following relations:

At the beginning, the initial extrinsic drain current *Ids* is considered equal to intrinsic current *Id*.

where: *Δ Ids (1)* is on a side the difference between *Ids (1)* and *Ids (0)* and on the other side it results on the effect of parasitic resistances for *Ids = Ids (0)*.

### 4.2. Calculation of transconductance and the drain conductance

The expressions of the transconductance and the conductance of drain are simple derivations of the drain current as a function as the drain and gate intrinsic voltages (Eqs. 50, 51), to obtain the values of these significant parameters, we based on numerical calculation as follows:

For the transconductance:

After the fixing of the drain voltage to the given value, the transconductance is obtained from the following relation:

where:

Same manner as the transconductance, the drain conductance is obtained after fixing of the gate voltage and after the following relation:

where:

## 5. Simulation results

In order to illustrate the exposed model, we elaborated simulation software based on different formulas and mathematical equations previously obtained and by using the numerical methods. The study carried out on a submicron gate length GaAs MESFET transistors which parameters shown in the table 1. The results obtained are exposed and interpreted in this section.

L (µm) | a (µm) | Z (µm) | Nd (At / cm^{3}) | µ_{0} (cm^{2}/ Vs) | E_{0} / Em |

0,3 | 0,145 | 100 | 1,2. 10^{17} | 3400 | 0,25 |

Rs (Ω) | Rd (Ω) | Rp (Ω) | a_{1} | b_{1} | c_{1} |

6 | 6 | 600 | - 0,06 | 0,12 | 0,10 |

In the fig. 3, we have presented the network of the static characteristics in the case of the preceding device. These characteristics illustrate the relation between the extrinsic drain current *Ids* and the bias voltages *Vds* and *Vgs*. We notice the presence of three regions which correspond to the three operation regimes (linear, non-linear and saturated).

To demonstrate the validity of the developed model and to compare its performance with the experimental data reported in the literature (Chin and We, 1993) a submicron GaAs MESFET having the parameters and device dimensions selected in Table 2. Fig. 4 represented a comparison between the proposed model and the experimental I-V characteristics for this device. It is clearly seen that good agreement between the model and the experimental data are obtained, this is quite interesting to argue the validity of the mathematical analysis and the proposed numerical methods for practical short gate-length GaAs MESFET devices.

L (µm) | a (µm) | Z (µm) | Nd (At / cm^{3}) | µ_{0} (cm^{2}/ Vs) | E_{0} / Em |

0,5 | 0,143 | 100 | 1,31. 10^{17} | 3600 | 0,25 |

Rs (Ω) | Rd (Ω) | Rp (Ω) | a_{1} | b_{1} | c_{1} |

6 | 6 | 1000 | - 0,06 | 0,12 | 0,10 |

Fig. 5 and Fig. 6 represent the transconductance as a function of the intrinsic drain voltage *Vd* for a series of intrinsic gate voltage *Vg*. In these figures, we noticed that the transconductance increases on the one hand as the absolute value of the voltage gate decreases, and on the other hand with the increase in the drain voltage until the saturation regime where the transconductance is saturated. This is explained because, more the gate voltage increases in absolute value, more the width of space charge area increases. The extension of this area ends when this one occupies all the width of the channel. No passage of the current is then theoretically possible.

Fig. 7 represents the drain conductance as a function of the drain voltage for a series of gate voltage. We notice that the drain conductance is decreases on the one hand as the drain voltage increases and on the other hand when the absolute value of the gate voltage increases. It takes its maximum value in linear regime, and is cancelled in regime of saturation. This explains why, in linear mode, the electrons available for conduction and present in the channel do not reach their speed limit. Also the drain current *Ids* varies in an important and quasi linear way with the drain voltage. On the contrary, for the strong values of *Vd* in the saturated regime, the electrons reached their speed limits and the current *Ids* progresses slightly with *Vd*.

## 6. Conclusion

During this work, a comprehensive new model is developed to simulate the static characteristics of short gate-length GaAs MESFET. The validity of the model is established by simulating *Ids*, *gm* and *Gd* characteristics. The performance of the model is compared with experimental results existing in the literature by calculating the I-V characteristics of a device with the gate length is equal to 0,5 µm. It has been demonstrated that the proposed model is a comprehensive one capable of simulating DC characteristics of short gate-length GaAs MESFETs. The transconductance and drain conductance curves obtained by the model have the same behavior with those of the theory, so that it has been shown that proposed model could be a useful tool for device simulators involving short channel MESFETs.