Open access peer-reviewed chapter

Technology CAD of Nanowire FinFETs

By T K Maiti and C K Maiti

Published: February 1st 2010

DOI: 10.5772/39522

Downloaded: 4947

1. Introduction

The potential applications of semiconductor nanowire (NW) field-effect transistors as potential building blocks for highly downscaled electronic devices with superior performance are attracting considerable attention. In the area of Technology CAD (TCAD) of nanowire FinFETs, it is fair to say that there have been very little or no reports are available in the literature on TCAD modeling of nanowire FinFETs. This chapter presents a detailed framework for virtual wafer fabrication (VWF) including both the device design and the manufacturing technology.

Technology computer aided design is now an indispensable tool for the optimization of new generations of electronic devices in industrial environments. In recent years, non-classical MOS devices such as nanowire FinFETs have received considerable attention owing to their capability of suppression of short channel effects, reduced drain-induced barrier lowering and excellent scalability. Different methods have been reported for the fabrication of silicon nanowires. The novel device designs need three-dimensional (3-D) process and device simulations. Nanowire FinFETs being nonplanar are inherently three-dimensional (3-D) in nature. Sentaurus process tool (3-D process simulation) has been used to study suitability of technology CAD for FinFET process development and the simulation results will be presented in this Chapter. TCAD predictability FinFETs having 25 nm gate lengths with nitride cap layer and fabricated using a conventional CMOS like process flow for novel strain-engineered (process-induced strain) nanowire have been described in detail. Effects of process-induced strain on the performance enhancement of nanowire FinFETs have been discussed.

Sentaurus Device simulator has been used to study electrical characteristics by solving self-consistently five partial differential equations (Poisson equation, electron and hole continuity equations, electron energy balance equation, and the quantum potential equation).The detail of device simulation for FinFETs will be presented. A compact model serves as a link between process technology and circuit design. As FinFETs are predicted to be used in RFIC applications, flicker noise in FinFET becomes very important and modeling of noise in FinFETs will also be described. Hot-carrier induced degradation behavior of nanowire FinFETs and extraction of SPICE parameters essential for circuit analysis and design will be described.

2. Importance of TCAD

For the past four decades, the performance of very large scale integrated (VLSI) circuits and cost-per-function has been steadily increased by geometric downscaling of MOSFETs. Advanced transistor structures, such as multiple-gate (MuG) or ultra-thin-body (UTB) silicon-on-insulator (SOI) MOSFETs, are very promising for extending MOSFET scaling because short channel effect (SCE) can be suppressed without high channel doping concentrations, resulting in enhanced carrier mobilities. In recent years, non-classical MOS devices such as FinFETs have received considerable attention owing to their capability of suppression of short channel effects, reduced drain-induced barrier lowering and excellent scalability.

The Ω-FinFETs have unique features such as high heat dissipation to the Si substrate, no floating body effect, and low defect density, while having the key advantages of the silicon-on-insulator (SOI)-based FinFETs characteristics. The Ω-FinFET has a top gate like the conventional UTB-SOI, sidewall gates like FinFETs, and special gate extensions under the silicon body. The Ω-FinFET is basically a field effect transistor with a gate that almost covers the body. However, the manufacturability of this type of device structures is still an issue. Many different methods have been proposed to fabricate these devices but most of them suffer from technical challenges mainly due to the process complexity.

Strained-Si technology is beneficial for enhancing carrier mobilities to boost Ion. Both electron and hole mobilities can be improved by applying stress to induce appropriate strain in the channel, e.g., tensile strain for n-channel MOSFETs and compressive strain for p-channel MOSFETs (Maiti et al., 2007). Effect of strain on mobility can be understood by considering the stress induced changes in the complicated electronic band structures of Si. The novel device designs increase the need for three-dimensional (3-D) process and device simulations. FinFET is a nonplanar device and are inherently three-dimensional (3-D) in nature. Therefore, for FinFETs, any meaningful process or device simulation must be performed in three dimensions. Synopsys tools SProcess/SDevice address this need (aSynopsys & bSynopsys, 2006).

2.1. Process simulation

The FinFET process flow used in process simulation is similar to the flow presented by F.-L. Yang et al. (Yang et al., 2002). Process flow used is summarized as follows:

1. Fin patterning and threshold voltage implant

2. Gate oxidation, In-situ N+poly gate deposition and patterning

3. nMOS S/D extension implantation

4. Spacer formation

5. S/D implantation

i. Contact formation

As the Sentaurus Process (aSynopsys, 2006) is designed as a simulator that works independently of the dimensionality of the structures to be simulated, the process flow was executed by a sequence of three tool instances as discussed above. During the process flow execution, intermediate structures are saved for subsequent use by Sentaurus Process. Sentaurus Process loads the intermediate geometries generated by Sentaurus Structure Editor and performs the implantation and diffusion steps associated with each intermediate structure. The starting material is a (100) FDSOI wafer with a top silicon layer thickness of 25 nm. The top silicon layer has initially a uniform boron concentration of ~5.5x1018 cm–3. The Fin height used in simulation was up to 50 nm, and with 12 nm cap oxide. Channel doping is performed to adjust nMOS Vt using ion implantation. To relieve the etch damage; a sacrificial oxide is removed before gate oxidation. 25 Å thermal oxide is grown and in-situ heavily doped N+ poly-silicon is deposited. After gate plasma etch, the source/drain extension implantation is simulated followed by annealing simulation.

The activation/annealing are simulated by Sentaurus Process using the pair diffusion model. For the 3-D Ω-FinFET simulation, analytic implantation model is used. For the point defects, the appropriate model is activated. For the activation, the solid solubility model is used. To capture the influence of the nonequilibrium point-defect concentrations on the diffusivity of the dopants (phosphorus, arsenic, and boron), the advanced pair-diffusion model is used. It has been observed that during the annealing process, boron is redistributed in a complex fashion. The arsenic extension implant introduces a large amount of interstitials, which during the annealing diffuse quickly to the surface, where they recombine. As boron diffuses only as boron interstitial pairs, boron is transferred to the surface in this process. Due to small volume in the channel Fin, a limited amount of boron is available and, therefore, the boron pileup at the surface in the extension area is accompanied by a corresponding depletion of boron in the center of the channel fin in the extension area. Composite spacer of silicon oxide and nitride is deposited and etched anisotropically with final thickness of ~ 32 nm. Heavily doped N+ and P+ junction are made with Phosphorous

Figure 1.

Device structure after process simulation.

Figure 2.

Arsenic distribution inside the Strained-Si Fin.

and Boron implantation. Thermal anneals above 1000 C are used for dopants activation. The process was completed by standard metal contact formation. Fig. 1-3 show some process simulated results for 25 nm gate length FinFETs. Silicon-Fin is fabricated on buried-oxide (BOX) and consecutively capped with nitride (Si3N4). A tensile process induced strain has been evolved in the Fin, during thermal process.

Figure 3.

Stress (εxx) distribution in channel for Ω-FinFET.

2.2. Device simulation

In advanced deep submicron MOS device structures, transport models must be used. Also the channel–gate oxide interface must be resolved to a very high level of accuracy. The finite-element mesh must also resolve the very steep gradients of the inversion layer. Accordingly, Noffset3D is used to remesh the Ω- FinFET for the device simulations. Also for the Ω-FinFET structure considered here, the body may not be fully depleted. Therefore, the continuity equations for both electrons and holes must be solved simultaneously. The very short gate length of 25 nm mandates the use of the hydrodynamic transport model. Further, the thin oxide thickness (2.4 nm) and relatively high body doping level (~5.5x1018 cm–3) require the consideration of quantization effects. Unlike other approaches to model quantization effects such as 1-D Poisson–Schrödinger and the modified local-density approximation (MLDA), the density gradient model is also applicable to nonplanar 3-D structures. Thus, in simulation, advanced quantization model (density gradient model) is used. Within the density gradient model, an additional partial differential equation is solved to determine the effective quantum potential. For the 3-D FinFET, Sentaurus Device solves self-consistently five partial differential equations (Poisson equation, electron and hole continuity equations, electron energy balance equation, and the quantum potential equation). In device simulation, the Ids–Vgs characteristics for a low-drain bias and high-drain bias are simulated and relevant electrical parameters, such as threshold voltages and drain current are extracted.

2.3. Results and discussion

Fig. 3 shows the Ids-Vgs characteristics for the device with the strained cap layer and relaxed cap layer. The ON-state Ids of~ 0.42 and ~0.38 mA/μm are obtained for strained and unstrained-Si Ω-FinFET, with OFF-state Ids < nA at an operating voltage of 1.0 V (|Vgs − Vth| = 0.96 V and |Vds| = 1.0 V). A slight Vt shift of approximately 15 mV is due to the strain-induced effect on bandgap. One can expect much higher drive currents by further reducing the channel length and gate oxide thickness. Despite the use of a 2.4 nm thick gate oxide, strained-Si Ω-FinFET exhibits near ideal S.S. (~64 mV/dec) and low DIBL (~20 mV/V).

Figure 4.

Id-Vgs characteristic of FinFETs at Vds = 0.05 V and 1.0 V with stressed nitride cap layer and relaxed cap layer.

Figure 5.

Comparison of simulated transconductance for both FinFET.

Fig. 5 shows the gm(dIds/dVgs) variation as a function of gate bias for both devices. Ω-FinFETs shows the peaking in gm value due to mobility dependence on gate-field which is well known for the bulk FET devices. The main reason is the electron confinement due to strain near surface where surface roughness scattering of the carriers at high gate fields (with reduced carrier mobility) leads to the peaking in gm. For strained-Si Ω-FinFET, a 30% higher gm than reference transistor is observed.

Fig. 6 compares the Ids-Vds characteristics for the devices with a highly tensile cap layer and a relaxed cap layer. The Ω-FinFETs with a highly tensile stress cap layer shows improvement of the saturation current Idsat of approximately 13% compared to the device with the relaxed cap layer. The stress that originates from oxidation and other processing steps has a minor effect on the carriers transport.

Figure 6.

Ids-Vds characteristics of FinFETs at Vg = 1.25 V with strained cap layer and relaxed cap layer

Summary of transistor parameters in comparison with conventional (Si only) FinFET is shown in Table 1. It is observed that simulated transistor performances (subthreshold swing and gate delay) of the Ω-FinFETs are significance.

TypeBulk-Si FinFETStrained-Si FinFET
Threshold voltage (mV)434381
Ion (μA/μm)700853
Ioff (nA/μm)1.132.02
Subthreshold swing
(mV/decade)
62.7764.55
DIBL (mV/V)2620

Table 1.

Comparison of transistor parameters with conventional FinFET.

3. Hot carrier degradation in nanowire (NW) FinFETs

Hot-carrier induced phenomena are of great interest due to their important role in device reliability (Maiti et al., 2007b). High energy carriers (also known as hot carriers) are generated in MOSFETs by high electric field near the drain region. Hot carriers transfer energy to the lattice through phonon emission and break bonds at the Si/SiO2 interface. The trapping or bond breaking creates oxide charge and interface traps that affect the channel carrier mobility and the effective channel potential. Interface traps and oxide charge also affect the transistor parameters, such as, the threshold voltage and drive currents. Several workers have reported the results of their investigation on hot-carrier effects on the performance of p-MOS transistors (Pan., 1994; Heramans et al., 1998). It has been shown that the degradation of p-MOS transistors is caused by the interface state generation and hole trapping in the gate oxide from the hot-carrier injection. Reliability assurance of analog circuits requires a largely different approach than for the digital case. It is generally accepted that injected and trapped electrons dominate the degradation behavior. In this work, we describe a physics based coulomb mobility model developed to describe Coulomb scattering at the Si-SiO2 interface and implement in device simulator. Hot-carrier induced current and subsequent degradation in nanowire (NW) Ω-FinFETs are investigated using simulation and validation with reported experimental data. The influence of the hot carriers on the threshold voltage and drive currents is examined in detail for nanowire Ω-FinFETs.

3.1 Quasi-2D coulomb mobility model

The silicon (Si)–silicon dioxide (SiO2) interface in nanowire (NW) Ω-FinFETs shows a very large number of trap states. These traps become filled during inversion causing a change of conduction charge in the inversion layer and increase the Coulomb scattering of mobile charges. Owing to the large number of occupied interface traps, Coulomb interaction is likely to be an important scattering mechanism in nanowire (NW) Ω-FinFET device operation, resulting in very low surface mobilities and may be described by a quasi-2D scattering model. The coulomb potential due to the occupied traps and fixed charges decreases with distance away from the interface. So, mobile charges in the inversion layer that are close to the interface are scattered more than those further away from the interface; therefore, the Coulomb scattering mobility model is required to be depth dependent. We assume that the electron gas can move in the x-y plane and is confined in the z direction. Electrons are considered confined or quantized if their deBroglie wavelength is larger than or comparable to the width of the confining potential. The deBroglie wavelength of electrons, given byλ=/2m*kBT, is approximately 150Å at room temperature, where as the thickness of the inversion layer is typically around 50Å to 100Å. Thus, one may justify treating the inversion layer as a two dimensional electron gas. The scattering from charged centers in the electric quantum limit has been formulated by Stern and Howard (1967). We consider only the p-channel inversion layer on Si (100) surface where the Fermi line is isotropic and calculate the potential of a charged center located at (r i , z i ). Using the image method, we get

Vi(r,z)=e24πε0k˜(rri)2+(zzi)2E1

wherer2=x2+y2, z = 0 corresponds the Si/SiO2 interface. z > 0 is in silicon whereas z < 0 is in the oxide. Wherek˜=(kSi+kox)/2for z < 0, and εo is the permittivity of free space. We assume parabolic sub bands with the same effective heavy-hole mass, m * . Since inversion layer electrons are restricted to move in the x-y plane, they would only scatter off potential perturbations that they see in the x-y plane. Therefore, we are only interested in determining the potential variations along that plane. To do so, one needs to calculate the two dimensional Fourier transforms of the potential appearing in Eqn. (1). The hole wave functions are then given by

ψi,k(r,z)=1Aξ(z)eik.rE2

where i represent the subband index andk=(kx,ky)is the two-dimensional wavevector parallel to the interface.ξ(z)is the quantized wave function in the direction perpendicular to the interface, E i its corresponding energy andr=(x,y). We denote the area of the interface by A. The effective unscreened quantum potential for holes in the inversion layer in the electric quantum limit in terms of the 2D Fourier transform is given by

v(q,zi)=e22k˜ε0qξi(z)ξj(z)eq.|zzi|dzE3

We now consider the effect of screening due to inversion layer electrons on Coulombic scattering. Screening is actually a many-body phenomenon since it involves the collective motion of the electron gas. Using the Coulomb screening we get,

v(q,zi)=e22k˜ε0(q+qs)ξi(z)ξj(z)eq.|zzi|dzE4

Whereqs=e22k˜ε0ξi(z)ξj(z)eq.|zzi|dzone obtains the scattering rate using Fermi’s golden rules,

S(q,zi)=2π2(e22k˜ε0(q+qs)ξi(z)ξj(z)eq.|zzi|dz)2δ(EkEk/)E5

where is Planck’s constant.EkandEk/denote the initial and final energies of the mobile charge being scattered. Scattering of inversion layer mobile charges takes place due to Coulombic interactions with occupied traps at the interface and also with fixed charges distributed in the oxide. Defining the 2D charge density N2Dδ(zi) at depth zi inside the oxide as the combination of the fixed charge Nf and trapped charge Nit as

N2D(zi)={Nit+Nf(0),zi=0Nf(zi),zi0E6

Using the above approximation, one obtains the total transition rate. Since, Coulombic scattering is an elastic scattering mechanism, the scattering rate or equivalently the inverse of the momentum relaxation time is then calculated as

1τm=1(2π)2.2π2(e22k˜ε0)2(1(q+qs)ξi(z)ξj(z)eq.|zzi|dz)2δ(EkEk/)(1cosθ)δkE7

Using the above relaxation time, one obtains the mobility of the i-th subband as,

μi=em*iτmεf0(ε)εdεεf0(ε)εdεE8

The average mobility,μ¯, is then given by

μ¯=ipiμi2ipiμiE9

where p i is the hole concentration in the i th subband. Taking into the different scattering mechanism and using the Matthiessen’s rule one obtains the total mobility µ.

3.2. Mobility model implementation

The Coulomb scattering mobility model has been implemented in Synopsys Sentaurus Device simulator. To activate the mobility model appropriate mobility values were defined in the fields of the parameter file. Simulation data for the drain current (Ids) versus gate voltage (Vgs) curves match the experimentally measured results very well (Singh et al., 2005). Fig. 7 shows the Ids-Vgs characteristics of the simulated p-type nanowire Ω-FinFET with a 10 nm-thick, and 100 nm-long Si-fin as the channel body. At room temperature, the devices show high ON-current (Ids at Vds = Vgs = 1.1 V) of ~0.68mA/µm, Vth ~ 0.2 V, and subthreshold swing (SS) of ~68 mV/dec. Low drain-induced barrier lowering (DIBL) of ~10 mV/V is obtained, with ION/IOFF> 107 at room temperature. These results are similar to those reported for nanowire Ω-FinFETs by Singh et al. (Singh et al., 2005).

Figure 7.

Gate bias dependence of drain current for nanowire Ω-FinFETs (both simulated and experimental) (after b Maiti et al., 2008).

3.3. Results and discussion

Fig. 7 shows a lower drain current for Ω-FinFETs which underwent hot carrier stressing (compared to unstressed devices). Degradation in drain current indicates that hot-carrier induced positive charges are localized near the drain end.

Figure 8.

Degradation of drain current under DC stress (after Maiti et el., 2008b).

Fig. 9 shows the threshold voltage Vth shift with increasing stress time. The threshold voltage Vth shift indicates that net positive charges exist at the gate dielectric interface as a result of hole trapping. As the lateral electric field near the drain increases in short channel devices, electron-hole pairs are generated by impact ionization. These generated holes have energies far greater than the thermal-equilibrium value and are the hot holes. In surface-channel of Ω-FinFETs, hot holes are injected into the gate oxide via hot-carrier injection (HCI), resulting in the formation of dangling silicon bonds due to the breaking of silicon-hydrogen bonds and lead to the interface traps generation (Hu et al., 1985). The charge trapping in interface states causes a shift in threshold voltage and the decrease of transconductance, which degrades the device properties over a period of time.

Figure 9.

Threshold voltage Vth shift with increasing stress time indicating an accumulation of negative charges due to electron trapping at the Si/SiO2 interface (after b Maiti et el., 2008).

The hot-carrier lifetime measurements were performed and the typical Idsat degradation as a function of stress time is plotted in Fig.10. The Idsat degradation is consistent with Vth shift.

Figure 10.

Idsat degradation as a function of stress time. Hot carrier lifetime in nanowire Ω-FinFETs after stressing for a given Isub/Id (after b Maiti et el., 2008).

4. Spice modeling of silicon nanowire FETs

In this section we will discuss the spice model of silicon nanowire FETs. This section presents the fully depleted BSIMSOI modeling of low power n- and p-MOS nanowire surrounding gate field-effect transistors (SGFETs), extraction of distributed device parasitics, and measuring the capabilities of these FETs for high-speed analog and RF applications.

4.1. Intrinsic SPICE modeling of nanowire FETs

SPICE models of n- and p-MOS SGFETs are created by fully depleted BSIMSOI parameters and are listed in Table 2. These parameters are optimized to ensure input and output I–V characteristics of 10 nm channel length and 2 nm radius SGFETs (Hamedi-Hagh & Bindal, 2008).

The distributed parasitic RC components across the intrinsic SGFET transistor are modeled for n- and p-MOS transistors, as shown in Fig. 11 and (b), respectively.

Cgsx is the parasitic capacitance between metal gate and the concentric source and Cgsy is the parasitic capacitance between metal gate and the source contact. The resistor rg accounts for the effective gate resistance at high frequencies caused by the distributed gate-oxide channel. The resistance Rg accounts for two parallel gate contacts. Cdsx is the parasitic capacitance between intrinsic drain and source contacts and Cdsy is the parasitic capacitance between drain and source interconnects. Resistors Rsx and Rsy represent source contacts and resistors Rnw and Rpw represent overall concentric n-well and p-well resistances from intrinsic source to extrinsic source contacts of n- and p-MOS SGFETs, respectively. Cgdx is the parasitic capacitance between gate contact and the intrinsic drain and Cgdy is the parasitic capacitance between gate and drain interconnects. The resistor Rd represents the drain contact of the transistor. The effective resistor rg is given by

rg=112(Rs2πRL)E10
ParametersValues
Channel Length (L)10 nm
Channel Radius (R)2 nm
Gate Oxide Thickness (tox)1.5 nm
Channel Doping Concentration (nch)1.5e+19 cm-3
Substrate Doping Concentration (nsub)1.0e+11 cm-3
Threshold Voltage (Vth0)0.26 V (nMOS)
-0.28 V (pMOS)
Mobility (U0)1000 cm2/V.s (nMOS)
300 cm2/V.s (pMOS)
Parasitic Resistance Per Unit Area (Rdsw)130Ω.µm (nMOS)
360Ω.µm (pMOS)
Saturation Velocity (Vsat)≈2e+06 cm/s
Subthreshold Region Offset Voltage (Voff)0.06 V
Channel Lenth Modulation (Pclm)25
Primary Output Resistance DIBL Effect (Pdiblc1)1.02e-06
Secondary Output Resistance DIBL Effect (Pdiblc2)1
Primary Short Channel Effect on Vth (Dvt0)3.8
Secondary Short Channel Effect on Vth (Dvt1)2.75
Short Channel Body Bias Effect on Vth (Dvt2)0 V-1
Primary Narrow Width Effect on Vth (Dvt0w)0
Secondary Narrow Width Effect on Vth (Dvt1w)7.25e+07
Narrow Width Body Bias Effect on Vth (Dvt2w)0.34 V-1
Subthreshold Region DIBL Coefficient (Eta0)0.008
Subthreshold Body Bias DIBL Effect (Etab)0.174 V-1
DIBL Coefficient Exponent (Dsub)1
Source/Drain to Channel Coupling Capacitance (Cdsc)1.373e-10 F/cm2

Table 2.

List of BSIMSOI model parameters of SGFETs (after Hamedi-Hagh & Bindal, 2008).

Figure 11.

Distributed parasitic components across. (a) Intrinsic n-MOS, Mn. (b) Intrinsic p-MOS, Mp, SGFETs (after Hamedi-Hagh & Bindal, 2008).

which is equal to the effective gate resistance of the planar transistors with signals applied to both ends of the gate. The distributed SGFET parasitic components are listed in Table 3(a) and (b) for resistors and capacitors, respectively.

Table 3.

List of SGFET parasitic (a) resistors (b) capacitors (after Hamedi-Hagh & Bindal, 2008).

4.2 Extrinsic SPICE modeling of nanowire FETs

S parameters are obtained by sweeping the frequency from 1 MHz to 103 THz and using ports with Z0 = 1 kΩ internal resistances to ensure stability. The transistors are biased with Vds = 1 V and Vgs = 0.5 V to yield the maximum transconductance and to ensure a high power gain. The S22 (output return loss) is a measure of the transistor output resistance and S21 (forward gain) is a measure of the transistor voltage gain. Due to similar dimensions, n- and p-MOS SGFETs have very similar parasitic components, while the gm and rout of n- and p-MOS transistors differ from each other. Therefore, it is expected that S22 and S21 of the n- and p-MOS transistors deviate from each other, while S11 (input return loss) and S12 (reverse gain) of transistors match more closely. The two important figure of merits for RF transistors are the maximum frequency of oscillation (fmax) and the unity current- gain cut-off frequency (fT). The fmax is obtained when the magnitude of the maximum available power gain (Gmax) of the transistor becomes unity and fT is obtained when the magnitude of the current gain (H21) of the transistor becomes unity. The Gmax and H21 of the transistor, under simultaneous conjugate impedance-matching conditions at input and output ports, are expressed in terms of S-parameters as (Hamedi-Hagh & Bindal, 2008)

Gmax=S212(1S112)(1S222)E11
and
H21=S21(1S11)(1+S22)+S12S21E12

The fmax and fT of n- and p-MOS SGFETs are 120 THz, 36 THz and 100 THz, 25 THz, respectively. All SPICE results indicated the potential use of nanowire FETs in high-speed and low-power next-generation VLSI technologies.

5. Process-compact SPICE modeling of nanowire FETs

In this section, we present a simulation methodology for nanowire FinFETs which allow the flow of pertinent information between process and design engineers without the need for disclosing details of the process. Compact SPICE model parameters are obtained using parameter extraction strategy as a polynomial function of process parameter variations. As a case study, SPICE models are used to identify the impacts of process variability in inverter circuit with nanowire FinFETs.

In advanced technology nodes (< 45 nm), process variations and defects are largely dominating the ultimate yield. The sources of the process variations and defects must be identified and controlled in order to minimize the yield loss. Technology CAD (TCAD) is a powerful tool to identify such root causes for yield loss. TCAD tools are used to study device sensitivities on process variations. Currently, TCAD is heavily used in device research and process integration phases of technology development. However, a major trend in the industry is to apply TCAD tools far beyond the integration phase into manufacturing and yield optimization. In this section, linking of process parameter variations (via DoE) with the electrical parameters of a device through Process Compact Model (PCM) is also demonstrated.

Towards extended TCAD, in process modeling, generally a systematic design of experiments (DoE) run is performed. DoE experiments can be systematically set up to study the control over process parameters and arbitrary choice of device performance characteristics. The models developed from DoE are known as process compact models (PCMs) which are analogous to compact models for semiconductor devices and circuits. PCM may be used to capture the nonlinear behavior and multi-parameter interactions of manufacturing processes (Maiti et al., 2008). SPICE process compact models (SPCMs) can be considered as an extension of PCMs applied to SPICE parameters. By combining calibrated TCAD simulations with global SPICE extraction strategy, it is possible to create self consistent process-dependent compact SPICE models, with process parameter variations as explicit variables. This methodology brings manufacturing to design, so that measurable process variations can be fed into design [borges06]. To design robust circuits using strain-engineered MOSFETs, the effect of process variability on the circuit model parameters examined in detail.

5.1. Process compact models: An overview

Process compact models (PCMs) methodology consists of TCAD simulations, using the process and device models that are calibrated to silicon, and process-dependant compact SPICE model extraction (see Fig. 12). The parameter extraction is performed using the parameter extraction tool Paramos (Synopsys, 2008c), which interfaces with TCAD or experimental data and directly generates process-aware SPICE models. The process-aware SPICE models allow designers to account for process variability and to develop more robust designs.

Process compact models:

Capture the process–device relationships between the process parameters and device performance of a semiconductor manufacturing process.

  1. Are robust, fast to evaluate, and can be embedded into other environments such as PCM Studio, spreadsheet applications, and yield management systems.

  2. Are analogous to device compact models, which capture electrical behavior and can be derived from measurements or simulations.

Figure 12.

Compact SPICE model extraction and validation methodology.

SPICE process compact models (SPCMs) can be considered as an extension of PCMs applied to SPICE parameters. Using a global extraction strategy, available from the Synopsys tool Paramos, pertinent compact SPICE model parameters are simultaneously obtained as a polynomial function of process parameter variations. The extraction procedure is performed using Paramos, which will deliver an XML file containing the extracted SPICE model parameters. This methodology brings manufacturing to design, so that measurable process variations can be fed into design. Additionally, design sensitivity to process can be fed back to manufacturing so that product dependent process controls can be performed. Here the chosen SPICE model parameters (Y i ) are extracted as an explicit polynomial function of normalized process parameter variations (P˜j) as shown in Eqn. 13. Process parameter variations are normalized with respect to the corresponding standard deviation of the parameter as shown in Eqn. 14. Such a normalization process enables the encryption of proprietary information like the absolute values of the process parameters.

yi=yi0+jn=1Naijnp˜jnE13

Where, Y i - Nominal value of the i-th model parameter, j is the j-th process parameter, N is the highest order of polynomial,aijnis the process coefficient of j-th process parameter for the i-th SPICE model parameter and for order n of the polynomial,p˜jis the normalized process parameter defined as,

p˜j=pjpj0σjE14

Where, p j is the j-th value of the process parameter,pj0is the nominal value of the j-th process parameter, σ j is the standard deviation of the j-th process parameter. Here we represent the BSIM4 SPICE model parameters as quadratic function of process parameters. This model is easily scalable to higher orders of polynomial (N) for higher accuracy of extraction (Tirumala et al., 2006). Current extraction strategy of the SPICE model parameters involves extraction of nominal SPICE parameters(y0i)followed by extraction of process coefficients(aijn)and re-optimized nominal values of SPICE parameters(y0i).

5.2. Process-aware SPICE parameter extraction

To extract the model parameters, process and device simulations were first performed using typical CMOS process flow. The model parameters extracted are for the nominal process conditions and various drawn gate lengths. One of the SPICE parameters, namely voltage (Vth), as a function of process parameters has been extracted. In order to validate the compact SPICE model, for a given set of process conditions and device bias states, I-V curves obtained from TCAD simulations are compared with those obtained from Paramos using process-dependant compact SPICE model card. Fig. 13 shows the current-voltage characteristics. The dots show the TCAD simulation data, and the solid lines show the electrical characteristics generated by global SPICE model.

Figure 13.

Current–voltage characteristics.

As an example, SPICE model parameter of threshold voltage (Vth) extracted as an explicit polynomial function of normalized process parameter variations(Pin)as shown in Eqn. 14.

Vth=Vth0+ainPinE15

Where, V th0 is the nominal value of threshold voltage, i is the i th value of the process parameter,ainprocess coefficient of i th process parameter for the SPICE model parameter and for order n of the polynomial, and P is the normalized process parameter. Such a normalization process (P) enables the encryption of proprietary information like the absolute values of the process parameters. BSIMSOI SPICE model parameters as quadratic function of process parameters have been considered. This model is easily scalable to higher orders of polynomial (n) for higher accuracy of extraction. The SPICE model parameter such as threshold voltage (V th ) involves extraction of nominal SPICE parameters (V th0 ) followed by extraction of process coefficientsainand re-optimized nominal values of SPICE parameters (Vth0). Threshold voltage model for strain-engineered nMOSFETs have been obtained using first order polynomial as function of gate length (Lg) and oxide thickness (Tox) as

Vth=Vth0+(Lgα1).β1+(Toxα2).β2E16

and corresponding threshold voltage Eqn.

Vth= 0.27+(Lg-90)/45*0.088032+(tox-0.055)/0.01*0.0231E17

Here, spice parameters are represented as first order polynomial function of process parameter variations. Threshold voltage parameter generated by the global SPICE model, shows the maximum error is approximately 12% and the root-mean-square (RMS) error is approximately 5%. These results show that the global model can be used to predict the electrical behavior of the devices in the absence of process variability.

6. Noise in silicon nanowire Fin-FET

This section deals with the noise in silicon nanowire FinFETs (SNWFinFETs). The noise of a device is the result of the spontaneous fluctuations in current and voltage inside the device that are basically related to the discrete nature of electrical charge. Noise imposes limits on the performance of amplifiers and other electronic circuits. Si nanowire transistors (SNWTs) have also been widely studied as chemical and biochemical sensors (Zhang, 2007a, Zhang, 2008b& Stern, 2007). Biosensing by SNWTs is based on the pronounced conductance changes induced by the depletion of charge carriers in the silicon body when the charged biomolecules are bound to its surface. The high noise level in the depletion (subthreshold) region may lead to reduced signal-to-noise ratios in these sensors (Wei, 2009). In this section Low-frequency noise (LFN) in SNWTs has been demonstrated in the subthreshold region.

6.1. Low frequency noise measurements

The standard noise measurement set-up included an E5263A 2-channel high speed source monitor unit, a SR 570 low noise amplifier (LNA) and a 3570A dynamic signal analyzer. Here, E5263A 2-channel high speed source monitor unit provided the necessary gate-source and drain-source biases as shown in Fig. 14. The minute fluctuations in the drain-source voltage were amplified to the measurable range using low amplifier. The output of the amplifier is fed to 35670A dynamic signal analyzer that performs the fast Fourier transform on the time domain signal to yield the voltage noise power spectral density (SV) in the 1-100 kHz range after correcting for amplifier gain. In order to obtain a stable spectrum, the number of averages was set at 40 and a 90% sampling window overlap was used for optimal real time processing. A computer interface was provided to control the dynamic signal analyzer and automate the noise data collection.

Figure 14.

Low frequency noise measurement system.

6.2 Low-frequency noise

Fig. 15 shows the frequency dependence of the measured drain-current noise spectral density Sv of 100 nm p-type SNWFinFETs, biased at Vds = −50 mV at different gate bias. The Sv extracted at f = 600 Hz of each curve is shown in the inset. The dispersion of the noise spectral density is due to randomly distributed oxide traps, the lattice quality and mobility variations of the ultrascaled dimension of SNWFinFETs.

Figure 15.

Drain–current noise spectral density Sv of p-type SNWFinFETs with L = 100 nm biased at Vds = −50 mV at different gate bias (Vgs).

© 2010 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike-3.0 License, which permits use, distribution and reproduction for non-commercial purposes, provided the original is properly cited and derivative works building on this content are distributed under the same license.

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T K Maiti and C K Maiti (February 1st 2010). Technology CAD of Nanowire FinFETs, Nanowires, Paola Prete, IntechOpen, DOI: 10.5772/39522. Available from:

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