Open access peer-reviewed chapter

High‐Efficiency Front Junction n‐Type Crystalline Silicon Solar Cells

By Yuguo Tao and Ajeet Rohatgi

Submitted: February 23rd 2016Reviewed: July 25th 2016Published: February 22nd 2017

DOI: 10.5772/65023

Downloaded: 2124

Abstract

This chapter aims to provide students/workers in the field of photovoltaics with the valuable information and knowledge needed to understand the physics and operation of high‐efficiency front junction n‐type crystalline silicon solar cells. The surface recombination and passivation mechanisms, and several promising passivation schemes for front and back cell surfaces, are addressed and reviewed. The advanced cell structures and their fabrication schemes to achieve higher efficiency are described and discussed, including selective emitter on the front and locally doped back surface filed or carrier selective rear contact composed of tunnel oxide and phosphorus‐doped polycrystalline silicon thin film. These advanced cell design features have become highly active areas of investigations in the photovoltaic industry for next‐generation production cells.

Keywords

  • front junction
  • recombination
  • surface passivation
  • selective emitter
  • tunnel oxide passivated contact
  • high efficiency

1. Introduction

Solar cells depend upon the photovoltaic effect for their operation that converts the incident energy of sunlight directly into electricity using the electronic properties of semiconducting materials. In the past few decades, silicon wafers have been used to fabricate the overwhelming majority of solar cells in the very dynamic photovoltaic industry because of the abundance and non‐toxicity of silicon, the simplicity of cell fabrication process, and the vast amount of processing knowledge developed and accumulated in the microelectronics industry. Simply speaking, silicon wafer‐based solar cells generate electricity via absorbing photons and generating electron‐hole pairs that are separated by a pn‐junction and then flow to electrical contacts on the front and back sides to perform work in external circuit, as shown in the Figure 1. In addition, due to several advantages of n‐type (typically phosphorus‐doped) silicon wafers over p‐type (typically boron‐doped), including better tolerance to common impurities (e.g. iron) [1], higher bulk lifetime and no light‐induced degradation (LID) [2], n‐type silicon solar cells with high efficiency can be potentially more cost‐effective than p‐type silicon solar cells. Hence, the focus in this chapter will be on high‐efficiency front junction n‐type crystalline silicon solar cell with both sides passivated and contacted, including their operating principle, advanced cell structures, surface passivation and fabrication schemes.

Figure 1.

Schematic energy band diagram of a front junction n‐type silicon solar cell in a non‐equilibrium (with illumination), including photon absorption, carrier generation and separation.

2. Operating principle of a front junction n‐type silicon solar cell

The operating principle of a front junction n‐type silicon solar cell is described in Figure 1 via the band diagram. The p+ emitter region is formed by ‘doping’ the front side of a n‐type silicon wafer with boron dopants in high concentration, and the conjunction of the p+ region and the n substrate forms the pn‐junction. Due to the doping concentration gradient across the pn‐junction, electrons flow by diffusion from the n region into the p+ region, and holes flow from the p+ region to the n region [3]. This leaves behind exposed charges on ionized boron and phosphorus doping atoms at lattice sites, which form the space charge region. These exposed charges build up an electric field that opposes the natural flow of electrons and holes until and equilibrium scenario is reached with a fixed space charge width and electric field [4]. This built‐in electric field also causes a bending of the conduction band (EC) and the valence band (EV) (Figure 1). When the solar cell is illuminated, photons with energy greater than the silicon band gap energy (Eg) are absorbed to excite electrons from the valence band to the conduction band, which generates an electron‐hole pair. The generated electrons and holes can diffuse within the bulk of the solar cell until they reach the space charge region, if they avoid recombination or trapping by defects. Then, the electric field at the pn‐junction separate these carriers by sweeping electrons to the n region and holes to the p+ region. In the case of illumination, quasi‐Fermi levels (EFn for electrons and EFp for holes) are used to analyse the solar cell in non‐equilibrium (Figure 1). The electrical contact to the front p+ emitter region is described as an ohmic contact while the metal contact to n region, without any heavy doping, is generally a Schottky‐type because the metal contact to n silicon induces a barrier to majority carrier (electrons) [3]. In order to obtain high cell efficiency, proper doping profiles in both the p+ and the n regions are necessary to reduce the contact resistance and the metal‐induced recombination.

2.1. Solar cell parameters

According to the ideal diode law (one diode model), an actual silicon solar cell with parasitic series resistance (Rs) and shunt resistance (Rsh) can be described by an equivalent circuit containing one diode as shown in Figure 2 and is often expressed as [3, 4]

Figure 2.

Equivalent circuit of a front junction n‐type silicon solar cell with parasitic series resistance (Rs) and shunt resistance (Rsh) [3, 4].

I=ILI0{exp[V+IRs(nkTq)]1}V+IRsRshE1

where I is the terminal current, IL is the light‐generated current with illumination, I0 is the saturation current (the solar cell leakage current in the dark), V is the terminal voltage, q is the electronic charge, k is the Boltzmann's constant, T is the absolute temperature and n is the ideality factor that is typically in the range of 1 and 2.

The resulting I‐V curve with illumination is often plotted as output power, as shown in Figure 3. The maximum power point (MPP) is also indicated at (Vmp, Imp). The fill factor (FF) is another important parameter determining cell performance, and it is a metric of the pn‐junction quality and the parasitic resistance of a finished silicon solar cell [3]. FF is a measure of the squareness of the I‐V curve and defined as

Figure 3.

A typical representation of an illuminated I‐V curve as well as output power curve as a function of voltage, including indication of short circuit current (Isc), open circuit voltage (Voc) and the maximum power point (Voc and Isc) [3, 4].

FF=ImpVmpIscVocE2

where Imp and Vmp are the corresponding current and voltage at the maximum power point, Isc is the current at short circuit condition (V=0) and Voc is the voltage at open circuit condition (I=0) [3, 4]. Finally, the most important metric of solar cell performance is the energy conversion efficiency and is defined as

η=IscVocFFPinE3

where Pin is the total incident light power striking the solar cell [3]. According to the detailed balance limit of efficiency, the maximum efficiency of an ideal single‐junction crystalline silicon solar cell with Eg of 1.12 eV at 25°C is about 30% [5]. Its major fundamental mechanisms of power loss include (1) photons with energy less than 1.12 eV (<Eg) cannot be absorbed and directly transmitted through the cell, (2) the excessive energy in photons with high energy (>Eg) is wasted via thermallization as the generated electron‐hole pair relax back to the edges of carrier band, (3) each absorbed photon creates only one electron‐hole pair regardless of its energy, and (4) as shown in Figure 1, quasi‐Fermi levels (EFn and EFp) stay within energy gap (|EFnEFp|< Eg), hence pn‐junction silicon solar cells are inherently capable of giving voltage output smaller than the potential corresponding to its band gap energy [3, 5].

2.2. pn‐junction formation

To form the pn‐junction on n‐type crystalline silicon wafers, a typical approach is to diffuse boron atoms into the silicon substrates at high temperature. This can be accomplished by several techniques including depositing boron‐doped silicon oxide via atmospheric pressure chemical vapour deposition (APCVD) and then thermal annealing at high temperature [6]. The boron emitter can be also formed by spinning‐on orthoboric acid (H3BO3) solutions [7, 8], which is considered to be a hydrate of boric trioxide (B2O3). During the subsequent thermal annealing, the boron oxide reacts with silicon to form SiO2 and B, which diffuses into silicon at high temperature, as described by

2B2O3+3Si3SiO2+4BE4

Screen‐printed boron emitters have also been explored by printing proper boron‐containing paste followed by a thermal drive‐in diffusion [9]. Another promising and widely used technology is called ‘BBr3 diffusion’ that involves a direct thermal diffusion of boron atom from a liquid boron tribromide (BBr3) source [10]. In this process, pure nitrogen (N2) carrier gas flows into a bubbler containing liquid BBr3, which creates and transports gaseous BBr3 into the quartz tube and deposits on the surface of silicon wafers loaded in a quartz boat [11]. During this deposition stage, a boron oxide layer is formed on the silicon wafer surface in the oxygen (O2) ambient according to

4BBr3+3O22B2O3+6Br2E5

This thin boron oxide layer contains very high concentration of inactive boron element on the silicon surface. So, a high temperature anneal (typically ≥950°C) is necessary to activate boron atoms and diffuse them into silicon bulk to form the p+ region through the reaction (4) [11]. During this process, a SiO2/B2O3 stack or the borosilicate glass (BSG) layer is formed on the surface that has to be removed to achieve better dielectric surface passivation quality. By controlling gas flow rate, diffusion temperature and duration, proper boron dopant profiles can be engineered [12].

Because all of these junction formation technologies suffer from wrap‐around or naturally double‐sided diffusion process, etching off one side or depositing a mask layer on one side is needed to prevent junction shunting. Therefore, ion implantation has been investigated and implemented as a promising alternative technology that has a unique characteristic to provide single‐sided diffusion and facilitates the development of next‐generation cells [13]. It can simplify the junction formation process by eliminating the extra processes of masking and etching. In addition, ion implantation offers other technical advantages, including (1) high junction uniformity, (2) flexibly and precisely controlled dopant profiles, (3) elimination of the edge isolation process, (4) capability of patterned doping for selective doping and (5) elimination of the dopant glass (i.e. BSG layer) removal process [14]. It is important to note that ion implantation forms an amorphous layer on the surface [15], therefore, a very high temperature (≥1000°C) is needed to recover lattice damage and activate dopants [16, 17]. In addition, proper ion dose, implant energy and anneal conditions are essential to obtain desired dopant profiles [18, 19]. Current ion implantation tools have throughput of more than 2000 wafers per h but the capex and maintenance is much higher than the traditional diffusion tubes [13]. Figure 4 shows two examples of boron emitter profiles measured by electrochemical capacitance‐voltage (ECV) profiling technique, revealing that the boron concentration decreases towards the silicon wafer surface due to the higher solubility of boron in the SiO2 layer than in silicon bulk [20].

Figure 4.

Two measured ECV profiles of ion‐implanted boron emitters with sheet resistance of 80 and 200 Ω/□ [16, 20].

2.3. Metallization

In order to extract electrical power from a silicon solar cell, metal contacts have to be applied to the front emitter and the rear base to collect the generated electron‐hole pairs. The collected electrons flow through the n+ regions into the external circuit to power the load and then recombine with the generated holes. In order to minimize the power loss, the electrical contact needs to have low contact resistance with doped silicon regions, low metallic resistance in the formed structure, good adhesion to silicon and reliable solderability for cell interconnection for module production [21]. There are several metallization technologies that are typically used in photovoltaic industry for research and production. First, the screen printing of metal pastes to form electrical contact is the most widely applied technology to manufacture silicon solar cells in photovoltaic industry today because it is very robust, simple, high‐throughput, low‐cost and reliable method [21]. Its first application dates back to 1970s. In this metallization process, a metal paste is printed through a patterned screen with well‐designed openings onto a wafer lying under the screen. This screen acts as a mask, consisting of a mesh of wires partially covered with an emulsion. By properly optimizing some key process parameters, including the snap‐off distance between screen and wafer, the printing pressure (pressing the screen against the wafer surface and pushing the metal paste onto wafer surface) and the printing speed, printed gridline with high aspect ratio can be obtained today with line width of ≤60 µm and height of ∼25 µm (Figure 5(A)) [16]. Then, the contact formation is realized by a firing process in a conveyor belt furnace that fires the metal pastes through the passivation layer and anti‐reflection coating (typically silicon nitride SiNx) on the front. During this firing process, hydrogen (H) is released from the hydrogen‐rich SiNx layer into the crystalline silicon to passivate bulk and interface defects to increase the cell performance [23, 24].

Figure 5.

(A) Optical scope image of screen‐printed gridline. (B) Scanning electron microscope image of photolithographically defined and plated gridline. (C) Optical scope image of laser‐opened point contact pattern for physical vapour deposited metallization [16, 22].

Second contact technology involves metal plating approach that offers low contact resistivity, good gridline conductivity and narrow gridline width (low metal shading). Thus, it is a promising alternative to the screen‐printing technology but metal plating typically requires an initial patterning step to create openings in a dielectric masking layer for the subsequent self‐aligned metallization [21]. The openings can be defined by photolithography [10] or laser ablation, and then the contacts are applied by electroless plating [25] or a combination of light‐induced plating (LIP) and electroplating in an inline plating machine [26]. For industrially feasible plated metallization, nickel (Ni) layer is typically used, first to obtain low contact resistivity and prevent copper (Cu) diffusion followed by copper plating to provide excellent line conductivity and low material cost (compared to silver) [27]. The gridline width after plating is typically around 30 µm, with height of ∼15 µm, as shown in Figure 5(B).

Third contact technology involves physical vapour deposition (PVD) that is attractive because of its potential advantages of lower specific contact resistance [28], reduced wafer breakage and processing of thinner wafers due to non‐contacting process. In addition, a thin (1∼2 µm) PVD aluminium (Al) on the entire rear area is sufficient to meet the required electrical conductance for large area silicon solar cells, which can lead to less wafer bow and less metal material consumption [22]. In order to form the contact between silicon and PVD metal, patterned openings through a dielectric masking layer are needed for the subsequent PVD metallization, which is typically created by laser ablation. Figure 5(C) shows an example of rear point contact pattern (300 × 300 µm2) after laser ablation, with the opening diameter of ≤40 µm and metal coverage of ≤1.4% [22]. To obtain a good solder contact to the PVD Al side, deposition of a double layer of Ni:V/Ag on top of PVD Al layer is often implemented to provide an excellent solderability and long‐term stability for module manufacturing [29].

2.4. Optical, resistive and recombination losses in a solar cell

Theoretical maximum Jsc of ∼44 mA/cm2 can be achieved for a single‐junction crystalline silicon solar cell, if all the striking photons with energy higher than silicon band gap (EphotonEg) are absorbed and all the electron‐hole pairs generated contribute to the cell current [3]. However, several optical losses can cause lower current density in real cells, including reflection at the front side (metal gridline and front surface), absorption in the metal and dielectric layers on both sides, absorption via free‐carrier absorption in highly doped regions and transmission (without being absorbed in the cell). It is important that the front metal shading should be as low as possible without contributing to significant increase in series resistance. Therefore, grid pattern needs to be optimized to minimize the resistive and optical losses. Finally, the size of pyramid on the front side should be as small as possible after the saw damage removal and texturing process to minimize the line width due to spreading of screen‐printed metal.

Actual silicon solar cells also suffer from ohmic losses due to parasitic resistance Rs and Rsh. Rs is mainly attributed to the sheet resistance of doped regions (p+ emitter and n+ back surface field) in the case of two dimensional current flow, bulk resistance of silicon substrate, metallic resistance of gridline and specific contact resistance between silicon and metal. Each of these resistive components can be approximately estimated by using a model and calculation approach [30] to minimize total Rs and achieve high FF. Rsh is a factor monitoring the non‐ideality of the pn‐junction and some defects near junction, especially edge shunting. Both high Rs and low Rsh can result in low FF and cause power loss.

Apart from optical and ohmic losses, recombination of generated carriers can reduce Jsc and Voc and limit the cell performance. There are two different intrinsic recombinations in semiconductor materials, namely Auger recombination and radiative recombination. Auger recombination is dominant in the heavily doped p+ and n+ regions. Auger recombination represents the process in which electron and hole recombine first by band‐to‐band radiative recombination and use the excess energy to excite another majority carrier (electron) in the conduction band for n+ silicon or hole in the valence band in the case of p+ silicon. Then, this excited carrier thermalizes towards the band edge by emitting phonons. Auger recombination strongly depends on majority carrier density; hence it is very effective in the heavily doped regions (p+ emitter and n+ back surface field). Radiative recombination refers to a process in which electron makes direct band‐to‐band transition to recombine with a hole in the valence band while emitting light. Because silicon is an indirect band gap material and a phonon is required for the band‐to‐band transition, this recombination mechanism is often neglected in silicon solar cell. A third and important bulk recombination mechanism is called SRH recombination (named after Shockley, Read and Hall [31, 32]), which is initiated by the energy levels created within the forbidden gap by impurities or defects. These energy levels form a stepping stair to facilitate the recombination of holes and electrons, which is a function of energy level location, trap density and its capture cross‐sections [31, 32]. Generally, mid‐gap or deeper traps are more efficient recombination centres. Because all three recombination mechanisms occur in parallel, the silicon substrate bulk lifetime (τbulk) is expressed as

1τbulk=1τAuger+1τradiative+1τSRHE6

where τAugeris the Auger lifetime, τradiativeis the radiative lifetime and τSRHis the SRH lifetime.

In addition to these three bulk recombination mechanisms, surface recombination is also very critical for cell performance. This is because dangling bonds present at both surfaces of the wafer induce defect levels within the forbidden band gap. Surface recombination is characterized by a surface recombination velocity that is a function of surface state density and cross‐section of surface traps [31]. To account for all the four recombination mechanisms, an effective lifetime (τeff) is used, and given by

1τeff=1τbulk+2sdE7

where s is the surface recombination velocity (SRV) and d is the silicon wafer thickness. All recombination processes not only reduce the maximum short circuit current density (Jsc) but also diminish the maximum Voc. According to Eq. (8), the total saturation current density (J0,total) in Eq. (1) strongly influences Voc because

Voc=nkTqln(JscJ0,total+1)E8
J0,total=J0e+J0b, bulk+J0b'E9

where J0e, J0b,bulk and J0b’ are the saturation current density contributions from front emitter, bulk wafer and back side, respectively. These parameter values can be directly measured and extracted from the quasi‐steady‐state photoconductance (QSSPC) technique [33]. Due to the progress and availability of high lifetime wafers and current photovoltaic industry trend towards thinner wafers for cost reduction, passivation of front and rear surfaces is becoming vitally important for achieving higher efficiency silicon solar cells.

3. Surface passivation of crystalline silicon solar cells

At the silicon wafer surface, the covalent silicon‐silicon bonds of crystal lattice are broken during wafer slicing, which creates non‐saturated (‘dangling’) bonds that are often referred as ‘surface states’ and can easily trap electrons from the conduction band or holes from the valence band as some of the energy levels are located near mid‐gap. In order to keep surface recombination losses at a tolerable level, the wafer surfaces must be electronically well passivated. According to the Shockley‐Read‐Hall theory [31], the SRV depends on several features, including the properties of the surface states, state density, their capture cross‐sections for electrons and holes, the injection level at the surface and the wafer doping level [34]. Therefore, SRV can be decreased by two technical approaches: (1) the chemical passivation by reducing the surface state density via depositing or growing a passivating dielectric film on the silicon surface and (2) the field‐effect passivation by reducing the concentration of one charge carrier type (either electrons or holes) at the surface via forming an internal electric field below the silicon surface with doping profile or electrical charges in dielectric insulator. Practically, these two fundamental passivation approaches are often applied together to minimize the SRV. For front junction n‐type crystalline silicon solar cells, the electronic quality of front boron emitter and back surface are usually expressed and quantified by J0e and J0b’. In a typical solar cell, there are two fundamentally different types of surface regions: metallized and non‐metallized. Non‐metallized surface regions are usually covered with dielectrics and are referred to as passivated regions. In order to achieve high cell efficiency, both J0e and J0b’ should be as low as possible.

3.1. Front boron emitter passivation

In order to take the advantages of high bulk lifetime n‐type crystalline silicon wafers, excellent passivation of the boron emitter is essential to reduce the SRV or the emitter saturation current density of the passivated region (J0e, pass). It is well known that aluminium oxide (Al2O3) contains a high density of built‐in negative charges on the order of ∼1013 cm‐2 [35], so the majority carrier (hole) is accumulated and minority carrier (electron) concentration is effectively reduced at the Al2O3‐passivated boron emitter surface, and consequently, the SRH recombination on the surface or the SRV is reduced. Experimentally, very low J0e, pass in the range of 10∼30 fA/cm2 has been demonstrated on 150 and 54 Ω/□ is the standard unit to describe a sheet resistivity for emitter or back surface field for silicon solar cells in the photovoltaic field. sheet resistance p+ emitters with surface doping concentrations around 1019 cm‐3 (prepared by BBr3) and Al2O3 passivation synthesized by plasma‐assisted atomic layer deposition (ALD) (Figure 6) [36].

It is also shown that with ALD‐Al2O3 passivation, ion‐implanted boron emitters (post‐implant anneal at 1040°C for 1 h) demonstrate noticeably higher J0e, pass at <150 Ω/□ sheet resistance, but similar passivation performance for ≥150 Ω/□ sheet resistance, compared to the BBr3‐prepared emitters (oxidation anneal at 1050°C). This is due to higher surface doping concentration (∼5 × 1019 cm‐3) resulted from lower oxidation temperature and shorter oxidation time. In addition, thermally grown silicon oxide (SiO2) also demonstrates decent surface passivation for the boron emitters with J0e, pass in the range of 60∼110 fA/cm2. However, silicon nitride (SiNx) deposited by plasma‐enhanced chemical vapour deposition (PECVD) does not effectively passivate boron‐doped emitters (Figure 6) due to the presence of positive built‐in charge. Furthermore, hydrogen‐rich amorphous silicon yields the passivation performance comparable to SiO2 [37].

Figure 6.

Measured emitter saturation current density on passivated region J0e,pass as a function of the sheet resistance for ion‐implanted boron emitters passivated by SiNx, thermal SiO2 and Al2O3. BBr3‐prepared and Al2O3‐passivated boron emitter reported in Ref. [36] is cited for comparison purpose.

3.2. Rear surface passivation

In practice, there are two different types of surfaces on the rear side of front junction n‐type silicon solar cells: diffused and non‐diffused. Thermal SiO2 film is very effective in passivating n‐type silicon surface because it not only reduces the surface state density but also leads to a field‐effect passivation due to positive fixed oxide charge [38]. It can reduce non‐diffused n‐type silicon surface SRV values below 10 cm/s [39]. Thermally grown SiO2 is also very effective in passivating phosphorus‐doped silicon surfaces. Since the phosphorus dopants in the diffused back surface of a n‐type cell have the same polarity as the n‐type silicon wafer, this doping profile creates a high‐low junction (n+n), the so‐called back surface field (BSF). The corresponding electric field formed by the rear high‐low junction of a BSF can very effectively shield holes from the rear surface, dramatically reducing rear surface recombination losses.

Figure 7.

Saturation current density of phosphorus‐doped and planarized rear surface J0b,pass as a function of the ion‐implanted phosphorus dose [41, 42].

SiNx formed by PECVD provides excellent passivation for n‐type surfaces because of its field‐effect passivation provided by positive interface charges and the properties of the capture cross‐sections of the dominant interface defects. Although the surface state density at Si‐SiNx interface is much higher than that in the case of thermally grown Si‐SiO2 interfaces, SiNx demonstrates additional advantages for silicon solar cells: (1) excellent anti‐reflection coating (ARC) on the rear side, which is suitable for bifacial architecture and (2) releasing large amounts of hydrogen during a high temperature (∼800°C) contact firing process to passivate interface and bulk defects (‘hydrogen passivation’ [40]).

In front junction n‐type silicon solar cells, phosphorus‐doped rear surfaces are typically passivated by the combination of thermal SiO2 and SiNx stacks. Figure 7 shows that very low saturation current density has been demonstrated on planarized back surface with ion‐implanted BSF J0b,pass of ≤20 fA/cm2 for low phosphorus dose and J0b,pass of ∼80 fA/cm2 for high phosphorus dose with doping concentration of ∼2 × 1020 cm‐3, which is compatible with screen printing [41, 42]. The J0b,pass of ≤100 fA/cm2 has also been reported for SiO2/SiNx‐passivated ion‐implanted and POCl3 formed BSF on textured surface [42, 43], which are suitable for fully screen‐printed bifacial front junction n‐type silicon solar cells [17].

3.3. Carrier selective tunnel oxide passivated rear contact

Figure 8.

(A) Transmission electron microscopy image and (B) schematic band diagram of tunnel oxide passivated contact structure [45].

Current high‐efficiency front junction n‐type silicon solar cells are often limited by the recombination in the heavily doped regions and at the metal/silicon contacts. A possible solution for minimizing doping and contact recombination is to insert a passivating material with offset bands between the metal and silicon, also known as passivated contact. One approach to accomplish this is to use an amorphous silicon‐based heterojunction (HIT solar cell), which suppresses recombination effectively and which has resulted in outstanding cell Voc of 750 mV [44]. However, this passivation scheme can withstand only low temperature (≤250°C) back‐end process, hence is not compatible with the industry standard screen‐printing and firing metallization technology [45]. Another approach to achieve a passivated contact involves a chemically grown ultra‐thin (∼15 Å) tunnel oxide capped with phosphorus‐doped n+ polycrystalline silicon (as shown in Figure 8(A)) and metal contact on the entire back side of n‐type silicon cell [45], which is referred to as the tunnel oxide passivated contact (TOPCON) [46, 47].

In this TOPCON structure, four parallel mechanisms contribute to carrier selectivity (as shown in Figure 8(B)) [45]. (1) Heavily doped n+ polycrystalline silicon creates an accumulation layer at the absorber surface due to the work function difference between the n+ polycrystalline silicon and the n‐ silicon absorber. This accumulation layer or band bending provides a barrier for holes to get to the tunnel oxide while electrons can migrate easily to the oxide/Si interface. (2) Tunnel oxide itself provides the second level of carrier selectivity because it presents a 4.5 eV barrier for holes to tunnel relative to 3.1 eV for electrons [48]. (3) There are very few or no states on the other side of the dielectric for holes to tunnel through because the valence band edge of n‐ silicon absorber is facing the forbidden gap of n+ polycrystalline silicon. (4) Even if a hole is able to tunnel through the oxide, it sees much higher resistance due to the n+ polycrystalline silicon regions to get to the metal contact for recombination while the majority carrier electrons can easily get there. Last but not least, due to the full area metal contact on the back, there is one‐dimensional (1D) current flow. This eliminates the lateral transport resistance (2D carrier flow), resulting in much higher FF. Therefore, this passivated contact is highly carrier selective and allows the flow of majority carriers via tunnelling while blocking minority carriers.

Figure 9.

(A) Implied Voc and J0b’ as a function of the PH3/SiH4 ratio during PECVD. (B) Implied Voc and J0b’ as a function of the polysilicon anneal temperature [45].

To obtain an efficiently doped n+ polycrystalline silicon layer to maintain the quasi‐Femi level splitting in silicon absorber (high Voc), a proper PH3/SiH4 ratio during PECVD is required for forming the phosphorus‐doped amorphous silicon layer [45]. Figure 9(A) displays that if the PH3/SiH4 ratio is too high (high doping level in as‐deposited amorphous silicon layer), the surface passivation quality degrades as indicated by low implied Voc (iVoc) and high saturation current density J0b’ obtained on symmetrical TOPCON structure. This is because more phosphorus dopants diffuse from the n+ polycrystalline silicon layer through the tunnel oxide into the silicon absorber, resulting in high Auger recombination, as well as high recombination at the silicon/SiO2 interface [49]. However, very low PH3/SiH4 ratio also causes inferior surface passivation due to the small band bending or weak accumulation layer created by the reduced doping in the n+ silicon layer, resulting in very weak field‐effect passivation. In addition, to facilitate the solid‐phase crystallization and activate the phosphorus dopants in the as‐deposited n+ amorphous silicon layer, a proper polysilicon anneal temperature is necessary as shown in Figure 9(B). However, a strong degradation in the interface passivation quality is observed if the anneal temperature is too high (≥900°C), again due to more dopant diffusion into the silicon base causing high Auger recombination and possible local disruption of tunnel oxide due to polycrystalline silicon grain growth and more interface defects [45, 46]. It has also been demonstrated that both the tunnel oxide growth temperature in nitric acid and the high temperature firing process can affect the passivation quality. A very low J0b’ of ≤5 fA/cm2 has been achieved by optimizing the TOPCON fabrication processes [50]. Similar passivation performance has also been achieved by depositing intrinsic amorphous silicon layer on top of the tunnel oxide layer followed by ion implantation of phosphorus and thermal annealing [51].

4. High‐efficiency front junction n‐type crystalline silicon solar cells

All front junction n‐type crystalline silicon solar cell structures fabricated to date feature some degree of surface passivation. In the following section, we discuss several types of advanced high‐efficiency front junction solar cells that have been developed on n‐type silicon substrates.

4.1. Passivated emitter with rear totally diffused (PERT) cells

Figure 10.

(A) Schematic of front junction n‐type PERT cell with bifacial feature [52, 53]. (B) Schematic of front junction n‐type PERT cell with rear point contacts [22].

Even though p‐type silicon solar cells dominate the PV market today, in recent years, several academic groups and companies have started to investigate front junction n‐type crystalline silicon solar cells. The schematic of front junction n‐type PERT ‘passivated emitter rear totally diffused’ [52, 53] cell is shown in Figure 10. PERT cell structure featuring a bifacial architecture is shown in Figure 10(A), which can collect radiation from the rear side of the solar cell, hence has the potential to achieve an increased energy yield (5∼20%) in certain module configurations. The PERT cell structure in Figure 10(B) shows the rear point contact that can reduce the rear metal‐induced recombination due to lower metal coverage, as well as reduce the lateral resistance due to smaller contact pitch [22].

Table 1 shows that 21.9% cell efficiency has been reported on thermal SiO2‐passivated boron emitter formed by BBr3 diffusion [53] while 22.7% cell efficiency has been achieved via Al2O3‐passivated boron emitter formed by ion implantation and photolithography on small area n‐type float zone (Fz) substrates [54] with rear point contacts. To make manufacturable n‐type PERT cells, screen‐printing metallization has been applied on large area n‐type Czochralski (Cz) silicon substrate with excellent cell efficiencies approaching 21% featuring bifacial architecture [17, 55], as listed in Table 1.

Literatureη (%)Voc (mV)Jsc (mA/cm2)FF (%)Area (cm2)StructureYear
[54]21.969541.176.54 (FZ)Rear point contact2002
[55]22.769140.980.24 (FZ)Rear point contact2014
[56]20.565539.579.1239 (CZ)Bifacial2014
[57]21.066539.879.3239 (CZ)Bifacial2015

Table 1.

Light I‐V results of high‐efficiency front junction n‐type PERT silicon solar cells.

The detailed characterization and analysis show that the 22.7% efficient PERT cell is largely limited by the rear side recombination (J0b’) due to the totally diffused BSF layer (J0b,pass), with J0b’ (J0b,pass+J0b,metal=29+4) = 33 fA/cm2, J0e (J0e,pass+J0e,metal=12+16) = 28 fA/cm2 and J0b,bulk = 10 fA/cm2 [54]. Therefore, to further improve the cell performance, the recombination in this heavily doped full BSF layer needs to be reduced. This can be accomplished by locally diffused BSF (PERL) structure on the rear side.

4.2. Passivated emitter with rear locally diffused (PERL) cells

The concept of ‘passivated emitter rear locally diffused (PERL)’ structure was introduced and developed in 1990s [56], in order to reduce the recombination from the rear side. The PERL schematic is shown in Figure 11(A), which can diminish the heavy doping effect by using locally phosphorus‐diffused area and decrease the metal‐induced recombination simultaneously via heavy doping (n++) underneath the contact metal. By upgrading from PERT to PERL structure, the J0b’ can be significantly reduced (from 33 to 15 fA/cm2), which can lead to an increase in Voc from 691 to 704 mV [10]. However, because the rear metal contact of PERL cell is restricted to a small fraction (<1%) of the rear surface, the carrier flow towards contact is constricted, which is beneficial for minority carriers (holes) but detrimental for majority carriers (electrons). On one hand, for minority carriers, such constriction is equivalent to reducing the conductance in the direction of the rear contact, which facilitates the build‐up of their concentration inside the solar cell resulting in higher Voc. However, for majority carriers, a lower conductance causes higher lateral resistive losses resulting in lower FF [57]. Hence, a trade‐off between Voc and FF needs to be considered. By optimizing the cell fabrication process to reduce contact resistance, a 23.9% efficient front junction PERL cell on small area n‐type Fz substrate with photolithography contacts was reported [58] with Voc of 705 mV and FF of 82.5%. The detailed characterization and analysis shows that this 23.9% efficient PERL cell is limited by metal recombination on the front (J0e,metal) and the rear side recombination J0b’, with total J0e of 30 fA/cm2 (J0e,pass=10,J0e,metal=20), J0b,bulk = 10 fA/cm2 and J0b’ = 15 fA/cm2 [54]. To further reduce recombination losses, selective emitter with heavier and deeper boron doping profile underneath front contact metal is typically implemented, as shown in Figure 11(B), which can dramatically decrease the front metal‐induced recombination (from 1800 to 200 fA/cm2) resulting in J0e,metal reduction from 20 to 2 fA/cm2 on the contacted region assuming ∼1.1% metal coverage [10, 59].

Figure 11.

Schematic of front junction n‐type PERL cell (A). (B) Front junction n‐type PERL cell with selective emitter [56, 58].

4.3. Tunnel oxide passivated contact cells

The implementation of polysilicon tunnel junction as an alternative to either totally or locally diffused junction to reduce the recombination at the contact of silicon solar cells has been reported in the 1980s [60]. Because of its excellent surface passivation and carrier selectivity, a full area TOPCON shown in Figure 12(A) was applied, which also enables one‐dimensional (1D) carrier transport on the rear side to eliminate FF losses due to 2D/3D carrier transport in the PERT and PERL cells.

Figure 12.

(A) Schematic of front junction n‐type TOPCON cell with selective emitter [59, 61]. (B) Schematic of large area front junction n‐type TOPCON cell with screen‐printed and fired front contact [45].

In addition, because both the heavy doping effect and the metal‐induced recombination are minimized in TOPCON structure, J0b’ is dramatically reduced from ≥15 fA/cm2 in a PERL cell to ≤8 fA/cm2 in TOPCON cell [50, 54, 59]. A small area (4 cm2) 24.9% efficient TOPCON cell has been reported [59] with selective boron emitter and photolithography contacts on the front in conjunction with TOPCON back (Figure 12(A)). This cell had a Voc of 719 mV, Jsc of 41.5 mA/cm2 and FF of 83.4% [59]. More recently, an efficiency of 25.1% is reported by moving the busbars outside the cell with Jsc of 42.1 mA/cm2 [61].

Figure 13.

Simulated J0 decomposition with each technology for large area front junction n‐type PERT, PERL and TOPCON cells [62, 63].

To implement TOPCON on a more manufacturable cell structure, large area front junction n‐type Cz silicon solar cells have been developed with ion‐implanted boron emitter, SiNx anti‐reflection coating and screen‐printed front contact, as shown in Figure 12(B), and cell efficiency of 21.4% with evaporated rear contact has been reported [45]. Figure 13 shows the simulated road map to achieve ≥23% efficient large area front junction n‐type silicon solar cells, including the reduction of all the J0 components (J0e, J0b, bulk and J0b’) in the cell [62, 63]. It is clearly shown that selectively doping is one of the most manufacturable and elegant way to reduce J0 of the metallized and diffused regions simultaneously. This is because heavy diffusion underneath grid reduces metal J0 and light diffusion in between the gridlines reduces J0 of the diffused region. The 2D modelling shows that the cell efficiency can be increased from 21.0 to ∼22.5% (bifacial architecture) by applying selectively doped emitter and BSF on large area n‐type Cz wafers. Moreover, implementing TOPCON structure on the rear side can raise the cell efficiency over 23% with screen‐printed contact on the front in combination with improved bulk material (10 Ω‐cm, 3 ms lifetime).

5. Summary and outlook

In this chapter, the physics and operation of front junction n‐type silicon solar cells is described, including detailed cell parameters, pn‐junction formation, metallization approaches and fundamental power loss mechanisms. To reduce surface recombination velocity for achieving high cell efficiency, Al2O3 has been approved to be very efficient on passivating heavily boron‐doped front emitter and thermal SiO2 is very effective to passivate phosphorous‐diffused regions. In addition, to minimize the metal‐induced recombination, implementation of selective boron emitter on the front side and locally‐diffused back surface field on the rear side are preferred. Furthermore, TOPCON passivation scheme shows even better performance by simultaneously reducing the metal‐induced recombination and the heavy doping effect, and allowing for 1D carrier transport. However, it is only suitable for being applied on the rear side of solar cell because the heavily doped polysilicon layer can absorb significant amount of incoming photons (hence low Jsc), if it is located on the front side.

High‐efficiency front junction n‐type silicon solar cells, including PERT, PERL and TOPCON cells, are reviewed and analysed. In combination with low‐cost screen‐printed metallization technology, PERT bifacial cell structure with homogeneous doping profiles on both front and back sides is a promising candidate of next‐generation solar cells for industrial application in terms of process simplicity and energy yield while the recently developed cell structure with TOPCON on the rear and selective boron emitter on the front demonstrates the promise of this technology option for higher cell efficiency.

Acknowledgments

The authors would like to thank all other group members of UCEP in Georgia Tech and R&D department of Suniva, Inc. for their great support. This work was supported by the DOE FPACE I and the FPACE II contracts, as well as the DOE Solarmat1 and the DOE Solarmat2 contracts.

© 2017 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Yuguo Tao and Ajeet Rohatgi (February 22nd 2017). High‐Efficiency Front Junction n‐Type Crystalline Silicon Solar Cells, Nanostructured Solar Cells, Narottam Das, IntechOpen, DOI: 10.5772/65023. Available from:

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