Sepcifications of potentiostat OTA from the experiment.
Driven by the demand of the bioelectronics market, many biosensors need to work in parallel or in a controllable way to achieve complicated biodetections, however the limited scale, speed, cost, complex signal processing, and bulky circuit routing problems prohibit the discrete biosensor solutions (Drummond et al., 2003). Nowaday biosensor are usually integrated on the same substrate to form biosensor array to improved the scale and efficiency, and solve the signal routing difficulties.
CMOS technology emerges since the mid-1960s, and rapidly captured the IC market. The aggressive scaling of CMOS technology following the famous Moore’s Law enables the realization of high-speed digital circuits, analog and mixed-signal circuits, as well as radio-frequency (RF) communication circuits. A single chip monotonically integrating all components of a complex electronics systems or laboratory systems which contain digital, analog, mixed-signal, and RF communication, microelectromechanical systems (MEMS), and other experimental functions, i.e. lab-on-a-chip (LOC) is avidly to be implemented to possess the capabilities of high-efficiency characterization, high-speed complex signal processing and communication, mass production, large scale, low cost, and low power as well. Fortunately, most of the fabrication processes of biosensors are compatible with the standard CMOS technology either directly or via the post-CMOS processes, e.g. DNA sensors fabricated on Si-nanowire (Li et al., 2004) and gold surface (Cheng et al., 2005) etc, which makes it possible to integrate the biosneosr arrays and CMOS IC on a single chip as a CMOS integrated biosensing system (IBS) (Augustyniak et al., 2006; Prakash et al., 2006; Thewes et al., 2005; Han et al., 2007).
The CMOS IBS usually composes of four parts in its system circuitry: integrated biosensor array, interfacing circuits, analog-to-digital (A/D) conversion, and digital signal processor (DSP), as shown in Figure 1(a). In some system requiring feedback controlling during the characterization, digital-to-analog (D/A) converters are also included depending on the applications, as shown in Figure 1(b). In the system architecture of CMOS IBS, the overall performance such as noise, bandwidth, sensitivity etc are mainly governed by the performances of interfacing circuits which controls the electrolyte potential and directly acquires signals from the integrated biosensor array.
The three electrode system, as shown in Figure 2, is the most popular electrode architecture of the integrated biosensor array in nowadays CMOS IBS. The system is composed of reference electrode, working electrode, and counter electrode (it is also called auxiliary electrode sometimes).
Reference electrode is an electrode with a stable and well-known electrode potential. There are many types of reference electrode used in electrochemical systems, such as hydrogen electrode, copper-copper(II) sulphate electrode, silver chloride electrode etc, among which the silver chloride (Ag-AgCl) electrode is commonly employed in the IBS. In some systems with feedback stabilization, the reference electrode made from inert metals such as gold (Au), platinum (Pt) etc are also utilized to simplify the fabrication process.
Working electrode is an electrode in the IBS on which reaction of interest is occurring. Common working electrode is usually implemented in inert metals such as Au, Ag, Pt, etc. Most biosensors apply a control voltage on the working electrode in contact with the electrolyte while measuring the current by a signal acquisition circuit, as shown in Figure 2.
Counter electrode is an electrode used in the IBS from which the sensing current is expected to flow and is also made from inert metals in most cases. The potential on this electrode is opposite in sign to that of the working electrode. Counter electrode is usually connected with the reference electrode by a potentiostat in a negative feedback loop to stabilize the electrolyte potential with respect to a reference during the biosensing process, as shown in Figure 2. In some systems, acquisition circuit is combined into the potentiostat, but which is not against the architecture of the interfacing circuits we are discussing here.
The on-chip potentiostat circuit serving for stabilizations of electrolyte potential and accommodation of electrochemical current (Augustyniak et al., 2006; Prakash et al., 2006; Thewes et al., 2005) is one of the major components in the IBS, which is usually realized as an operational transconductance amplifier (OTA) ( Zhang et al., 2009 ). Table 1 shows the specifications of the potentiostat OTA from a typical biosensor system based on nano-particle assembly.
|Typical assembling voltage||1.8 ± 0.2 V|
|Min. assembling voltage||~1 V|
|Electrolyte potential range||0 to 1.8 V|
|Max. potential variation||5 mV|
|Assembling current range||~ 10 nA to ~ 100 µA|
|Max. signal bandwidth||< 100 kHz|
It can be seen that the assembling voltage range falls in the typical supply voltage range of standard CMOS technology, but due to the aggressive scaling of CMOS technology, typical supply voltage of mainstream CMOS process can barely satisfy the specifications in Table 1. For this reason, a potentiostat OTA with rail-to-rail input common-mode range is highly preferred in the CMOS IBS. On the other hand, considering the loading capability required by the assembling current range, a Class-AB output stage should also be incorporated for its bidirectional loading capability and high power efficiency.
The potentiostat OTA has been designed and illustrated in Figure 3. The potentiostat OTA uses the complimentary folded-cascode input stage composed of transistor M0 to M13 to achieve the rail-to-rail input common-mode range to enable the required assembling voltage, and reduce the input-referred noise to stabilize the potential as well, while incorporates the Class-AB output stage composed of transistor M29 to M32 to provide the maximized loading capability and accommodate the assembling current requirement. Transistors M14 to M21 function as the common-mode feedback circuit and provide biasing voltage for the folded-cascode input stage. M25 to M28 are two source follower to match the DC voltage between stages, while the other biases are served by M22 to M24 from a current IB. Simulation results show that biasing at a current of IB=1 µA the circuit is capable of providing a rail-to-rail input and output dynamic range and a unit gain bandwidth up to 42.7 MHz, while the output current headroom, I max, is over 450 µA, which meet the specifications in Table 1.
The potential variation is due to: (I) finite transconductance of the potentiostat OTA, (II) input referred noise, and (III) the input referred offset. If Gm DC is the DC transconductance of the potentiostat OTA, the potential variation, Vft , due to (I) can be expressed as
According to the noise theory, transistors M0, M1, M5, M6, M7, M8, M12, and M13 in the first stage contribute to the overall noise. The noise power spectral density, SI , in a MOS transistor is given by (Linares-Barranco et al., 2003; Linares-Barranco et al., 2004)
where γ is the thermal noise parameter, gm is the transconductance, Ids is the drain-source current, Cox , W, and L are the gate capacitance per unit area, transistor width and length, respectively, and k, T, and f are the Boltzman constant, temperature, and frequency, respectively. KF , AF , and EF are flicker noise parameters with the typical values of 2×10-25, 2, and 1, respectively. Since the corner frequency fc , where thermal noise and flicker noise exhibit the same power density, is calculated as 5.4 Hz by using parameters provided by the foundry, much smaller than the unit gain bandwidth, therefore, flicker noise is negligible in the proposed OTA, and the input referred noise voltage Virn can be characterized by
where gmj is the transconductance of transistor Mj, j = 0, 1,…, 32.
Virn can be diminished by increasing the biasing currents and aspect ratios of the input differential pairs, but trades off with the power consumption and the physical area. The spectral density input referred noise of proposed OTA on different common-mode input voltages are shown in Table 2.
Monte-Carlo simulation is also performed to characterize the input referred offset by utilizing the mismatch parameters provided by the foundry, and the results are also shown in Table 2. In the worst case with VCM = 0 V, the overall potential variation due to the above three issues is 4.12 mV, which implies an 8 bit of potential resolution and satisfies the boundary condition in Table 1. The other circuit performances are summarized in Table 2.
|Parameters||V CM = 0 V||V CM = 0.9 V||V CM = 1.8 V|
|DC transconductance||2.22 S||5.43 S||3.90 S|
|3- dB bandwidth||1.97 kHz||2.07 kHz||1.94 kHz|
|Phase margin||"/75 o||"/80 o||"/75 o|
|Max. output pull current||451 µA||451 µA||-|
|Max. output push current||-||459 µA||459 µA|
|Input referred offset||3.51 mV||1.60 mV||2.75 mV|
|Input referred noise||61.8 nV/µHz||38.2 nV/µHz||57.7 nV/µHz|
|Overall potential variation||4.12 mV||1.93 mV||3.24 mV|
|Potential resolution||8 bit||9 bit||9 bit|
|DC power dissipation||40.4 µW||50.3 µW||58.0 µW|
|Power supply||1.8 V||1.8 V||1.8 V|
3. Acquisition circuits
The design of acquisition circuits in the IBS is circumscribed by the sensing mechanism of the biosensor. In the electrical biosensing, there are two major schemes in analyte detection: direct current (DC) sensing and alternative current (AC) sensing.
In the DC sensing, a DC voltage is usually applied to the working electrode in an IBS, and the current flowing from counter electrode to the working electrode is measured (Augustyniak et al., 2006; Thewes et al., 2005). This method suffers from the large background noise in the electrolyte seriously, which prevent it from the applications requiring high sensitivities of biosensing.
In the AC sensing, the acquisition circuit senses the AC modulation current by applying an AC voltage superimposed on a DC biasing on the working electrode (Huang & Chen, 2008). Since only the background noise within the band-of-interest deteriorates the signal-to-noise ratio, the AC sensing has much better sensitivity than the DC sensing scheme.
|DNA releasing voltage||0.9 V|
|DNA modulation voltage||±0.5 V|
|Current headroom||±100 nA|
|Current sensitivity||~100 pA|
|Max. signal bandwidth||10 kHz|
|Min. sensor impedance||~5 MΩ|
A desirable acquisition circuit should usually accommodate both schemes of biosensing, however, as summarized in Table 3, the fastidious requirements, such as sensitivity, bandwidth, input range, etc., for the following circuits make great challenges to analog integrated circuit designers. There are various methods and circuits dealing with the ultralow current in biosensing applications, e.g., current integrator (sometimes it is called as potentiostat) (Ayers et al., 2007; Narula & Harris, 2006), transimpedance amplifiers (Rodriguez-Villegas, 2007; Basu et al., 2007), and ultralow current-mode amplifiers (ULCA) (Zhang et al., 2007; Ramirez-Angulo et al., 2004; Steadman et al., 2006; Zhang et al., 2009). The current integrator is capable of providing sub-picoampere sensitivity, however, the circuit bandwidth is typically below 1 kHz, which cannot fully accommodate the bandwidth of AC sensing. Transimpedance amplifiers possess wider bandwidth and good sensitivity, however, its dynamic range is limited by the supply voltage, which becomes a serious issue along with the scaling of supply voltage in today’s CMOS technology. The ULCA turns out to be a favorable candidate with high sensitivity, sufficient bandwidth, and wide dynamic range for IBS with AC sensing capabilities.
3.1. Circuit design of ULCA
In ULCA design, conventional transistor-strong-inversion-based current-mode circuits are out of consideration due to the large noise background induced by the dc quiescent current, and weak-inversion-based (subthreshold) current-mode circuits emerge as the candidates. Since the subthreshold circuits suffer from supply voltage fluctuations and die-to-die process fluctuations (Mead, 1989), they are usually closely integrated with other adjacent stages on a single die and share the same supply voltage, along with careful considerations on the matching, symmetry, and biasing issues (Linares-Barranco et al., 2003; Linares-Barranco et al., 2004; O’Halloran & Sarpeshkar 2004).
Some ULCA topologies have been reported (Zhang et al., 2007; Ramirez-Angulo et al., 2004; Steadman et al., 2006), as shown in Figure 4. The circuit in Figure 4(a) is working in the Class A mode. It uses a regulated current mirror to achieve the current amplification. The quiescent currents are provided by current sources, whereas the bandwidth is limited by capacitor C 0. Although the circuit provides good linearity over the input range, since the quiescent current I 0 should be low enough to reduce the noise level and meet the requirement of sensitivity, the specified current headroom (in both positive and negative directions) can hardly be achieved. One can certainly introduce the Class B complementary topology in Figure 4(b) to meet the headroom requirement and increase the sensitivity by removing the noise background induced by I 0; however, this comes at the cost of substantially losing bandwidth in the low-input cases.
To meet the specifications in Table 3, a Class AB ULCA aiming at biosensing amplification has been designed and verified in SMIC 0.18-µm CMOS mixed-signal technology (Zhang et al., 2009). The design elaborately considered the issues and tradeoffs over gain, bandwidth, noise, and offset. The experimental results show that the ULCA can completely satisfy the requirements of typical DNA-based IBS and is eligible to serve for the preamplification of ultralow biosensor signals in the IBS.
The ULCA schematic is shown in Figure 5. In this circuit, the current from DNA biosensors is input to a complementary regulated current mirror consisting of an N-type opamp AN0 , a P-type opamp AP0 , and transistors M0 , M1 , M3 , and M4 , where it is amplified by a factor of 10 (20 dB). The opamps AN1 and AP1 and the transistors M6−M11 compose a voltage limiter.
Due to the “virtual short” mechanism, “IN” is fixed at “REF” by AN0 and AP0 , and a quiescent current of I ref is established in M0 and M3 by AN1 and AP1 . When a positive input is applied Vn , the output of the opamp AN1 reduces, thus turning off M2 . The current of M 0 and M 1 is sunk by AP0. On the other hand, since Vp tends to drop down, the current provided by AN0 becomes smaller. However, M5 is turned on by AP1 to compensate the current at node Vp, which limits Vp from dropping and maintains the quiescent current of M0 and M3 equal to the reference current Iref provided by M6−M9, even if the input current IIN is much larger than Iref. A similar conclusion can also be made for the negative input cases.
It can be seen that M2 and M5 alternatively sustain the quiescent current for the current mirror, which in turn keeps a constant bandwidth as the input varies between positive and negative directions. Furthermore, Iref can be designed small enough to achieve the required sensitivity and noise level without being restricted by the current headroom, since the current headroom no longer depends on the magnitude of the quiescent current in the ULCA. Therefore, the circuit can provide an extremely high sensitivity and a large current headroom at the required bandwidth. Due to the variation and pad leakage issues, Iref is unpractical to be provided off-chip. Therefore, three steps of current mirroring are introduced by M12−M16 in the biasing stage, where each step achieves a conversion factor of 0.1. A microampere-level off-chip current is downconverted 1000 times to relax these unwanted impacts. Capacitors C0 and C1 serve for frequency compensation and bandwidth limitation purposes in the circuit.
The auxiliary N- and P-type opamps are shown in Figure 6(a) and (b). In the circuit, M0, M1, M3, and M4 consist of a differential input stage. M0 and M1 are biased in their subthreshold regions for the purpose of noise reduction; meanwhile, they are chosen as large dimensions to improve the matching and reduce the offset and flicker noise. Transistors M5 and M6 consist of a transconductance output stage that provides current for the following circuits. Capacitors Cn and Cp represent the load capacitances of the opamp.
As shown in Figure 5, when a positive input is applied, the gain is provided by the regulated current mirror consisting of M0, M1, and opamp AP0, whereas M3−M5 and opamp AP1 are serving as current sources providing the quiescent current for the stage, which can be simplified to the circuit shown in Figure 7(a). A complementary discussion of the negative input case leads to the topology shown in Figure 7(b).
3.2. Small signal AC analysis
The small-signal equivalent circuit for ac analysis is shown in Figure 7(c). In this circuit, gm, gmb, go, and Cgs are the gate transconductance, body transconductance, output conductance, and gate capacitance of the MOSFET, and goa, Cia, and Coa are the output conductance, input capacitance, and output capacitance of the opamp, respectively. Ci is defined as Cgs0 + Cgs1 + C0 (or C1). The transconductance of the opamp is modeled as gma(s), considering the delays introduced by the parasitic capacitances of its internal nodes. As suggested in (Linares-Barranco et al., 1992), gma(s) can be written as
where gma is the DC transconductance, and ωa models the delay.
Detailed analysis of the equivalent circuit results in the characterization function of as2+bs+c=0, where:
and the parameters are defined as follows:
Cia:Input capacitance of opamp.
Coa:Output capacitance of opamp (Cn or Cp).
Ci:Cgs0+Cgs1+C0 (or C1).
gm:Transconductance of MOSFET.
gmb:Body transconductance of MOSFET.
go:Output conductance of MOSFET.
goa:Output conductance of opamp.
To maintain the ac stability, all the poles of the circuit transfer function must be placed in the left-hand side of the Laplace plane, i.e. a>0, b>0, c>0 must be satisfied, resulting in the conditions of gN ma, gP ma> gm1, C0> gP ma/ωa, and C1> gN ma/ωa. Moreover, it can be found that provided the quiescent current Iref, by adjusting C0 and C1, the bandwidth of the ULCA can be confined at the expected value.
3.3 Noise characterization
It is known that three kinds of noises are considered in the CMOS circuit: thermal noise and shot noise, which are white noise, and flicker noise or 1/f noise. According to the noise theory and the characterizations in (Linares-Barranco et al., 2003) and (Linares-Barranco et al., 2004), the subthreshold noises in the MOSFET are basically contributed by shot noise and flicker noise, and the noise power density SID is given by
where ID is the drain–source current of the MOSFET, W and L are the channel width and length, Cox is the gate capacitance per unit area, and q, f, and K represent the unit charge, frequency, and a process-dependent parameter, respectively. In the 0.18-µm technology, the typical value of Cox is about 1.08 × 10−2 F/m2, and K is 2 × 10−24 F2/m2 for nMOS and 4 × 10−26 F2/m2 for pMOS.
By equaling the two terms in (8), one can derive the noise corner frequency as fc = KID/2qWLC2 ox. In a W = 10 µm and L = 1 µm sized nMOS, fc is around 8 Hz when biased at ID = 1.5 nA, which is no more than 0.1% of the required 10-kHz bandwidth, whereas for pMOS, fc is two orders lower. In the DNA biosensor, the modulation signal is usually band limited with a typical bandwidth of 10 kHz and a lower frequency of 10 Hz; therefore, shot noise dominates over the whole signal band of interest from the above design.
The noise performance of the ULCA can be characterized by two noise sources vn and in with the corresponding power densities of Svn and Sin, which can be calculated as usual by evaluating the output noise current with the input open or shorted to the ground and dividing by the gain. The simplified expressions are reported as
where A is the current gain of the ULCA, and Sva is the input referred noise power density of the opamp. From (9) and (10), Sin and Svn can be reduced by decreasing the input-referred noise of the opamp and the quiescent current Iref, however trading with the power consumption and the bandwidth of the ULCA.
3.4. Mismatch considerations
The performances of the practical circuit also suffer from process fluctuations due to transistor mismatches, e.g., variations of W, L, and threshold voltage VT, which would induce the input-referred offset (IRO) Ioff, gain error δA, and bandwidth variation δBW of the ULCA. More specifically, one can find that Ioff is due to the IROs Voff of opamps AN0 and AP0 and the mismatches of M0, M1, M3, and M4; δA is caused by mismatches of M0, M1, M3, and M4; whereas δBW is mainly induced by Voff of opamps AN1 and AP1. It is known that the variances of W, L, and VT due to process fluctuations are inversely proportional to the area of the MOSFET; therefore, as a first-order approximation, Ioff, δA, and δBW are inversely proportional to √WL, which can be reduced by increasing the sizes of M0, M1, M3, and M4 and the input differential pairs of opamps in the ULCA, provided that the bandwidth specification is satisfied.
Incorporating the above considerations on stability, noise, and mismatch, HSPICE simulations are made on the circuit to meet the circuit specification in Table 3, and the optimized quiescent current is designed as Iref = 1.5 nA, whereas capacitors C0 and C1 are set to 1 pF. Monte Carlo simulation based on the design kit of SMIC 0.18-µm CMOS technology also shows that Ioff and BW are within −30~120 pA and 12~16 kHz, whereas δA/A is less than ±5%, when the channel length is chosen as L = 1 µm, and the aspect ratios (W/L) of N and P transistor units are 10 and 20, respectively.
3.5. Experiment and discussions
The ULCA is realized in the SMIC 0.18-µm CMOS mixed-signal technology, and Figure 8 shows the die micrograph of the chip. The box encloses the ULCA circuitry, which occupies about 230 × 80 µm2 of the chip area. The performance of the ULCA is measured in terms of gain, bandwidth, noise, offset, etc. The results are shown and discussed in this section.
To test the performance of the ULCA, very large resistors (from 1 to 10 GΩ) are used to convert the voltage into input currents down to the picoampere or sub-nanoampere range, which may further keep the input noise current small since the input noise current spectrum density due to the resistor is inversely proportional to the resistance. The whole circuit is placed in an aluminum box with Bayonet Neill-Concelman (BNC) connectors to shield from unwanted interferences. In the experiment, VREF is biased at 0.9 V to provide maximized input range on both positive and negative directions while satisfying the voltage range specifications in Table 3. The input voltage varies between 1.9 and −0.1 V to provide the positive and negative input currents by replacing the resistors.
The DC gain as a function of input currents ranging from −1 to 1 µA is plotted in Figure 9, which is 0.5% lower than the designed value of 20 dB and implies about 2% of the overall mismatch on transistors M0, M1, M3, and M4 due to fabrication variations. The gain error over the input range is less than 0.3%. One can certainly increase the transistor dimensions to further reduce the mismatch and achieve better linearity, however trading with the bandwidth performance.
The bandwidth has been characterized by analyzing the step response of the ULCA, which is cascaded by a commercial transimpedance amplifier, and the result as a function of input currents is also illustrated in Figure 9. It can be seen that the bandwidth basically linearly increases with the input current levels on both positive and negative directions from around 20 kHz to 1 MHz. The minimal bandwidth of 15 kHz occurs in the low-input cases, satisfying the 10 kHz requirement in the application. The overshoot of the bandwidth is because the offset of opamps AN1 and AP1 and the threshold mismatch shift the actual quiescent current of M0 and M3 up to around 2 nA (estimated value) from the designed value of 1.5 nA. A larger bandwidth may slightly degrade the noise performance and sensitivity, but it could be adjusted by somewhat tuning the biasing current Iref down for compensation.
The IRO is analyzed by keeping the input open while measuring the mean current at the output and dividing by the gain, which is found to be 96.6 pA at VOUT = 0.9 V. The IRO corresponds to the offsets of opamps and mismatches at the output node; however, it is not critical for the application. One can either slightly modify VOUT for compensation or do the calibration after acquisition and analog-to-digital conversion in the digital domain by a simple subtraction.
The noise performance of the ULCA is characterized in terms of the input-referred noise current (IRNC) by measuring the mean-square-root value of the output current fluctuation at each input current level and dividing by the gain. The result is shown in Figure 10. It is noticed that the IRNC of the ULCA starts at 37.6 pArms at zero input and basically remains at the same level for |Iin| < 1 nA, whereas it linearly increases for larger input levels. The target current sensitivity of ~100 pA is satisfied. The signal-to-noise ratio (SNR) increases for |Iin| < 10 nA and gradually saturates at values around 36 dB for larger input levels. The SNR is smaller on the positive input side than on the negative side; this is due to the fact that nMOS exhibits a higher current noise than pMOS. It is worth mentioning that the minimal noise current is larger than the simulated value of 12 pArms but falls in the range provided by Monte Carlo simulation by utilizing parameters from the foundry, which can be explained from two aspects: 1) the actual quiescent current of M0 andM3 is slightly larger than the designed value due to offsets of the opamp; and 2) the mismatches of M0, M1, M3, and M4 degrade the symmetry of the ULCA topology, thus increasing the noise level.
Linearity is presented by the gain versus input characteristic in Figure 11. The gain approximately remains at 19.9 dB for the input range of −100 to 100 µA and degrades for larger input levels. The maximal input current is estimated to about ±0.4 mA as determined by the 1-dB (or 10% in the linear scale) degrading point of gain, which implies 141 dB of headroom-to-noise ratio or equivalent to 23 bit. Moreover, depending on the electric properties of the DNA sensor and the buffer solution, the minimal impedance from the biosensor electrode is around 5 MΩ. The input impedance of the ULCA is measured as 15.5 kΩ, which is much lower than the biosensor impedance in the application, satisfying the interface condition.
|DC gain||19.9 dB|
|3-dB bandwidth||15 kHz|
|Current sensitivity||37.6 pArms|
|Potential variation||583 nVrms|
|Input-referred offset||96.6 pA|
|Input impedance||15.5 kΩ|
|Max. input current||±0.4 mA|
|Input dynamic range||141 dB|
|DC power consumption||35 µW|
|Power supply||1.8 V|
A novel subthreshold Class AB ULCA aiming at the application of signal preamplification in the IBS has been demonstrated in SMIC 0.18-µm CMOS technology. Experimental results show that the ULCA completely accommodates the application and can provide a current gain of 19.9 dB, 3-dB bandwidth of 15 kHz, and an input range of −0.4 to 0.4 mA, whereas the IRO and the noise current are less than 96.6 pA and 37.6 pArms, respectively. Table 4 shows the summarized parameters of the circuit. The ULCA can also be used for ultralow current amplification in other types of biosensor interfaces, nanoscale device sensing, and optical sensing in the future.
4.1. A few trade-offs
In order to accurately acquire signals during the sensing process, CMOS IBS has to work on a stable electrolyte potential, which is precisely controlled by the potentiostat through the reference and counter electrodes from a negative feedback mechanism. The potential variation is mainly due to the offset and noise of the potentiostat OTA. Offset can be reduced by increasing the size of input differential pair of the OTA, or introducing a digital correction circuit via a D/A converter and logics, but trades with the circuit area. On the other hand, noise can be reduced by either increasing the size or biasing current of input differential pair, but trades with the area and power, respectively.
The sensitivity of CMOS IBS is mainly governed by the acquisition circuits, which translates to the IRNC of ULCA. One can reduce IRNC by reducing the DC quiescent current, but trading with the bandwidth required in the biosensing. In some biosening systems with low electrolyte impedance, noise voltage (potential variation on the working electrode) of ULCA also becomes a concern, which also trades with the power and area of the circuit.
In general, interfacing circuits is the bottle neck of the CMOS IBS design. A good design comes with various requirements of a specific biosensing system, which differs from one system to another. Various trade-offs must be considered in the circuit design according to the system specifications as well as power and area budgets.
4.2. Future research
Future research of CMOS IBS covers a number of directions to further improve the efficiency and performance of the system. One of the methods is to incorporate a preamplification step such as polymerase chain reaction (PCR) or rolling circle amplification (RCA) before the electrical sensing, which increases the analyte concentration in the electrolyte and biosensing current level, thus relaxing the sensitivity requirements of the interfacing circuit. Keeping the same sensitivity, one can further shrink the dimension of electrodes and increase the scale of IBS to improve the throughput and sensing efficiency.
As the scale of IBS growing up, asymmetry due to the electrode layout also becomes an issue, because the current density distributes from the counter electrode to all the working electrodes in the electrolyte, which could be quite different from each other depending on the positions. Some structures such as multiple counter electrodes, interlacing electrodes, partition, etc are being investigated. Further research also needs to be invested to characterize the current distribution in the electrolyte for a specific electrode layout when the number of electrode scales up.
From the circuit angle, the sensitivity can be further improved by using the lock-in filtering, which extracts the current only at the vicinity of frequency-of-interest therefore minimizing the background noise contributions and maximizing the signal-to-noise ratio. The challenge part is that a high resolution A/D conversion is required to translate current signals into digital domain before the digital lock-in filtering. Logarithmic transimpedance amplification is another candidate to achieve high sensitivity and satisfying the bandwidth requirements, while ameliorating the dynamic range limitations by compressing output voltage range. The signal decompress can be realized by digital circuits after the voltage digitization.
The CMOS IBS research and production continue to offer a fertile ground for innovation. In this chapter, design considerations on the CMOS IBS interfacing circuits, including the integrated biosensor array, potentiostat, and acquisition circuits, have been introduced. A number of circuit design trade-offs between potential variation, sensitivity, speed, dynamic range, power, and physical area have also been discussed. Finally, future research directions to further improve the IBS performances in terms of efficiency and sensitivity are reviewed.
This work was supported by the National Science Foundation of China under Grant 60236020 and Grant 90307016, by a grant from Intel, and by a private research grant from Dr. D. Yang.
The authors would like to thank Prof. Y. Chen of the Mechanical and Aerospace Engineering Department, University of California, Los Angeles, for the collaboration with his research team.