Open access peer-reviewed chapter

Analysis and Control of Power Electronic Converters Based on a System Zero Locations Approach

By Jorge-Humberto Urrea-Quintero, Nicolás Muñoz-Galeano and Lina-María Gómez-Echavarría

Submitted: March 20th 2018Reviewed: July 20th 2018Published: November 5th 2018

DOI: 10.5772/intechopen.80426

Downloaded: 225

Abstract

This chapter presents a procedure to design and control power electronic converters (PECs), which includes a zero-based analysis as a dynamical system response criterion for dimensioning converter passive elements. For this purpose, a nonideal boost DC-DC converter (converter considering its parasitic losses) is dynamically modeled and analyzed in steady state as an application example. The steady-state model is obtained from the average nonlinear model. The steady-state model allows deducing expressions for equilibrium conversion ratio M D and efficiency η of the system. Conditions for the converter conduction modes are analyzed. Simulations are made to see how parasitic losses affect both M D and η . Then, inductor current and capacitor voltage ripple analyses are carried out to find lower boundaries for inductor and capacitor values. The values of the boost DC-DC converter passive elements are selected taking into account both steady-state and zero-based analyses. A nonideal boost DC-DC converter and a PI-based current mode control (CMC) structure are designed to validate the proposed procedure. Finally, the boost DC-DC converter is implemented in PSIM and system operating requirements are satisfactorily verified.

Keywords

  • power electronic converters
  • boost DC-DC converter
  • zero-based analysis
  • current mode control
  • parasitic loss analysis
  • efficiency

1. Introduction

Design procedures of PECs must establish a trade-off between passive elements’ values and dynamical performance because of the close dependence between them. Dynamical performance should not be deteriorated and operating requirements must be satisfied [1]. This task generally implies the construction of a nonlinear dynamical model and its implementation in any computational tool [2].

Dynamical modeling and steady-state analyses of PECs have received significant attention as tools to model system design [3]. Through dynamical modeling, it is possible to perform an analysis of the system behavior and its relation with passive elements’ values [1]. Meanwhile, steady-state analysis provides expressions to determine in PEC: (a) MD, (b) η, and (c) continuous conduction mode (CCM) and discontinuous conduction mode (DCM) boundaries [3].

Multi-resolution PEC models can be constructed where parasitic losses can be taken into account [4]. However, if parasitic losses are not considered, the PEC model is simplified; but models do not adequately represent the PEC behavior in its entire operation range [5]. Moreover, a simplified model cannot predict both MDand ηnonlinearities and limitations [6].

Parasitic losses are typically modeled as appropriate equivalent series resistances (ESRs) associated with passive elements of PECs [3, 7, 8]. Parasitic losses can be included in the PEC design stage when both dynamical performance and ηare taken into account [6]. Several works, [4, 7] to mention some of them, propose different PEC modeling approaches that have included parasitic losses. Nevertheless, in the reviewed literature, a consensus about what is the suitable detailed level of the model does not exist, in which PEC’s dynamical behavior can be accurately represented; without the model, deduction becomes a challenge for the designer. However, the trend remains with the so-called average models which describe low-frequency and neglect high-frequency dynamics (semiconductor switching dynamics) of the system [9].

Average models that take, some or all, parasitic losses into account, have been presented by [1, 10]. Recent works [7, 10, 11, 12, 13, 14] show that a practical level of model detail for PECs includes parasitic losses associated with their passive elements and disregards losses due to semiconductor switching. Models with this level of detail are suitable for system design, MDderivation, ηanalysis, and dynamical performance evaluation [12]. Additionally, these models are suitable for control purposes [2, 10].

It is clear that based on average models, PECs can be designed to carry out dynamical performance analysis. Notwithstanding, a design procedure is needed that comprises all necessary steps to design and control PECs and fulfills all given operating requirements. This design procedure must be simple and useful.

In the PEC field, few works that take into account dynamical characteristics of the system have been carried out [15, 16, 17]. In these works, PEC’s design problem is presented as an optimization problem. In consequence, a procedure to easily design and control PECs is still needed. In this chapter, a procedure to easily design and control PECs is introduced. In this procedure, neither an optimization process is carried out nor is the control structure fixed. But, zeros’ location impact over the system dynamical responses is analyzed, showing that a careful selection of the PEC passive elements could both avoid electronic device failures due to large overshoots and improve the dynamical system performance.

The structure of the chapter is organized as follows: in Section 2, both time- and frequency-domain models of the boost DC-DC converter are derived. In Section 3, the boost DC-DC converter is studied in steady state. Section 3 is composed of Sections 3.1, 3.2, 3.3, and 3.4. In Sections 3.1 and 3.2, expressions for MDand ηare derived including some parasitic losses. In Section 3.3, conditions to operate in CCM or DCM are found. In Section 3.4, both inductor current and capacitor voltage ripple analyses are carried out to find lower boundaries for inductor and capacitor values that fulfill ripple requirements. In Section 4, the value of the passive elements is selected such that operating requirements are fulfilled and system dynamical performance is achieved. Mathematical model is contrasted with a PSIM implementation of the boost DC-DC converter. In Section 5, the widely accepted current mode control (CMC) structure for boost DC-DC converters is designed.

2. Nonlinear dynamical modeling

Figure 1 shows a circuital representation of a typical boost DC-DC converter including its parasitic losses associated to the passive elements. The boost DC-DC converter supplies energy to a dominant-current load represented as a Norton equivalent model. Engines and inverters are common dominant-current loads that can be supplied by a boost DC-DC converter. In Figure 1, Lis inductor, Cis capacitor, and RLand RCare the parasitic losses for Land C, respectively. RLand RCrepresent all parasitic losses.

Figure 1.

Circuital scheme of the DC-DC boost converter: configuration (a) h 1 = 1 , h 2 = 0 . Configuration (b) h 1 = 0 , h 2 = 1 .

The boost DC-DC converter operating in CCM can take two configurations according to the switch position as shown in Figure 1. First (Figure 1(a)) and second (Figure 1(b)) configurations correspond to switch H=h1h2being turned on h1=1, h2=0and turned off h1=0, h2=1, respectively. Therefore, the switching function ucan be defined as follows: u=h1or u=1h2.

State variables are inductor current iLand capacitor voltage vCwhich represent the energy variation in the system. The system inputs are u, DC input voltage source vg, and current source io. Variations of ioare useful to represent system current perturbations. The system outputs are output voltage voand iL. The corresponding dynamical model of the system in Figure 1 is given by Eqs. (1) (2), where αC=RC/Rand ϕC=RC/1+αC.

LdiLdt=vgRL+ϕC1u2iL+ϕCR11uvC+ϕC1uioE1
CdvCdt=11+αC1uiLvCRioE2

In this chapter, the widely accepted PI-based CMC structure for the boost DC-DC converter is adopted [15, 16]. PI controllers’ tuning requires a frequency-domain model. From Eqs. (1) and (2), it is possible to obtain a linear state-space model of the boost DC-DC converter. Next, the frequency-domain model is obtained by means of the realization given by Eq. (3).

Gs=1detsIACadjsIATB+DE3

The linear state-space model for the boost DC-DC converter is given by Eqs. (4) and (5), where x=iLvCT, u=dvgioT, and y=iLvoT. ILand VC, Dand Ioare states and inputs in their rated values, respectively. d=uo(average value of u) is the duty ratio, a continuous variable, and d01. In this chapter, dis used as the input control, while Dis din the operation point.

ẋ=Ax+BuE4
y=Cx+DuE5

where,

A=RL+ϕC1D2LϕCR11DL1D1+αCC1RC1+αCE6
B=2ϕCIL1DVCϕCR1ϕCIoL1LϕC1DLIL1+αCC011+αCCE7
C=10ϕC1D1ϕCRE8
D=000ϕCIL0ϕCE9

The transfer functions given by Eqs. (10)(15) are obtained by applying the realization given by Eq. (3), where GiLds=ILs/Ds, GiLvgs=ILs/Vgs, GiLi0s=ILs/I0s, Gvods=Vos/Ds, Gvovgs=Vos/Vgs, and Gvoi0s=Vos/I0s.

GiLd=1R(RC1+αC2RϕCIL1DVCϕCRRϕCIos+ϕC+R1DRILVCϕCRRϕCIo)RLC1+αCs2+L+RCRL+ϕC1+αC1D2s+RL+R1D2E10
GiLvg=RC1+αCs+1RLC1+αCs2+L+RCRL+ϕC1+αC1D2s++RL+R1D2E11
GiLi0=ϕCRC1D1+αCs+R1DRLC1+αCs2+L+RCRL+ϕC1+αC1D2s++RL+R1D2E12
Gvod=CϕC1D1+αC2RϕCIL1DVCϕCRRϕCIo+LILϕCRsILϕCR1D22ϕC+RL+1D2RϕCIL1DVCϕCRRϕCIoRLC1+αCs2+L+RCRL+ϕC1+αC1D2s+RL+R1D2E13
Gvovg=RϕCC1+αCs+11DRLC1+αCs2+L+RCRL+ϕC1+αC1D2s+RL+R1D2E14
Gvoi0=RϕC1D2ϕC1DRLϕCC1+αCs+1RLC1+αCs2+L+RCRL+ϕC1+αC1D2s+RL+R1D2E15

Once the current control loop in the CMC structure is closed, the equivalent simplified representation of the boost DC-DC converter shown in Figure 2 is obtained. Large- and small-signal models of the simplified boost DC-DC converter are given by Eqs. (16) and (17), respectively. The transfer functions of the simplified model are given by Eq. (18). The numerator of Eq. (18) has two components, one for each system input, i.e., iREFand io, respectively. In the CMC structure, Eq. (18) is employed to tune the PI controller in the outer control loop, which regulates vo.

CdvCdt=11+αCiLREF1DvCRioE16
vC.=11+αC1RCvC+11+αC1DC11+αC1CiLREFiovo=11+αCvC+11+αCRC1D11+αCRCiLREFioE17
Gvos=1+αCRCRCs+R+RC1D1+αCRCRCs+R+RC1+αC1+αCRCs+1E18

Figure 2.

Equivalent simplified representation of the boost DC-DC converter.

3. Steady-state analysis

Once the system model is obtained, the following analysis might be carried out: (1) derivation of the MDexpression, (2) losses effect and efficiency expression derivation, (3) condition analyses of CCM and DCM, and (4) inductor current ΔiLand capacitor voltage ΔvCripple analysis. The aim of these analyses is to determine suitable passive elements’ (Land C) boundaries which satisfy the design requirements.

3.1. First step: derivation of the equilibrium conversion ratio M(D) expression

Steady-state model allows to derive expressions for average rated values for both vCand iLas functions of the system inputs and parameters. The steady-state model is obtained by setting the model given by Eqs. (1) and (2) to zero. Thus, Eqs. (19) and (20) are obtained.

IL=VCR1DE19
Vg=RL+R1D2R1DVoE20

From Eqs. (1) and (2), it is found that Vo=VCin steady state. The expression of MDfor the boost DC-DC converter is conveniently written using Eq. (21), where αL=RL/R. MDindicates the conversion gain factor in voltage in terms of D, R, and RL.

MD=VoVg=1DαL+1D2E21

Note that MDdoes not depend on RCdue to the fact that the capacitor current in the average model is zero, leading to no voltage drop in RC.

It is important to remark that if RL=0in Eq. (21), this expression is in agreement with the ideal boost DC-DC MD, i.e., MD=1/1D. However, the converter reaches an efficiency equal to 100%if RL=0. Additionally, MDtends to when Dtends to 1. The above consideration is not true in a real boost DC-DC converter application and, for this reason, an analysis without including parasitic losses is not convenient.

3.2. Second step: losses effect and efficiency expression derivation

This section shows how parasitic losses affect ηin the boost DC-DC converter case. Losses effect and efficiency analyses are carried out in order to find suitable values for RLand RCsuch that the designed PEC fulfills the operating requirements.

The DC transformer correctly represents the relations between DC voltages and currents of the converter. The resulting model can be directly solved to find voltages, currents, losses, and efficiency in the boost DC-DC converter [20].

Eqs. (22) and (23) are obtained from Eqs. (1) and (2). These equations establish that the average value of both iLand vCare equal to zero in steady state. Figure 3 is the representation of Eqs. (22) and (23) as a DC transformer model.

0=VgRL+ϕC1D2IL11+αCVC1DVdE22
0=VC1+αCR+11+αCIL1DIdE23

Figure 3.

DC transformer model of the boost DC-DC converter.

The equivalent circuit model in Figure 3 allows to compute the converter efficiency η. From Figure 3, it is possible to deduce the efficiency expression given by Eq. (24).

η=1D21+αCαL+1D2E24

Simulations of Eqs. (21) and (24) are shown in Figure 4 for several values of αCand αLratios in order to test how much losses affect both MDand η.

Figure 4.

(a) Conversion ratio M D vs. duty cycle D . (b) Efficiency η vs. duty cycle D .

Figure 4(a) and (b) is shown together to relate MDand η. Two different values of Dcan be selected to reach the same value of MD. Nevertheless, higher values of Dlead to lower efficiency values. For this reason, it is recommended that the converter operates at low values of Das possible.

Figure 4(a) shows how the αLratio affects MD: αL=0is the ideal case for the boost DC-DC converter (without losses) and MDin the converter has an increasing trend and eventually tends to infinity. When αLincreases (real case, converter with losses), MDdecreases and the curve has a quadratic trend. It can be observed that the higher αLvalue matches to the lower converter conversion ratio MD.

From Figure 4(b), it is observed that the maximum ηvalue reached by the converter is determined by losses and it is given in D=0for every MDcurve. For the studied case, it is the combination of αCand αLthat determines the maximum value of η, which decreases while Dincreases, dropping to 0when Dtends to 1. Hence, the converter should operate as far as possible with low Dvalues. Additionally, an increase of either αCor αLcauses a decrease in η. Therefore, αCand αLshould tend to zero to guarantee high converter efficiency. Values of αCand αLwere clustered in groups of curves. For αL=0and αC=00.050.1(above lines group), it is noted that while αCincreases, ηslightly decreases. For curves group αL=0.05and αC=00.050.1(middle lines group) and for curves group αL=0.1and αC=00.050.1(below lines group), something similar occurs—ηdecreases while αCincreases. However, decreases in ηare more notable when αLincreases than when αCincreases. The combined effect of high αLand αCleads to a highly inefficient system with high losses.

3.3. Third step: conditions for the converter conduction model

The CCM is suggested since DCM causes a larger voltage ripple in the boost DC-DC converter case [18, 19]. In consequence, the peak inductor current in DCM is higher than in CCM [22]. By [20], the condition for operating in the CCM is IL>ΔiLand the condition for operating in the DCM is IL<ΔiL. The DCM condition for the boost DC-DC converter is given by Eq. (25), where Ts=1/fswand fswis the converter switching frequency.

Figure 5.

K D , K , and conduction mode (CM) conditions.

D1D2>2LRTsE25

The left side of Eq. (25) is a function that only depends on D. Here, this function is named as KD=D1D2. The right side of Eq. (25) is a dimensionless function that depends on L, R, and Ts, which is named in this chapter as K=2L/RTs. If Land Rare taken as the converter parameters and fswis fixed, Kis a constant and represents the converter measure to operate in CCM and DCM [20]. Large values of Klead to CCM. Small values of Klead to the DCM for some values of D. KDis a function that represents the boundary between DCM and CCM. Then, the minimum value of Kmust be at least equal to the maximum value of KD, i.e., maxKDminK, if it is desired that the converter always operates in CCM, see Figure 5. Therefore, if values for Rand Tsare given in the system specifications, a condition for the minimum possible value of Lthat assures CCM operation is given by Eq. (26), with maxKD=0.148, that is equal to the critical value of KKc.

L>0.148RTs2E26

3.4. Fourth step: inductor current and capacitor voltage ripple analysis

ΔiLand ΔvCanalyses are carried out to determine constraint equations for a suitable choice of both Land Cvalues. The carried out analysis in this section is suitable for the boost DC-DC converter operating in CCM. Figure 6 shows both typical inductor voltage vLand inductor current iLlinear-ripple approximations. The slope with iLincreasing or decreasing is deduced from the analysis of VLat each subinterval of time taken into account. Typical values of current inductor ripple ΔiLlie under 10% of the full-load value of IL[20]. From Figure 6, it is seen that iLbegins at the initial value of iL0. After time proceeds, iLincreases during the first subinterval (DTs) and decreases during the second subinterval (1DTs), both with a constant slope. Then, the switch changes back to its initial position at time t=Tsand the process repeats.

Figure 6.

(a) Typical inductor voltage linear-ripple approximation. (b) Typical current inductor linear-ripple approximation.

As illustrated in Figure 6(b), both current ripple and inductor magnitudes are related through the slope of iL. The peak inductor current Ipkis equal to ILplus the peak-to-average ripple ΔiL. Ipkflows through inductor and semiconductor devices that comprise the switch. The knowledge of Ipkis necessary when specifying the rating of the device. The ripple magnitude can be calculated through the knowledge of both the slope of iLand the length of the first subinterval (DTs). The iLlinear-ripple approximation is symmetrical to IL; hence during the first time subinterval, iLincreases by 2ΔiL(since ΔiLis the peak ripple, the peak-to-peak ripple is 2ΔiL). In consequence, the inductor value Lcan be chosen from Eq. (27).

L=VgαL1DVo2ΔiLDTsE27

Eq. (27) is a lower boundary for the Lvalue, where Lcan be chosen such that a maximum ΔiLis attained for the boost DC-DC operating condition.

Likewise, vClinear-ripple approximation is depicted in Figure 7(b), where a relation between the voltage ripple and the capacitor magnitude is observed. It is seen that vCbegins at the initial value of vC0. After time proceeds, vCdecreases during the first subinterval (DTs) and increases during the second subinterval (1DTs), both with a constant slope. Then, switch changes back to its initial position at time t=Tsand the process repeats itself. The ripple magnitude can be calculated through the knowledge of both the slope of vCand the length of DTs. The change in vC, 2ΔvCduring DTs, is equal to the slope multiplied by DTs. In consequence, Eq. (28) can be used to select the capacitor value of Cto obtain a given ΔvC. Eq. (28) is a lower boundary for Cvalue, where Ccan be chosen such that a maximum ΔvCis attained for the worst boost DC-DC operating condition.

Figure 7.

(a) Typical capacitor current linear-ripple approximation. (b) Typical capacitor voltage linear-ripple approximation.

C=Vo2RΔvCDTsE28

4. Passive elements’ value determination

In this section, the boost DC-DC converter operating requirements are specified. Then, the values of the passive elements are determined such that operating requirements are fulfilled and system dynamical performance is achieved. Finally, the mathematical model is contrasted with a PSIM implementation of the boost DC-DC converter.

4.1. System operating requirements

In the boost DC-DC converter application, typical requirements are: input voltage range, output voltage range, output power range, output current range, operating frequency, output ripple, and efficiency. Unless otherwise noted, the continuous operating mode is assumed. The set of operating requirements for the boost DC-DC converter are specified in Table 1.

RequirementsValues
MinTypMax
Input voltage range30 V35 V40 V
Output voltage range50V70 V95 V
Output power range0 W100 W300 W
Output current range0A2A8A (At 50 V)
Operating frequency100KHz
Output current ripple1%5%10%
Output voltage ripple0.1%0.5%1%
Steady-state efficiency90%95%98%
Load25 Ω50 Ω100 Ω

Table 1.

Boost DC-DC converter operating requirements.

4.2. Zeros’ location analysis

The values of the passive elements are selected to fulfill the operating requirements. The main interest is to choose suitable values for inductors and capacitors such that constraints like maximum physical admissible currents and voltages, converter efficiency, and converter CM are satisfied by keeping an acceptable dynamical system performance.

Expressions given by Eqs. (27) and (28) were deduced via steady-state analysis for lower inductor Land capacitor Cboundaries, respectively. These expressions are suitable to choose Land Cvalues as functions of ΔiL, Δvc, states, and inputs in their steady-state value. Additionally, the expression given by Eq. (26) was deduced from the converter CM analysis, which allows to guarantee the boost DC-DC converter CCM operation in all the operating ranges by choosing suitable Land Rvalues.

In PECs, it is desired that ΔiLmaxΔiLand ΔvomaxΔvoshould be assured in the entire operation range. Then, based on the worst condition for ΔiLand Δvo, Land Clower boundaries can be deduced such that ripple constraints are satisfied. Eqs. (29) and (30) give lower boundaries for Land C, respectively.

LmaxVgRLmaxR1DminVo2maxΔiLDTsE29
CmaxVo2minRmaxΔvoDTsE30

Eq. (26) also gives a minimum boundary for Lvalue. Then, Eqs. (26) and (29) must be evaluated and the maximum Lvalue must be selected as the lower boundary.

Eqs. (29) and (26) depend on RCand RLthrough αCand MD, respectively. However, from the steady-state analysis, instead of calculating RCand RLvalues, it is suitable to establish αCand αLvalues. αCand αLvalues can be chosen such that the system efficiency is η90%in the entire operating range.

The maximum boost DC-DC conversion condition corresponds to maxMD. Then, maxMD=maxVo/minVg. According to the operating requirements in Table 1, minVg=30Vand maxVo=95V, thus the maximum conversion condition in the example here presented is maxMD3.17. In consequence, loss ratios must be αC<0.05and αL<0.05when R=maxR=100Ω.

Figure 8 shows MDand ηcurves for RL=150mΩ, RC=70mΩ, and R=25Ω, i.e., αL=0.006and αC=0.0034. With these αLand αCvalues, it is assured that η90%and MD3.17. Two points are remarked over both MDand ηcurves for the rated converter conversion condition MD=2and MD3.17. From Figure 8(a), it is seen that the converter has sufficient boost capacity to guarantee that for MD3.17, the voltage requirement is satisfied. Additionally, from Figure 8(b), it is seen that for MD=2and MD3.17, the converter has 97and 93%of efficiency, respectively.

Figure 8.

(a) Conversion ratio M D . (b) Efficiency η .

From Eq. (29), maxIL=maxVC/minR1D. Then, on the one hand, if maxΔiL=0.1maxIL, L326.34μHmust be selected according to Eq. (29) in order to keep the converter in safe operation [22]. On the other hand, L40μHto always operate in CCM by evaluating Eq. (26). The iLripple-based condition is a less restrictive boundary for Lthan the CCM-based condition. Therefore, L326.34μHis the lower boundary for this element.

If maxΔvC=0.01maxVoin order to keep a converter in safe operation [22], C14.120μFaccording to Eq. (30).

Minimum Land Cvalues are selected as system parameters. Next, a simulation of the designed boost DC-DC converter is carried out. Figure 9 shows the step system response for Vg=35V, Vo=70V, Io=0A, L=326.34μH, C=14.120μF, R=50Ω, αC=0.0034, αL=0.006, and fsw=100kHz.

Figure 9.

(a) G i L d step system response. (b) G vd step system response.

From Figure 9, it is seen that, with minimum values of Land C, voltage overshoot is O.S.Gvd=57.4718%, current overshoot is O.S.GiLd=187.2323%, and system setting time is ts=3.03ms. From Figure 9(a), it is seen that the peak current value is 33.1686A, while the steady-state current value is around 11.5477A. From Figure 9(b), it is seen that the peak voltage value is 214.5027V, while the steady-state voltage value is around 136.2166V.

A designed system with these overshoots needs to oversize its electronic devices such that these devices support both peak voltage and current values without system damage. However, such electronic devices can be expensive and inconvenient. For instance, in this chapter, an analysis of the boost DC-DC converter dynamical characteristics is carried out. This dynamical analysis studies the impact of Land Cvalues over the zeros in transfer functions given by Eqs. (10) and (13), which determine overshoots and system setting time.

In a system as it is known, dynamical response is determined by poles and zeros’ location [23]. Zeros are determined by the selected inputs and outputs of the system. Zeros’ location is related to some system performance restrictions such as tracking limitations in feedback systems when classical control structures are employed [21, 22]. Moreover, large current or voltage overshoots in converter transient response can cause converter failures. PEC design process could take into account zeros’ location due to Land Cvalues such that the right half-plane (RHP) zeros are avoided or their impacts are attenuated. In consequence, the impact of Land Cvalues over the zeros is analyzed to establish a trade-off between their values and the dynamical system response.

In the boost DC-DC converter dis chosen as control input, while vgand ioare considered disturbances. Thus, dvariations’ effect is of primary interest over system output. In consequence, duty ratio-to-voltage-output Gvdand duty-ratio-to-inductor-current GiLdtransfer functions are studied. A simulation was carried out to evaluate the effects of large values for both Land C. Figure 10 shows Gvdand GiLdovershoots and setting time for L326.34μH2000μHand C14.12μF100μF.

Figure 10.

(a) G vd step system response for varying L and C : overshoot with zeros. (b) G i L d step system response for varying L and C : overshoot with zeros. (c) Step system response varying L and C : setting time.

From Figure 10, it is seen that the minimum possible value of Ccauses maximum overshoot in vo; while a minimum possible value of Lcauses maximum overshoot in iL. Moreover, minimum Cand Lvalues give minimum system setting time.

In contrast, large values of Ccause high overshoot of iL; while large values of Lcause high system setting time. In consequence, two additional design requirements are given in order to establish maximum possible values for Land Csuch that system overshoots and setting time are suitable: (a) maximum duty-ratio-to-output-voltage overshoot maxO.S.Gvdand (b) maximum duty-ratio-to-inductor-current overshoot maxO.S.GiLd.

From Figure 10, it is seen that the system dynamical response cannot be modified if the values of both Land Care simultaneously increased. Meanwhile, if either Lor Cvalues are increased, both O.S.Gvdand O.S.GiLddecrease. Nevertheless, larger values of Lhave a major impact than larger values of C.

L=1mHand C=15μFare selected by results shown in Figure 10 since with these values O.S.GiLd105%and O.S.Gvd53%, i.e., O.S.GiLdis approximately reduced to 82%and O.S.Gvdis approximately reduced to 4%. Furthermore, ts=4.32ms, i.e., the system setting time is only increased by 1.3ms. Thus, these Land Cvalues establish a trade-off between system overshoots and performance. It is remarked that selected Land Cvalues are commercially available.

4.3. System frequency response verification

Frequency response of both the mathematical model and a PSIM circuital implementation are contrasted in order to validate the dynamical model of the designed boost DC-DC converter via simulation. The boost DC-DC converter was parameterized with L=1mH, C=15μF, Vg=35V, Vo=70V, Io=0A, αC=0.0034, αL=0.006, R=50Ω, and fsw=100kHz. In consequence, IL=2.8812Aand D=0.5141in the equilibrium point.

Figure 11 presents the boost DC-DC converter Bode diagrams of the PSIM circuital implementation and the mathematical model given by Eqs. (10)(15). The frequency response of the PSIM circuital implementation matches with the mathematical model. Then, the PSIM circuital implementation is satisfactorily reproduced by the mathematical model.

Figure 11.

(a) G i L d Bode diagram. (b) G vd Bode diagram.

5. Control structure design

Nonminimum phase behavior is a well-known result derived from the boost DC-DC converter study [24]. To avoid this system behavior, a CMC structure has been proposed [18, 24]. Nonminimum phase behavior is avoided with this control structure since both GiLdand inductor-current-to-output-voltage GvoiLREFtransfer functions have a minimum phase behavior.

The converter control design is focused on imposing a desired low-frequency behavior on the system. Here, a CMC structure for the boost DC-DC converter is designed. The aim is to tune PI controllers such that the control objective is achieved. Figure 12 shows the CMC structure for the DC-DC boost converter. As it is seen in Figure 12, the CMC structure employs two PI controllers: first one for iLcontrol and second one for voregulation. These PI controllers are arranged in master-slave form; where iLcontrol loop is the inner loop and vocontrol loop is the outer loop. This master-slave arrangement allows voregulation while preserving iLwithin specified safety limits.

Figure 12.

Boost DC-DC CMC structure scheme.

In the boost DC-DC converter which operates in a switch-mode power supply and feeds a certain variable load, the dneeds adjustments in order to ensure a constant vofor the entire operating range (voltage regulation). Besides, against any system disturbance (vgand iorandom changes), the dvalue should be adjusted to drive the system back to the operating point. The PI controller in the outer loop provides the set-point of the inner loop, which acts as the control input of the outer loop. The proportional and integral (PI) controller in the inner loop generates a continuous signal for d, which by means of a pulse width modulation (PWM) is applied to the power switching gate.

5.1. Controller tuning

Controller’s tuning task begins with the set of design specifications. The goal of the boost DC-DC converter controller is to maintain vowithin 2% of its rated value (i.e., 68.6V71.4V) in response to random changes (disturbances) in both vgand io. Also, the controller should be able to drive vowithin the tolerance for vgvariations over a range from 30to 40V.

The inner loop control bandwidth must be 20kHzor less due to the fact that fswis equal to 100kHz, and the outer loop control bandwidth must be smaller than 1/5of the inner loop control bandwidth [25], i.e., smaller than 5kHz. Additionally, a robustness index of Ms<2is desired to establish a trade-off between control performance and robustness [26].

A PI controller was tuned by acting directly on dto track the inductor current reference iLREFsince GiLdexhibits a minimum phase behavior. The inductor current PI controller was tuned by means of the root-locus technique, adopting the following design specifications: damping factor ζequal to 0.707and a 20kHzclosed-loop bandwidth. The tuned PI controller transfer function GCiLsis given by Eq. (31). These PI controller design specifications ensure: (a) Zero steady-state error and a satisfactory reference tracking for frequencies below 20kHz; this is observed on transfer function TiLiLREFin Figure 13. (b) Effective disturbance rejection for both input voltage vgand current source iovariations, which are observed on transfer functions TiLvgand TiLioin Figure 13, respectively. (c) A closed-loop robustness Ms=1.2.

GCiLs=1.27s+55218sE31

Figure 13.

Inner current control loop transfer functions.

A PI controller was tuned to regulate vosince the GvoiLREFstransfer function given by the Eq. (18) exhibits a minimum phase behavior. This PI controller provides the set-point of the inner control loop. The PI controller of the outer control loop was tuned by means of the root-locus technique considering a damping factor ζequal to 0.707and a 5kHzclosed-loop bandwidth. The tuned PI controller transfer function GCvosis given by Eq. (32). These PI controller design specifications ensure: (a) Zero steady-state error observed on transfer function TvovoREFin Figure 14. (b) Effective disturbance rejection for the current source iovariations, which are observed on transfer function Tvoioin Figure 14. (c) A closed-loop robustness Ms=1.2.

Figure 14.

Outer output voltage control loop transfer functions.

GCvos=0.07994s+235.1sE32

5.2. Closed-loop system performance verification

The designed boost DC-DC converter with its control structure was implemented in PSIM to assess the closed-loop system robustness. Three cases were proposed to evaluate the control structure robustness against most common disturbances. (i) An experiment that simulates a change of ±35%around the nominal value of the load was carried out. Next, (ii) an experiment that simulates a change of ±15%around the nominal value of the input voltage was carried out. Finally, (iii) an experiment that simulates a combined change of ±35and ±30%around the nominal values of the load and the input voltage, respectively, was carried out. Figure 15 shows the dynamical system response against the perturbations mentioned above. From Figure 15, it is seen that the system stability is not affected by any of the simulated perturbations, which means that the control structure is robust against the system perturbations from both the load and the input voltage up to 35%.

Figure 15.

Closed-loop behavior at unit steps system disturbances.

Figure 15(a) shows the closed-loop behavior at unit step changes of ioaround the operating point corresponding to the full load. Two iounit step changes were applied to evaluate the control structure performance. The first step change was applied at t=10msfor 10ms, then the current source returns to its rated value io=0A. The second unit step change was applied at t=30msfor 10ms, then the current source returns to its rated value io=0A. In Figure 15(a), a satisfactory tracking of iLREFand regulation of voto reject load disturbances depicted as changes in iois observed.

Figure 15(b) shows the closed-loop behavior at unit step changes of vg. Two vgunit step changes were applied to evaluate the control structure capabilities to regulate voand to evaluate the capabilities of the designed boost DC-DC converter. The first unit step change was applied at t=10msfor 10ms. This first unit step change was equal to vg=5V, i.e., the final value of the input voltage was vg=30Vthat corresponds with its lower boundary. The second unit step change was applied at t=30msfor 10ms. This second unit step change was equal to vg=+5V, i.e., the final value of the input voltage was vg=40Vthat corresponds to its upper boundary. In Figure 15(b) a satisfactory reference tracking of iLREFand control regulation of voto changes in vgis observed. It is important to remark that under the worst condition for vg, the boost DC-DC converter was able to keep voin its rated value.

Finally, Figure 15(c) shows the closed-loop behavior at random unit step changes of both ioand vg. These unit step changes were applied such that the designed control structure performance could be evaluated against any random disturbance. From Figure 15(c), it is possible to see that the designed control structure has a satisfactory performance against multiple disturbances within specified design requirements for the boost DC-DC converter in Table 1.

In order to carry out system operation requirements verification, case (c) of Figure 15 is taken into account. Figure 16 shows: (a) Pin, Poutand (b) iLand vo, when case (c) of Figure 15 is considered.

Figure 16.

(a) Instantaneous Power verification. (b) Ripples verification.

From Figure 16(a), it is seen that Poutdoes not exceed the maximum admissible output power in steady state and is always lower than Pin. b. Figure 16(b) shows iLand vo. A zoom was made for the worst simulated system condition. From Figure 16(b), it is seen that even in the worst iLand vocondition, ΔiLand Δvoare below 1%. Accordingly, the designed boost DC-DC converter satisfies both ΔiLand Δvoconditions.

In conclusion, Figure 16 shows that the boost DC-DC converter system operating requirements given in Table 1 are successfully satisfied.

6. Conclusions

In this chapter, a procedure to easily design and control PECs was proposed and zeros’ location impact over the system dynamical responses was analyzed, showing that a careful selection of the PEC passive elements could both avoid electronic device failure due to large overshoots and improve the dynamical system performance. Parasitic losses RLand RCwere included in order to have a more realistic approach to the system. The presented procedure was composed of:

  1. The nonlinear dynamical system modeling approach to obtain a mathematical tool and evaluate the system performance. The obtained dynamical model was suitable to describe the dynamical behavior of the system and to derive the steady-state model.

  2. The steady-state analysis that allowed to find suitable constraints for passive elements’ values. The steady-state analysis was composed of: (a) MDexpression derivation, (b) losses effect analysis and ηexpression derivation, (c) conditions for analysis of CCM and DCM, and (d) ΔiLand ΔvCanalyses.

  3. The passive elements’ value determination based on the system zeros’ location. A zero-based analysis allowed to choose the passive elements’ values such that a trade-off between operating requirements and system transient response were achieved. This analysis reduced the system outputs’ overshoot alleviating electronic devices’ stress and improving the system’s performance.

  4. The proposal of a model-based control structure; particularly, a CMC structure based on PI controllers for automatic converter control was implemented in the boost DC-DC converter, although a control structure does not need to be fixed in this procedure.

  5. The procedure was applied to a boost DC-DC converter application taking into account the parasitic losses associated with its passive elements, which allows to investigate the details of its performance, operation, and behavior. It was possible to design a boost DC-DC converter that fulfills all the operating requirements in the entire operating range, even if bounded disturbances appear. Design was based on the nonlinear dynamical model and steady-state analysis. The CMC structure was implemented for the designed boost DC-DC converter. PI controllers were tuned by means of root-locus controller design method. The boost DC-DC converter was implemented in PSIM where system operating requirements, closed-loop performance, and robustness were successfully verified.

Acknowledgments

This work was partially supported by COLCIENCIAS (Fondo Nacional de Financiamiento para la Ciencia, la Tecnología y la Innovación Francisco José de Caldas) with the doctoral scholarship 727-2015. The authors would also like to thank “estrategia sostenibilidad UdeA”.

Conflict of interest

The authors declare no conflict of interest.

Author contributions

Jorge H. Urrea-Quintero carried out most of the work presented here, Nicolás Muñoz-Galeano was the advisor of this work, and Lina M. Gómez had a relevant contribution with her extensive knowledge about systems theory.

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Jorge-Humberto Urrea-Quintero, Nicolás Muñoz-Galeano and Lina-María Gómez-Echavarría (November 5th 2018). Analysis and Control of Power Electronic Converters Based on a System Zero Locations Approach, Applied Modern Control, Le Anh Tuan, IntechOpen, DOI: 10.5772/intechopen.80426. Available from:

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