SAR ADC simulated performance.

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Open access peer-reviewed chapter

By Tales Cleber Pimenta, Gustavo Della Colletta, Odilon Dutra, Paulo C. Crepaldi, Leonardo B. Zocal and Luis Henrique de C. Ferreira

Submitted: December 10th 2011Reviewed: July 19th 2012Published: January 9th 2013

DOI: 10.5772/51715

Downloaded: 8074

Analog to digital (A/D) converters provide the interface between the real world (analog) and the digital processingdomain. The analog signals to be converted may originate from many transducers that convert physical phenomena like temperature, pressure or position to electrical signals. Since these electrical signals are analog voltage or current proportionals to the measured physical phenomena, its necessary to convert them to digital domain to conduct any computational. Nowadays, the development of the IC technology resulted in a growth of digital systems. A/D converters are present in the automotive industry, embedded systems and medicine for example. Thus, A/D converters have become important and the large variety of applications implies different types of A/D conversions.

For the A/D type considerations, the analog input should be characterized as one of the following three basic signal types [3].

Direct current (DC) or slowly varying analog signals.

Continuous changing and single event alternating current (AC) signals.

Pulse-amplitude signal.

For sampling the first type of signals, typical A/D conversion architectures are slope, voltage to frequency, counter ramp and sigma-delta. The second signal type is better sampled using the successive approximation, multistep and full parallel A/D conversion architectures. The last signal type uses successive approximation, multistep, pipeline and full parallel architectures.

After choosing the A/D converter architecture, it is important to keep in mind that any of them have nonlinearities that degrade the converter performance. These nonlinearities are accuracy parameters that can be defined in terms of Differential Nonlinearity (DNL) and Integral Nonlinearity (INL). Both have negative influence in the converter Effective Number of Bits (ENOB) [2].

Differential Nonlinearity (DNL) is a measure of how uniform the transfer function step sizes are. Each one is compared to the ideal step size and the difference in magnitude is the DNL.

Integral Nonlinearity (INL) is the code midpoints deviation from their ideal locations.

Therefore it is important to design implementations capable of improving the ADCs performance by improving DNL and INL.

Physiological signals have amplitudes ranging from tens of *V* to tens of *mV* and the frequencies spanning from DC to a few *KHz*. By considering those features and the application requirements, in order to make a reliable conversion, A/D converter may not have missing codes and must be monotonic. This can be accomplished assuring that the DNL error is less then *0.5* of last significant bits (LSBs).

Advances in low power circuit designs and CMOS technologies have supported the research and development of biomedical devices that can be implanted in the patient. These devices have a sensor interface specially designed to acquire physiological signals, usually composed of an operational amplifier with programmable gain and reconfigurable band-width features, low pass filter and an A/D converter [8, 10]. The signals are acquired and digitalized in the sensor, thus protecting data from external noise interference.

Specific research on A/D converters for biomedical application is focused on design low power circuits regardless of the monotonic feature, once DNL error is above *0.5 LSBs*, affecting the converter accuracy [5, 6]. The proposed Successive Approximation architecture offers both low power consumption and high accuracy features for use in biomedical applications.

Figure 1 illustrates the block diagram of the conventional SAR architecture. It is composed of a Successive Approximation Register that controls the operation and stores the output converted digital data, of a digital-to-analog converter stage (DAC), a comparator usually built with a operational amplifier and of a sample and hold circuit. The output can be taken serially from the comparator output or parallel from the SAR outputs.

The operation consists on evaluating and determining the bits of the converted digital word, one by one, initiating from the most significant bit. Thus the SAR architecture uses *n* clock cycles to convert a digital word of *n* bits. The successive approximation architecture provides intermediate sample rates at moderate power consumption that makes it suitable for low power applications.

The internal DAC stage, illustrated in Figure 1 is usually designed using capacitor networks that are susceptible to mismatches caused by the fabrication process variation, since the design is based on absolute capacitance values. These mismatches affect the converter accuracy, thus increasing the DNL and INL errors.

The presented architecture aims to eliminate the mismatches introduced during fabrication process by replacing the conventional internal DAC based on capacitor networks by a digital PWM modulator circuit and a first order low pass filter.

Figure 1 shows the block diagram of the proposed architecture (dotted line) as a modification on a conventional one (full line).

A PWM signal can be stated in terms of an even function, as illustrated in Figure 2 [1]. By using Fourier series, it can be represented in terms of equations (1) to (4).

where *A0 *represents the fundamental frequency, *An *states the even harmonics and *Bn *states the odd harmonics.

By performing the integral on a PWM signal with amplitude *(f(t)=k)*, the results are given by equations (5) to (7).

where *p* denotes the duty cycle.

That result shows that the PWM signal consists of a DC level and a square wave of zero average, as illustrated in Figure 3. Only the DC level is necessary in order to implement an internal DAC stage, since any DC level varying from zero to *k* can be obtained by selecting the proper duty cycle.

A way of recovering the DC level is to low pass filter the PWM signal. Since there is no ideal filter, the recovered DC level will have a certain ripple, as illustrated in Figure 4.

This section provides the modeling of a *4 bit* A/D Converter. Functional models for the SAR, PWM generator, Low pass filter and comparator blocks are discussed. Also the equating necessary to determine the filter features and clock frequencies is developed. SAR and PWM generator digital circuits are modeled using VHDL hardware description language. Comparator and the first order low pass filter are modeled using compartmental blocks.

A macro level simulation is performed using MatLab in order to validate the architecture. Electrical and post layout simulations are performed using Spectre simulator. The A/D converter Layout is developed in *0.5 m* standard CMOS process using Cadence Virtuoso and NCSU Design Kit (Free design kit available from North Caroline State University).

The Successive Approximation logic evaluates every digital word output bit according to the clock (CLK) signal. Thus, initiating by the most significant bit, one by one, the bits are evaluated and determined, until the last significant bit. Figure 4 illustrates the SAR digital circuit. The control logic is based on a simple shift register. There is also a flip-flop array that stores the input selection (SEL) that is attached to the comparator output.

On a reset (RST) signal, the shift register is loaded with 10000 and the flip-flop array is loaded with 0000. The combinational logic based on OR gates assures the value 1000 at the output (*Q3-Q0*). When the first clock pulse arrives, the shift register value is changed to 01000 while the flip-flop array remains with the same value, except for the most significant bit, since it has been already determined. Thus, the SAR output will show something like *X000*, where *X* represents the previously determined value.

One special feature is to use an extra flip-flop in the shift register to indicate the end of conversion (END), enabling the converted digital word to be read in the rising edge of the fifth clock pulse.

Circuits powered by *2.5V* using a *0.5 m* standard CMOS process, as in this case, can operate at *2MHz* maximum frequency, limiting the operation to about *200 Hz* of sampling rate, regarding the proposed architecture design. These feature lead to a high value of capacitance in the RC first order low pass filter, which is impracticable to be integrated. An alternative used to validate the proposed architecture is the implementation of an external first order RC low pass filter, as show in Figure 6.

The digital PWM modulator circuit is capable of varying the duty cycle of the output (PWM) according to the digital input word (*D3™ D0 *). The circuit is illustrated in Figure 7 and consists of registers, a synchronous *4-bit* counter, a combinational reset and a combinational comparison logic.

On a reset (RST) pulse, the counter resets to *0000* and the registers store the input word. The counter is incremented at every clock (CLK) cycle and the comparison logic assures that the output remains set while the counter does not reach the value stored into the registers. When it occurs, the output resets and the count continues until the counter reaches the end of counting. The reset logic makes the output flip-flop to set every time the counter resets, thus assuring that the output is set at the beginning of the counting. At this time, the registers are updated with the value present in the input (*D3- D0 *) from the SAR output. The reset logic also has a flip-flop responsible for synchronizing the output of the AND gate to the clock signal, since the AND inputs arrive at different timings.

The inverter based comparator circuit is used in order to decrease power consumption, since there is no quiescent power consumption. Figure 8 illustrates the comparator stage that uses a low power consumption architecture [7].

The circuit uses lagged clock signals to avoid overlapping, therefore assuring that the switches *S1, S2 *and *S3 *do not close at the same time. At time *1 *, the switch *S2 *is open and the switches *S1 *and *S3 *are closed, thus charging the capacitor *C* with *Vin-Vth *, where *Vth *is the inverter threshold voltage. Consequently any voltage variation during time *2 *will be sensed by the inverter.

At time *2 *, the switches *S1 *and *S3 *are open and *S2 *is closed, thus applying to the capacitor *C* the voltage produced by the PWM generator. This produces a voltage variation in the inverter input and the comparator makes the decision.

The switches *S1 *, *S2 *and *S3 *were replaced by solid state switches based on a nMOS transistor. After passing through a booster circuit, the clock signal is applied to the transistors gates.

The previous subsections illustrated the functional models for each stage of the proposed *4-bit* A/D converter. Nevertheless is still necessary to determine the low pass filter features and the clock frequency for the digital stages, SAR, comparator and PWM generator.

The comparator must evaluate every time the SAR tests a new bit, so they have to be synchronized by the same clock signal. Assuming that all *N* bits must have to be determined before a new sampling begins, equation (8) states the clock frequency for the comparator and the SAR stage.

where *N* represents the shift register number of bits, including the EOC bit and *fs *represents the sampling rate.

Now, the low pass filter time constant ought to be determined. Equation (9) shows the cut off frequency for the first order filter.

where *fc *represents the cut of frequency and states the filter time constant.

Assuming *5 *to accommodate a signal, equation (9) can be rewritten as equation (10)

From Figure 1, it can be observed that the filter must respond faster or at least at the same rate the SAR tests each bit. Thus, equation (11) states the maximum time constant for the low pass filter.

The frequency of the PWM signal must have to be characterized in order to be properly filtered. Since there is no ideal filter, the filtered signal will present a ripple. The PWM signal can be stated in terms of DC level and a sum of even harmonics, as in 12.

Taking into account only the even harmonics, as stated in 13, the energy carried by them can be determined.

It is known that the energy is proportional to

Equation 14 shows that the cosine term is independent of the duty cycle *p* and that the maximum energy occurs when

It can be observed that *cos(2 n )* is unity for any value of *n*, the term *sin(2 n )* is zero for any value of *n*. Thus, equation 15 can be rewritten in terms as 16.

Equation 16 shows that the maximum energy in each harmonic is obtained at different duty cycles.

Since there is no ideal filter, after the low pass filtering, the harmonics will not be completely eliminated, but attenuated. It is necessary to evaluate the minimum attenuation required by system, once it is directly linked to ripple amplitude present in the filtered DC level.

Since the first harmonic caries the most energy, it is reasonable to take just it into account to characterize the low pass filter.

Thus, considering the first harmonic (*n=1*) and the maximum energy scenario *h1 *represents the ripple amplitude variation given by the first harmonic.

It is important to notice that the cosine term introduces a variation interval of

Figure 9 illustrates two sequential quantization levels defined by the filtered PWM signal. If the ripple present in two sequential quantization levels overlaps, the converter will lead to a wrong conversion.

Thus, equation (19) states the minimum attenuation necessary to keep ripple under an acceptable value.

Since equation (19) expresses the attenuation in *dB*, the easier way to determine the PWM frequency is to plot the Bode diagram of the previously designed low pass filter and look directly into the frequency that provides the minimum necessary attenuation, as shown in Figure 10. Higher attenuation will decrease the ripple amplitude assuring the correct behavior of the A/D converter and a maximum attenuation is limited by the maximum frequency achieved by the PWM signal.

Finally, the PWM generator design requires a clock frequency

where

The *4 ™ bit* SAR ADC using PWM technique was designed for the ON *0.5 m* CMOS process using Cadence Virtuoso. simulations were conducted on Spectre simulator.

Figure 11 shows the circuit layout that occupies *0.749 mm2 *. The main simulation results are given in table I.

It can be observed that the proposed architecture improved the A/D Converter accuracy, since the DNL and INL values are less then 0.1 LSB and also that it consumes low power.

Technology | 0.5 um |

Supply Voltage | 2.5 V |

Max. Sampling frequency | 200 Hz |

ENOB (@166.67 Hz) | 3.7549-b |

DNL(max) | 0.086 LSB |

INL(max) | 0.99 LSB |

Power Consumption | 16 uW |

FoM (Figure of Merit) | 7.11 nJ/conv.-step |

Figure 12 shows the post layout simulation of DNL and INL for a slow ramp input. The values are good, lower than *0.086 LSB* and *0.1 LSB*, respectively, showing that the characteristic of proposed architecture does not differ too much form the ideal one.

Figure 13 illustrates the output frequency spectrum for a *32* point DFT. When ADC is tested with sinusoidal input at 166.67 Hz for a 15.63 Hz signal, it gives a good SNDR value of 24.36 dB, which results in 3.7549 effective number of bits (ENOB), thus proving the high accuracy achieved by the proposed architecture.

The 4-bit layout was fabricated trough MOSIS education program. The prototypes will be tested and the results will be compared to the simulations.

After chip characterization, a proper integrated low pass filter will be implemented in a new prototyping. A new ADC with a larger number of bits will be developed in order to better investigate the non-linearities, ENOB and FoM results.

In order to validate the proposed architecture, a *4 ™ bit* SAR A/D converter was designed in *0.5 m* CMOS standard process. The layout was developed using CADENCE Virtuoso and occupies *0.749 mm2 *. Post-layout simulations conducted in Spectre simulator using the BSIM3v3 model show that the modifications introduced in the internal DAC stage contributed to minimize DNL (*0.086 LSB*) and INL (*0.099*) errors, as expected.

They also contributed to improve A/D converter accuracy, since the SNDR was improved to *24.36 dB* of *25.84 dB* maximum theoretical value, leading to *3.75* effective bits.

The feature of being almost fully digital contributes to reduce the circuit complexity, the silicon area and power consumption.

The features of high accuracy and low power consumption make the proposed architecture suitable for biomedical applications.

This architecture can be extended to build higher resolution converters by only adding more hardware to the digital stages or building pipeline structures.

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