1. Introduction
Analog signal amplification in discrete-time system can be performed by switched-capacitor amplifiers (Martin et al., 1987). Switched-capacitor amplifier has been used in the design of digital-to-analog converter (Yang & Martin, 1989). The schematic for the switched-capacitor amplifier is shown in Figure 1.
Assuming an infinite op amp gain, the output voltage at end of
irrespective of the op amp offset voltage. If the clock waveforms shown in parentheses are used, then an inverting function is realized, and
again independent of the op amp input offset voltage. During the reset phase (
To improve the overall linearity, minimize the effect of common-mode interference and noise, the fully differential approach has obtained wider acceptance for accurate and/or high-speed signal processing. The switched-capacitor amplifier in (Martin et al., 1987) is a differential-to-single-ended design. A fully differential switched–capacitor amplifier using series compensation MOSFET capacitors has been presented in (Yoshizawa et al., 1999). However its operating voltage is ±2.5-V. Consequently there is an increasing demand to extend these improvements to this circuit.
This chapter describes the design of two 1V fully differential CMOS switched-capacitor amplifiers in a standard CMOS technology using improved bootstrapped switches. In section 2, the circuit realization of these two switched-capacitor amplifiers is addressed. In section 3 the circuit design of low-voltage building blocks is described. Experimental results are presented in section 4 to support the ideas put forth in paper. Finally conclusion is given.
2. Circuit Description
Figure 2 shows the first low-voltage fully differential CMOS switched-capacitor amplifier based on improved bootstrapped switches described in section 3.2, where switches S1-S4 and S1’-S4’ are matched improved bootstrapped switch pairs and switches S5-S6 and S5’-S6’ are NMOS matched switch pairs. In order to minimize the number of improved bootstrapped switches, two analog reference voltages are used:
To see how this circuit operates, consider the inverting circuit during the reset phase (
It should be noted that the clock waveforms with the primed superscripts change before the nonprimed waveforms in order to reduce nonlinearities due to charge injection.
Another technique to further reduce the number of improved bootstrapped switches is shown in Figure 5, where switches S1 and S4 and S1’ and S4’ are matched improved bootstrapped switch pairs. Those switches connected to
To see how this circuit operates, consider the inverting circuit during the reset phase (
Then based on charge conservation principle we can write:
3. Low-voltage building blocks
In this section, the low-voltage circuit building blocks used in the two fully differential CMOS switched-capacitor amplifiers are discussed
3.1. Op Amp
Figure 8 shows the used op amp. It is based on a fully differential folded-cascode p-type two-stage Miller-compensated configuration. The second stage is a common-source amplifier with active load which also allows a large output swing. In order to avoid the common-mode feedback (CMFB) circuit for the first stage, transistors
3.2. Improved bootstrapped switch
The improved bootstrapped switch shown in Figure 10 is utilized in the proposed circuit. The circuitry is improved version of that presented in (Abo & Gray, 1999). In the circuit presented in (Abo & Gray, 1999), the voltage at the drain side of the main switch
4. Experimental results
Based on the principles presented earlier, we have designed two 1-V fully differential CMOS switched-capacitor amplifiers. These two switched-capacitor amplifiers were operated with ±0.5-V. The capacitor sizes used were
Two figures of the measured input/output waveforms for 0.2V peak-to-peak sinusoidal differential input signal are shown in Figure 13 and Figure 14, respectively. The input signal was at 10kHz whereas the clock signal was at 1MHz. It can be seen that the gain is very close to the nominal value of -5.
Figure 15 and Figure 16 show the resulting output spectrum. As shown in Figure 15 and Figure 16, the even-order harmonics have been largely attenuated by the fully differential topology and 59dB and 52dB spurious-free dynamic range (SFDR) are exhibited, respectively. The circuits of Figure 2 and Figure 5 dissipate 206.5μW and 206.6μW, respectively with a 1V power supply.
5. Conclusion
Two fully differential CMOS 1-V switched-capacitor amplifiers have been described. Rail-to-rail operation of improved bootstrapped switches allows very low voltage robust switched-capacitor designs in standard CMOS technologies while avoiding transistor gate oxide overstress. The circuits have been fabricated and all aspects of their performance have been confirmed.
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