Summary of
1. Introduction
The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) (or just MOS) is widely used and presents many advantages over the bipolar transistors (BJT) in many applications.
It requires less silicon area and its fabrication process is relatively simpler. It is possible to implement most analog and digital circuits using almost exclusively MOS transistors. All these properties allow packing a large number of devices in a single integrated circuit.
Additionally, and most important, its operation requires less power, making it extremely suitable to RFID circuits.
This chapter aims to provide background on MOS transistors, from its physical operation to modeling, including RF modeling. The basic knowledge is essential to analyze and to design RFID circuits implemented using CMOS transistors. The chapter also presents noise analysis which is essential to low voltage signal, as it is the case of RFID circuits.
2. Physical CMOS operation
Fig. 1 shows the physical structure of the
The gate region has a length
There is also the
2.1. Forming the channel
As can be observed from the Fig. 1, the substrate forms
forward condition all the time. Since the drain is biased at a positive voltage, it is only necessary to connect the bulk to the ground in order to keep both junctions cut off.
With no bias applied to the gate, there are two back-to-back diodes between drain and source, and consequently, there is no current. This is true since each
When a positive voltage is applied between gate and source -
If
The symbols for the
2.2. Triode condition
Now, if a very small voltage
This condition of operation is known as ohmic, linear or triode.
2.3. Saturation condition
As
At the condition
Once the transistor enters the saturation region of operation, the drain current
Fig. 8 summarizes the conditions of operation of an
2.4. Deriving the i D - v DS relationship
Consider the biasing depicted in Fig. 9. Since the channel potential varies from zero at the source to
where
Since, by definition, current is proportional to charge times velocity, and considering the current is the same along the channel, then:
The minus signal is due to the negative charge of electrons. The velocity of carriers at low fields is the product of mobility (
Now integrating along the channel, one obtains:
Thus, the expression for the drain current in the triode region is:
The value of the current for the saturation operation can be obtained by replacing
As described earlier, the current does not depend on
Observe that expression (6) was obtained using the value of L, as given in Fig. 9. Nevertheless, when the transistor is saturated, the channel becomes shorter, as shown in Fig. 7. A reduction in the length of the channel, known as channel length modulation, means a variation in the resistance, and therefore a variation in the current
Expression (6) can be modified in order to include the variation in the channel length, represented as
which can be approximated to:
Since
where
The effect of channel length modulation can be seen in the
An extrapolation of
2.5. Output resistance
Fig. 10 and expression (9) show that an increase in
which can be simplified to:
Therefore, a MOS transistor in the saturation region is not totally independent of
Considering the transistor operating in the triode region, as given by expression (5), if the value of
This relationship represents the behavior of the MOS transistor as a linear resistance whose value is controlled by
2.6. Transconductance
The large signal behavior of a MOS transistor in the saturation region is given by expression (6). Nevertheless, for a given biasing, the designer may be interested in the small signal behavior of the transistor. For a given small variation in the
which results in:
Observe the transconductance depends on the ratio
In this case, the transconductance depends on the ratio
It clearly does not depend on ratio
2.7. Body effect
In many circuits, the substrate and the source are not at the same potential, as it is possible to stack transistors. In that case, the substrate it is at lower potential than the source, and therefore the source-substrate junction becomes reversed biased. This reverse biasing widens the depletion layer, which in turn reduces the channel depth.
The effect of the bulk-source voltage
where
where
Any signal between substrate and source promotes a drain current component. The substrate acts as a second gate, and in turn will present a corresponding trasnconductance, named body transconductance, given as:
From expressions (6), (17) and (18), then it is possible to state that:
where
And it is in the range of
2.8. Small signal model
Considering the output impedance, the transconductance and the body effect, the small signal model of a
If the source and the substrate are at the same potential, then the model can be simplified, as the term
2.9. Summary
Table 1 summarizes the main
Saturation | Condition | |
i-v characteristic | ||
Output resistance | ||
Transconductance | ||
Body transconductance | ||
Triode | Condition | |
i-v characteristic | ||
Output resistance | ||
Threshold voltage |
2.10. p MOS transistor
In a
3. RF CMOS model
Unfortunately, the structure and the operation of a MOS transistor present parasitic capacitances that limit its frequency of operation. The parasitic capacitances may result from the capacitor formed between the gate and the channel, between gate and source/drain, and between drain/source and substrate.
3.1. Gate capacitances
The gate, the dielectric and the channel form a capacitor. When the transistor is working in the triode region with a small voltage
When the transistor is working in the saturation region, the channel presents a tapered shape and it is pinched off at the drain end, as presented in Fig. 7. It can be seen that the gate to channel capacitance is almost entirely modeled at the source, since the drain does not present a channel. It can be shown that the capacitances are:
If the transistor is cut off, there is no capacitance between gate and channel, since there is no channel for cut off. The entire capacitance is then between the gate and the substrate, therefore:
As can be observed from Fig. 1, the gate extends over the drain and the source areas. Therefore, there is an overlapping capacitance between the gate and the drain/source. Denoting the overlapping length by
For modern processes,
3.2. Junction capacitances
As shown by Fig. 2 there are two reversed biased junctions formed between the substrate and source/drain. Each junction consists of two semiconductors (drain/source and the substrate) and the depletion layer, thus forming a capacitor. The source-substrate capacitance can be found to be:
where
By the same way, the drain-substrate capacitance is given by:
3.3. The high frequency model
The small signal model of the MOS transistor given in Fig. 11 can be update to include the gate and the junction capacitances, as presented in Fig. 14. Although this model represents the transistor for high frequencies, it is very complex for manual analysis.
If the source and the substrate are shorted, the model can be greatly simplified, as shown in Fig. 15.
4. Unity gain frequency
An important Fig. of merit for the MOS transistor is the unit gain frequency that is defined as the frequency in which the short circuit current gain becomes unit. This definition is based in the common source configuration, as shown in Fig. 16.
The current
The approximation is due to the fact that
Therefore, from expressions (29) and (30):
Since the magnitude of
Therefore, the unit gain frequency is:
As can be observed, the unit gain frequency is directly proportional to
4. RF CMOS noise model
The two most important types of noise in MOS devices are the
4.1. Thermal noise
The main source of thermal noise in a MOS transistor is due to the resistive channel in the active region, and has a value of:
where
The other source of thermal noise is the gate. Fluctuation in the channel potential couples capacitively into the gate terminal, which in turn translates into a noise gate current. Noise gate current can also be produced by the resistive material of the gate. This total noise gate can be ignored at low frequencies but becomes significant at high frequencies as it is the case of RF circuits. It has been shown the gate noise may be expressed as:
where
Mostly of the time, instead of using a current source at the gate, it is more convenient to consider an equivalent voltage source. The equivalent voltage source of expressions (31) and(32) is given by:
where
4.2. 1/f noise
The
The
For
As can be observed from expression (53), the
The
where
4.3. Noise model
The noise model of an
5. Conclusions
The proper understanding of physical operation to modeling of CMOS transistors is essential to the analysis and design of RFID circuits. Among its advantages, the CMOS transistors demands lower power consumption than other transistors.
Noise analysis of CMOS transistors is also fundamental to analysis and design of any circuit, including RFID.
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