1. Introduction

Analog signal amplification in discrete-time system can be performed by switched-capacitor amplifiers (Martin et al., 1987). Switched-capacitor amplifier has been used in the design of digital-to-analog converter (Yang & Martin, 1989). The schematic for the switched-capacitor amplifier is shown in Figure 1.

Figure 1.

A differential-to-single-ended CMOS switched-capacitor amplifier. Depending on the input-stage clock signals, the amplifier can be either noninverting (as shown) or inverting (input-stage clocks shown in parentheses).

Assuming an infinite op amp gain, the output voltage at end of ϕ2 is given by

irrespective of the op amp offset voltage. If the clock waveforms shown in parentheses are used, then an inverting function is realized, and

again independent of the op amp input offset voltage. During the reset phase ( ϕ1 C3 is connected in feedback around the op amp which causes the output change only by the op amp input offset voltage. The switches are realized as CMOS transmission gate. For low supply voltages, a conductance gap begins to appear around the middle of the supply range (Crols & Steyaert, 1994). This means that under low-voltage operation, this configuration no longer works. Existing solutions of low-voltage operation of switched-capacitor circuits include using low threshold voltage process (Matsuya & Yamada, 1994), switched-opamp technique (Baschirotto & Castello, 1997, Cheung et al., 2001, Cheung et al., 2002, Cheung et al., 2003, Crols & Steyaert, 1994, Peluso et al., 1997, Peluso et al., 1998, Sauerbrey et al., 2002, Waltari & Halonen, 2001, Wu et al., 2007), opamp-reset switching technique (Chang, & Moon, 2003, Keskin et al., 2002, Wang &. Embabi, 2003), voltage multiplier (charge pump) technique (Nicollini et al., 1996, Rombouts et al., 2001), clock multiplier (clock booster) technique (Au & Leung, 1997, Rabii & Wooley, 1997), and bootstrapping switch technique (Abo & Gray, 1999, Dessouky & Kaiser, 2001, Park et al., 2004). First, the use of low-threshold transistors involves special and high-cost technology (Matsuya & Yamada, 1994). The switched-opamp technique (Baschirotto & Castello, 1997, Cheung et al., 2001, Cheung et al., 2002, Cheung et al., 2003, Crols & Steyaert, 1994, Peluso et al., 1997, Peluso et al., 1998, Sauerbrey et al., 2002, Waltari & Halonen, 2001, Wu et al., 2007) and opamp-reset switching technique (Chang, & Moon, 2003, Keskin et al., 2002, Wang &. Embabi, 2003) can only be applicable to filters, delta-sigma modulators, and pipelined analog-to-digital converters. The main limitations of voltage multiplier (charge pump) technique (Nicollini et al., 1996, Rombouts et al., 2001) regards: the gate-oxide breakdown reliability, the need to supply a dc current to the op amps from the multiplied supply (this necessitates the use of an external capacitor, with additional cost), and the conversion efficiency of the charge pump (which is lower than 100%). The clock multiplier (clock booster) technique (Au & Leung, 1997, Rabii & Wooley, 1997) suffers from the technology limitation associated with the gate oxide breakdown. Device reliability can be assured in the bootstrapped switch technique (Abo & Gray, 1999, Dessouky & Kaiser, 2001, Park et al., 2004), owing to keeping the terminal-to-terminal voltages of the MOSFET devices within the rated operating supply voltage of the technology. The bootstrapped switch provides a small, nearly constant input resistance. The switch linearity is also improved, and signal-dependent charge injections is reduced.

To improve the overall linearity, minimize the effect of common-mode interference and noise, the fully differential approach has obtained wider acceptance for accurate and/or high-speed signal processing. The switched-capacitor amplifier in (Martin et al., 1987) is a differential-to-single-ended design. A fully differential switched–capacitor amplifier using series compensation MOSFET capacitors has been presented in (Yoshizawa et al., 1999). However its operating voltage is ±2.5-V. Consequently there is an increasing demand to extend these improvements to this circuit.

This chapter describes the design of two 1V fully differential CMOS switched-capacitor amplifiers in a standard CMOS technology using improved bootstrapped switches. In section 2, the circuit realization of these two switched-capacitor amplifiers is addressed. In section 3 the circuit design of low-voltage building blocks is described. Experimental results are presented in section 4 to support the ideas put forth in paper. Finally conclusion is given.

2. Circuit Description

Figure 2.

First low-voltage fully differential CMOS switched-capacitor amplifier. Depending on the input-stage clock signals, the amplifier can be either noninverting (as shown) or inverting (input-stage clocks shown in parentheses).

Figure 2 shows the first low-voltage fully differential CMOS switched-capacitor amplifier based on improved bootstrapped switches described in section 3.2, where switches S1-S4 and S1’-S4’ are matched improved bootstrapped switch pairs and switches S5-S6 and S5’-S6’ are NMOS matched switch pairs. In order to minimize the number of improved bootstrapped switches, two analog reference voltages are used: VSS at the op amp input where a normal NMOS switch can be used to switch the lowest supply voltage, and a VDD+VSS2 common-mode voltage at the op amp output and the circuit input to maximize the signal swing. The improved bootstrapped switch is used to switch signals at this voltage level. Figure 3 is the single-ended version of Figure 2.

Figure 3.

Single-ended version of Figure 2.

To see how this circuit operates, consider the inverting circuit during the reset phase ( ϕ1 ) and during valid output phase ( ϕ2 ), as shown in Figure 4. Then based on charge conservation principle we can write:

It should be noted that the clock waveforms with the primed superscripts change before the nonprimed waveforms in order to reduce nonlinearities due to charge injection.

Another technique to further reduce the number of improved bootstrapped switches is shown in Figure 5, where switches S1 and S4 and S1’ and S4’ are matched improved bootstrapped switch pairs. Those switches connected to VSS are realized with NMOS transistors, while those switches connected to VDD are realized with PMOS transistors. In Figure 5 a single reference voltage at VSS is used. However, the signal still varies around VDD+VSS2 at the circuit input as well as at the op amp output to preserve the maximum swing. The difference between the two reference voltages is compensated by injecting a fixed amount of charge at the op amp input using extra capacitor pairs CM1 = C12 and CM2 = C22 ( C′M1 = C′12 and C′M2 = C′22 ) switching between VDD and VSS (Baschirotto & Castello, 1997). Figure 6 is the single-ended version of Figure 5.

Figure 4.

Single-ended CMOS switched-capacitor amplifier, (a) during reset phase ( ϕ1 ), (b) during valid output phase ( ϕ2

To see how this circuit operates, consider the inverting circuit during the reset phase ( ϕ1 ) and during valid output phase ( ϕ2 ), as shown in Figure 7.

Then based on charge conservation principle we can write:

Figure 5.

Second low-voltage fully differential CMOS switched-capacitor amplifier. Depending on the input-stage clock signals, the amplifier can be either noninverting (as shown) or inverting (input-stage clocks shown in parentheses).

Figure 6.

Single-ended version of Figure 5.

3. Low-voltage building blocks

In this section, the low-voltage circuit building blocks used in the two fully differential CMOS switched-capacitor amplifiers are discussed

3.1. Op Amp

Figure 8 shows the used op amp. It is based on a fully differential folded-cascode p-type two-stage Miller-compensated configuration. The second stage is a common-source amplifier with active load which also allows a large output swing. In order to avoid the common-mode feedback (CMFB) circuit for the first stage, transistors M51, M52, M61, and M62 are used, which is similar to (Waltari & Halonen, 1998). For the second stage, a simple passive switched-capacitor CMFB circuit, shown in Figure 9, is used. The improved bootstrapped switches are used to connect and disconnect the common-mode sensing capacitor.

Figure 8.

Low-voltage op amp.

Figure 9.

Common-mode feedback circuit for the low-voltage op amp.

4. Experimental results

Based on the principles presented earlier, we have designed two 1-V fully differential CMOS switched-capacitor amplifiers. These two switched-capacitor amplifiers were operated with ±0.5-V. The capacitor sizes used were C1 =1.25-pF, C2 =0.25-pF, and C3 =0.25-pF, for a nominal gain of -5. The circuits of Figure 2 and Figure 5 were fabricated using a TSMC 0.35-μm double-poly four-metal CMOS technology. Figure 11 and Figure 12 show the photomicrographs of Figure 2 and Figure 5, respectively. The chip areas of Figure 2 and Figure 5 excluding bonding pads are 414×278-μm and 460×330-μm, respectively.

Figure 11.

Photomicrograph of Figure 2.

Figure 12.

Photomicrograph of Figure 5.

Two figures of the measured input/output waveforms for 0.2V peak-to-peak sinusoidal differential input signal are shown in Figure 13 and Figure 14, respectively. The input signal was at 10kHz whereas the clock signal was at 1MHz. It can be seen that the gain is very close to the nominal value of -5.

Figure 13.

Measured differential input and output waveforms of Figure 2 (f_clk=1-MHz, f_in=10-kHz, sinusoidal differential input voltage=0.2-V_pp).

Figure 14.

Measured differential input and output waveforms of Figure 5 (f_clk=1-MHz, f_in=10-kHz, sinusoidal differential input voltage=0.2-V_pp)

Figure 15 and Figure 16 show the resulting output spectrum. As shown in Figure 15 and Figure 16, the even-order harmonics have been largely attenuated by the fully differential topology and 59dB and 52dB spurious-free dynamic range (SFDR) are exhibited, respectively. The circuits of Figure 2 and Figure 5 dissipate 206.5μW and 206.6μW, respectively with a 1V power supply.

Figure 15.

Measured output spectrum of Figure 2.

5. Conclusion

Two fully differential CMOS 1-V switched-capacitor amplifiers have been described. Rail-to-rail operation of improved bootstrapped switches allows very low voltage robust switched-capacitor designs in standard CMOS technologies while avoiding transistor gate oxide overstress. The circuits have been fabricated and all aspects of their performance have been confirmed.