About the book
A notable limitation of the bus-based interconnection System-on-Chip (SoC) is scalability. This is due to the physical limitation being imposed by high-density of the supported ports. An effective and widely embraced approach for addressing the issue is a Network-on-Chip (NoC) architecture. Consequently, a large number of cores can be parallelized and packed into the majority of computing devices. In this context, a huge amount of communications has been experienced between the intellectual properties (IPs) and the cores. The NoC technology can offer the required architectural flexibility and parallelism for supporting the associated massive cores and IPs. Based on this, for high-performance communication, there has been a growing increase in the implementation of NoC architectures for on-chip communications in the embedded multicore processors such as Multiprocessor SoCs (MPSoCs), Chip Multiprocessors (CMPs), and Graphics Processing Units (GPUs).
This book aims to provide the fundamental concepts and the state-of-the-art in the area of NoC architecture. Moreover, as the employed routing algorithm can considerably influence the overall network performance metrics regarding the latency and throughput, this book will cover a number of innovative routing algorithms that are not only capable of minimizing the latency but also effective for maximizing the throughput. Also, scheduler for an integrated optical NoC with salient features such as high throughput, low latency, and fairness will be considered. Besides, due attention will also be given to area limitation and power consumption in the NoC design architecture.
Other topics of interest include, but are not limited, to the following: innovative NoC architectures; novel interconnect technologies with salient features; switch allocation and on-chip security.