Open access peer-reviewed Edited Volume


Isiaka Alimi

Instituto de Telecomunicações

Member of IEEE with expertise in Optical Communications, currently working on a funded project concerning the development of a quantum random number generator network server. Final Status Confirmed


Oluyomi Aboderin

Instituto de Telecomunicações

Dr. Aboderin joined the National Space Research and Development Agency (NASRDA) in 2005 as a research engineer and obtained a Ph.D. in Telecommunications Engineering from the University of Porto years later with a lot of practical experience.

Nelson Muga

Instituto de Telecomunicações

Dr. Muga received his Ph.D. in Physical Engineering at the Aveiro University in 2011 for research on polarization-effects in fiber-optic communication systems. He is currently a senior researcher at the Instituto de Telecomunicações, Aveiro, where he participated in 20+ R&D research projects, developing expertise in the field of high-speed optical communication systems and quantum secure optical communications.

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António L. Teixeira

Universidade de Aveiro

Dr. Teixeira received a Ph.D. degree from the University of Aveiro (UA) in 1999, partly developed with the University of Rochester. He worked for Nokia Siemens Networks and Coriant as a Standardization Expert for a short period of time. Since 2014, he has been the Dean of UA Doctoral School with over 400 papers published (over 100 in journals) and is a holder of eight patents.


System-On-Chip and Hybrid NoC Broadcast Routing Arbitration Switch Allocation Packets Scheduling Application Mapping Thermal-Aware Mapping Silicon Photonics Nanophotonics 3D Integration Through-Silicon-Vias (TSVs)

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About the book

A notable limitation of the bus-based interconnection System-on-Chip (SoC) is scalability. This is due to the physical limitation being imposed by high-density of the supported ports. An effective and widely embraced approach for addressing the issue is a Network-on-Chip (NoC) architecture. Consequently, a large number of cores can be parallelized and packed into the majority of computing devices. In this context, a huge amount of communications has been experienced between the intellectual properties (IPs) and the cores. The NoC technology can offer the required architectural flexibility and parallelism for supporting the associated massive cores and IPs. Based on this, for high-performance communication, there has been a growing increase in the implementation of NoC architectures for on-chip communications in the embedded multicore processors such as Multiprocessor SoCs (MPSoCs), Chip Multiprocessors (CMPs), and Graphics Processing Units (GPUs).

This book aims to provide the fundamental concepts and the state-of-the-art in the area of NoC architecture. Moreover, as the employed routing algorithm can considerably influence the overall network performance metrics regarding the latency and throughput, this book will cover a number of innovative routing algorithms that are not only capable of minimizing the latency but also effective for maximizing the throughput. Also, scheduler for an integrated optical NoC with salient features such as high throughput, low latency, and fairness will be considered. Besides, due attention will also be given to area limitation and power consumption in the NoC design architecture.

Other topics of interest include, but are not limited, to the following: innovative NoC architectures; novel interconnect technologies with salient features; switch allocation and on-chip security.

Publishing process

Book initiated and editor appointed

Date completed: July 2nd 2020

Applications to edit the book are assessed and a suitable editor is selected, at which point the process begins.

Chapter proposals submitted and reviewed

Deadline Extended: Open for Submissions

Potential authors submit chapter proposals ready for review by the academic editor and our publishing review team.

Approved chapters written in full and submitted

Deadline for full chapters: September 21st 2020

Once approved by the academic editor and publishing review team, chapters are written and submitted according to pre-agreed parameters

Full chapters peer reviewed

Review results due: December 10th 2020

Full chapter manuscripts are screened for plagiarism and undergo a Main Editor Peer Review. Results are sent to authors within 30 days of submission, with suggestions for rounds of revisions.

Book compiled, published and promoted

Expected publication date: February 8th 2021

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About the editor

Isiaka Alimi

Instituto de Telecomunicações

Isiaka A. Alimi received his Ph.D. degree in Telecommunications Engineering from the University of Aveiro, Portugal, in 2018. He was a Senior Engineer (radio frequency management and transmission) for the Federal Radio Corporation of Nigeria from 2004 to 2012. He joined the Department of Electrical and Electronics Engineering, Federal University of Technology, Akure, Nigeria, in 2013. He is currently a researcher at the Instituto de Telecomunicações, Aveiro, Portugal, where he has been participating in various R&D activities. He has authored/co-authored more than 30 technical papers in journals and 6 book chapters. His research interests include network security, optical communication networks, microwave photonics, advanced signal processing and their applications for effective resources management in access networks. Dr. Alimi is a member of the Institute of Electrical and Electronics Engineers (IEEE).

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Book chapters authored 3

Books edited 1

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