Open access peer-reviewed Edited Volume

Field Programmable Gate Arrays (FPGAs) II

George Dekoulis

Aerospace Engineering Institute


FPGA Architecture Programmable LogicDigital Signal Processing FPGA Circuit Design Layout Techniques CAD for FPGAs Algorithms Optimization High-Level Abstractions Tools for FPGAs Verilog C ASIC FPGA-like Computing Engines Accelerators Reconfigurable ComputingCPU GPU SoC

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About the book

This book aims to analyze recent state-of-the-art innovations in the area of Field Programmable Gate Arrays (FPGAs). The book will focus, but not limit to, six wide subject areas, namely: FPGA Architectures, FPGA Circuit Design, CAD for FPGAs, High-Level Abstractions and Tools for FPGAs, FPGA-based and FPGA-like Computing Engines and all possible engineering applications that implement FPGA design techniques.
FPGA Architectures are related to programmable logic fabrics and their components, including flexible logic cells, routing, embedded blocks (memory, processors, DSP) and I/O interfacing. Novel commercial architectures and architectural features are also included. FPGA Circuit Design refers to circuits and layout implementations using FPGAs. The impact of future process and design technologies on FPGAs will also be discussed. CAD for FPGAs refers to algorithms for synthesis, mapping, technology, logic and timing optimization, clustering, placement and routing of FPGAs. Book chapters will be included on novel design software for system-level partitioning, debug and verification. Book chapters on algorithms for modeling, analysis, and optimization of timing and power are welcome. The methods for analyzing and improving static and dynamic power, power and clock distribution, yield, manufacturability, security, reliability, and testability will also be discussed. The usage of novel memory or nano-scale devices in FPGAs will also be covered. High-Level Abstractions and Tools for FPGAs refer to general-purpose and domain-specific languages, tools and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. They also refer to novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems. FPGA-based and FPGA-like Computing Engines encompass systems and software for compiled accelerators, re-configurable computing, adaptive computing, and rapid-prototyping. They also incorporate programmable overlay architectures implemented using FPGAs. Applications and Design Studies are welcome on the implementation of novel designs using FPGAs establishing state-of-the-art in high-performance, low-power, efficiency, security or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (CPU, GPU) are welcome.
The book welcomes submissions on all areas of electronics, electrical engineering, computer science and engineering, telecommunications, space engineering, satellite communications, avionics, aerospace engineering or re-configurable processing that implement FPGA techniques.
We hope this book will be beneficial to both professionals, researchers, and academicians and, moreover, to inspire the younger generations into pursuing relevant academic studies and professional careers within the FPGA industry. 

Publishing process

Book initiated and editor appointed

Date completed: August 6th 2019

Applications to edit the book are assessed and a suitable editor is selected, at which point the process begins.

Chapter proposals submitted and reviewed

Deadline Extended: Open for Submissions

Potential authors submit chapter proposals ready for review by the academic editor and our publishing review team.

Approved chapters written in full and submitted

Deadline for full chapters: October 26th 2019

Once approved by the academic editor and publishing review team, chapters are written and submitted according to pre-agreed parameters

Full chapters peer reviewed

Review results due: January 14th 2020

Full chapter manuscripts are screened for plagiarism and undergo a Main Editor Peer Review. Results are sent to authors within 30 days of submission, with suggestions for rounds of revisions.

Book compiled, published and promoted

Expected publication date: March 14th 2020

All chapters are copy-checked and typesetted before being published. IntechOpen regularly submits its books to major databases for evaluation and coverage, including the Clarivate Analytics Book Citation Index in the Web of ScienceTM Core Collection. Other discipline-specific databases are also targeted, such as Web of Science's BIOSIS Previews.

About the editor

George Dekoulis

Aerospace Engineering Institute

Prof. George Dekoulis received a PhD in Space Engineering and Communications from Lancaster University, UK, in 2007. He was awarded a 1st Class BEng (Hons) in Communications Engineering from De Montfort University, UK, in 2001. He received several awards from STFC, UK and EPSRC, UK and the 'IET Hudswell International Research Scholarship”. He is currently a professor at Aerospace Engineering Institute (AEI), Cyprus. Founder of the IEEE Aerospace and Electronic Systems Society (AESS) - Cyprus. General Chair of IEEE Aerospace Engineering Innovations 2019 (IEEE AEI 2019) Symposium, 20-23 April 2019, Limassol, Cyprus. He has previously worked as a professor in Aerospace Engineering at various Departments, such as Space & Planetary Physics, Aeronautical & Space Engineering, Professional Flight, Robotics/Mechatronics & Mechanical Engineering, Computer Science & Engineering and Electrical & Electronics Engineering. His research is focused on the design of reconfigurable Aerospace Engineering systems.

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