The gate-all-around silicon nanowire transistor (GAA-NW) has manifested itself as one of the most fortunate candidates for advanced node integrated circuits (ICs). As the GAA transistor has stronger gate control, better scalability, as well as improved transport properties, the device has been considered as a potential alternative for scaling beyond FinFET. In recent publications, the basic feature and scalability of nanowire have been widely explored primarily focusing on intrinsic device characteristics. Although the GAA-NW has superior gate control compared to other architectures, the device is surrounded by huge vertical gate metal line and S/D contact metal lines. The presence of this vast metal line forms a strong parasitic capacitance. While scaling down sub-7 nm node dimensions, these capacitances influence strongly on the overall device performances. In this chapter, we have discussed the effects of various parasitic capacitances on scaling the device dimensions as well as their performances at high-frequency operations. TCAD-based compact model was used to study the impacts of scaling GAA-NW’s dimensions on power performance and area gain perspective (PPA).
Part of the book: Nanowires