Yasuaki Ishikawa

By M. Ajmal Khan and Yasuaki Ishikawa

Stacking fault free and planar defects (twin plane) free catalyzed Si nanowires (Si NWs) is essential for the carrier transport in the nanoscale devices applications. In this chapter, In-catalyzed, vertically aligned and cone-shaped Si NWs arrays were grown by using vapor–liquid–solid (VLS) mode on Si (111) substrates. We have successfully controlled the verticality and (111)-orientation of Si NWs as well as scaled down the diameter to 18 nm. The density of Si NWs was also enhanced from 2.5 μm−2 to 70 μm−2. Such vertically aligned, (111)-oriented p-type Si NWs are very important for the nanoscale device applications including Si NWs/c-Si tandem solar cells and p-Si NWs/n-InGaZnO Heterojunction LEDs. Next, the influence of substrate growth temperature (TS), cooling rate (∆TS/∆𝑡) on the formation of planar defects, twining along [112] direction and stacking fault in Si NWs perpendicular to (111)-orientation were deeply investigated. Finally, one simple model was proposed to explain the formation of stacking fault, twining of planar defects in perpendicular direction to the axial growth direction of Si NWs. When the TS was decreased from 600°C with the cooling rate of 100°C/240 sec to room temperature (RT) after Si NWs growth then the twin planar defects perpendicular to the substrate and along different segments of (111)-oriented Si NWs were observed.

Part of the book: Nanowires