Chapters authored
Industrial IoT Using Wavelet Transform
For many years now, communication in the industrial sector has been characterized by a new trend of integrating the wireless concept through cyber-physical systems (CPS). This emergence, known as the Smart Factory, is based on the convergence of industrial trades and digital applications to create an intelligent manufacturing system. This will ensure high adaptability of production and more efficient resource input. It should be noted that data is the key element in the development of the Internet of Things ecosystem. Thanks to the IoT, the user can act in real time and in a digital way on his industrial environment, to optimize several processes such as production improvement, machine control, or optimization of supply chains in real time. The choice of the connectivity strategy is made according to several criteria and is based on the choice of the sensor. This mainly depends on location (indoor, outdoor, …), mobility, energy consumption, remote control, amount of data, sending frequency and security. In this chapter, we present an Industrial IoT architecture with two operating modes: MtO (Many-to-One) and OtM (One-to-Many). An optimal choice of the wavelet in terms of bit error rate is made to perform simulations in an industrial channel. A model of this channel is developed in order to simulate the performance of the communication architecture in an environment very close to industry. The optimization of the communication systems is ensured by error correcting codes.
Part of the book: Wavelet Theory
Ultra-High Performance and Low-Cost Architecture of Discrete Wavelet Transforms
This work targets the challenging issue to produce high throughput and low-cost configurable architecture of Discrete wavelet transforms (DWT). More specifically, it proposes a new hardware architecture of the first and second generation of DWT using a modified multi-resolution tree. This approach is based on serializations and interleaving of data between different stages. The designed architecture is massively parallelized and sharing hardware between low-pass and high-pass filters in the wavelet transformation algorithm. Consequently, to process data in high speed and decrease hardware usage. The different steps of the post/pre-synthesis configurable algorithm are detailed in this paper. A modulization in VHDL at RTL level and implementation of the designed architecture on FPGA technology in a NexysVideo board (Artix 7 FPGA) are done in this work, where the performance, the configurability and the generic of our architecture are highly enhanced. The implementation results indicate that our proposed architectures provide a very high-speed data processing with low needed resources. As an example, with the parameters depth order equal 2, filter order equal 2, order quantization equal 5 and a parallel degree P = 16, we reach a bit rate around 3160 Mega samples per second with low used of logic elements (≈400) and logic registers (≈700).
Part of the book: Wavelet Theory