The design and component level architectures of a novel offset compensated digital baseline restorer (BLR) and an original hybrid interpolator are described. It allows diminishing the effect of modifications occurring during the readout of Positron Emission Tomography (PET) pulses. Without treatment, such artifacts can result in a reduction in the scanner’s performance, such as its sensitivity and resolution. The BLR recompenses the offset of PET pulses. Afterward, the pertinent parts of these pulses are located. Onward, the located portion of the signal is resampled by using a hybrid interpolator. This is constructed by cascading an optimized weighted least-square interpolator (WLSI) and a Simplified Linear Interpolator (SLI). The regulation processes for the WLSI coefficients and evaluation of the BLR and the interpolator modules are presented. The proposed hybrid interpolator’s computational complexity is compared with classic counterparts. These modules are implemented in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) and synthesized on a Field Programmable Gate Array (FPGA). The functionality of the system is validated with an experimental setup. Results reveal notable computational gain along with adequate dynamic restitution of the bipolar offsets besides a useful and accurate improvement of the temporal resolution relative to the computationally complex conventional equivalents.
Part of the book: Integrated Circuits/Microchips