Chapters authored
Enabling Optical Wired and Wireless Technologies for 5G and Beyond Networks
The emerging fifth-generation mobile communications are envisaged to support massive number of deployment scenarios based on the respective use case requirements. The requirements can be efficiently attended with ultradense small-cell cloud radio access network (C-RAN) approach. However, the C-RAN architecture imposes stringent requirements on the transport networks. This book chapter presents high-capacity and low-latency optical wired and wireless networking solutions that are capable of attending to the network demands. Meanwhile, with optical communication evolutions, there has been advent of enhanced photonic integrated circuits (PICs). The PICs are capable of offering advantages such as low-power consumption, high-mechanical stability, low footprint, small dimension, enhanced functionalities, and ease of complex system architectures. Consequently, we exploit the PICs capabilities in designing and developing the physical layer architecture of the second standard of the next-generation passive optical network (NG-PON2) system. Apart from being capable of alleviating the associated losses of the transceiver, the proposed architectures aid in increasing the system power budget. Moreover, its implementation can significantly help in reducing the optical-electrical-optical conversions issue and the required number of optical connections, which are part of the main problems being faced in the miniaturization of network elements. Additionally, we present simulation results for the model validation.
Part of the book: Telecommunication Systems
Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction
Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.
Part of the book: Network-on-Chip