Geometrical parameters and values of FinFETs and GAAFETs.
DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.
- field-effect transistors
- RC delay
- parasitic resistance
- parasitic capacitance
Gate-all-around (GAA) is a widely-using structure such as logic field-effect transistor (FET) due to its excellent short channel characteristics [1, 2, 3, 4, 5, 6] or its high surface-to-volume ratio [7, 8], 3-D NAND flash memory for bit-cost scalability [9, 10], photodiode due to its waveguide effect [11, 12], and gas sensor due to its high physical fill factor or surface-to-volume ratio [13, 14]. Especially for logic applications, GAAFETs have been introduced by attaining good gate electronics and increasing current drivability under the same active area.
Currently, fin-shaped FETs (FinFETs) have been scaled down to 10-nm node  and further to 5-nm node  by forming ultra-sharp fin for high current drivability while maintaining gate-to-channel controllability. GAAFETs are possibly showing great potential to substitute FinFETs in the following technology node, and the performance comparisons between FinFETs and GAAFETs have been investigated [3, 4, 5, 6, 17]. But more detailed analysis between FinFETs and GAAFETs is needed to set the device guideline by considering fine TCAD calibration and middle-of-line levels.
Therefore, in this work, DC/AC performances of 3-nm-node GAAFETs were investigated using fully-calibrated TCAD platform. By changing the GAA geometries, we found optimal GAA structure to minimize the RC delay for three different applications such as low power (LP), standard performance (SP), and high performance (HP) applications.
2. Device structure and simulation methods
All the simulation works were performed using Sentaurus TCAD . Drift diffusion transport equations were calculated self-consistently with Poisson and electron/hole continuity equations. Density-gradient model was adopted for the quantum confinement of carriers within the channel. Slotboom bandgap narrowing model was used to consider the doping-dependent energy bandgap. Mobility models include Lombardi for the mobility degradation at the channel/oxide interface, inversion and accumulation layer model for impurity, phonon, and surface roughness scatterings, and low-field ballistic model for quasi-ballistic effects in ultra-short gate length (Lg). Shockley-Read-Hall, Auger, and Hurkx band-to-band tunneling recombination models were adopted. Deformation potential model was used to consider the stress-induced energy bandgap, effective mass, and effective density-of-states. All these physical models were used equivalently in [19, 20].
Figure 1 shows the schematic diagrams of FinFETs and three-stacked GAAFETs. FinFETs have highly-doped punch-through-stopper (PTS) at 2 × 1018 and 4 × 1018 cm−3 for NFETs and PFETs, respectively, in order to prevent the sub-fin leakage currents at off state [21, 22]. GAAFETs, on the other hand, have buried oxide (BOX) layer beneath the source/drain (S/D) regions without PTS so that the bottom leakage currents are completely blocked [1, 23]. Bulk FinFETs can adopt the BOX layer according to , but the conventional device structure was considered in this work. S/D doping concentrations of the n-type and p-type devices are 2 × 1020 and 4 × 1020 cm−3, respectively. Interfacial layer (IL), HfO2, and low-k spacer regions have the dielectric constants of 3.9, 22.0, and 5.0, respectively. Contact resistivity at S/D and silicide interface is fixed to 10−9 Ω·cm2 . Equivalent oxide thickness (EOT) is 1.0 nm, which consists of 0.7-nm-thick IL and 1.7-nm-thick HfO2.
Table 1 shows the geometrical parameters and values of 3-nm-node FinFETs and GAAFETs. Contacted poly pitch (CPP) and fin pitch (FP) are 42 and 21 nm, following 3-nm technology node . There are two types of GAAFETs: nanowire FETs (NWFETs) having the same width and thickness as WNW, and nanosheet FETs (NSFETs) having thin NS thickness (TNS) of 5 nm but wide NS width (WNS) as 10, 20, 30, 40, and 50 nm. The number of NW or NS channels (Nch) is varied as 1, 2, 3, 4, and 5.
|CPP||Contacted poly pitch||42 nm|
|FP||Fin pitch||21 nm|
|NP||Nanowire/sheet pitch||WNW or WNS + 16 nm|
|Lg||Gate length||12 nm|
|Lsp||Spacer length||5 nm|
|Wfin||Fin width||5 nm|
|Hfin||Fin height||46 nm|
|WNW||Nanowire width||5, 6, 7, 8, 9, 10 nm|
|WNS||Nanosheet width||10, 20, 30, 40, 50 nm|
|TNS||Nanosheet thickness||5 nm|
|TSP||Nanowire/sheet spacing||10 nm|
|Nch||The number of channels||1, 2, 3, 4, 5|
Figure 2 shows the schematic process flows of GAAFETs. The detailed gate-las process flows are described in . After depositing Si0.7Ge0.3/Si multi-layer and etching like fin structure, poly-Si gate and low-k regions are formed. Inner-spacer is formed by etching sidewalls of Si0.7Ge0.3 regions selectively and depositing low-k regions. Followed by depositing BOX layer, selective epitaxial growth of S/D regions is performed. After removing poly-Si gate, channel release process is performed by etching Si0.7Ge0.3 regions selectively. Replacement metal gate, silicidation, and metal contact formations are done afterwards.
All the TCAD results were calibrated to Intel 10-nm node FinFETs . Detailed calibration flows are as follows. Geometrical parameters such as Lg, fin width (Wfin), fin height (Hfin), CPP, and FP were referred from . Subthreshold characteristics such as subthreshold swing (SS) and drain-induced barrier lowering (DIBL) were fitted by changing annealing temperature and time for proper S/D doping profiles. Saturation velocity was tuned to fit the drain current (Ids) in the saturation region, whereas minimum low-field mobility and ballistic coefficient were varied to fit the Ids in the linear region. Some parameters related to surface roughness scatterings were also modified to fit the Ids in the strong inversion region accordingly. These calibration flows were equivalent as in . After calibration, FinFETs were scaled down to the 3-nm node for comparison with GAAFETs.
3. Results and discussion
3.1 DC performances of NWFETs and NSFETs
Figure 3 shows the Ids of all the GAAFETs having different WNW or WNS at the fixed Nch of 3 at the drain voltages (Vds) of 0.70 V. It is not shown in this figure, but the Ids increases generally as the WNW or WNS increases irrespective of Nch. As the WNW increases, the Ids shifts leftward and the gate-induced drain leakage (GIDL) increases by losing the gate-to-channel controllability . P-type NWFETs have larger GIDL than n-type NWFETs due to larger S/D doping penetrations into the channel for p-type devices. On the other hand, NSFETs have small GIDL and Ids shifts as thin TNS of 5 nm forms 1-D structural confinement and maintains good short channel characteristics. To the following, there are three applications at different off-state currents (Ioff): LP at the Ioff of 100 pA/μm, SP at the Ioff of 10 nA/μm, and HP at the Ioff of 100 nA/μm . These values were normalized to NP.
Figure 4 shows SS and DIBL of all the devices. Threshold voltages (Vth) and SS are extracted at the constant current of Weff/Lg × 108 A, where Weff is the effective width equal to 2 × Hfin + Wfin for FinFETs, 4 × WNW × Nch for NWFETs, and (2 × WNS + 2 × TNS) × Nch for NSFETs. DIBL is calculated as the difference of the Vth at two different Vds of 0.05 and 0.70 V for n-type (−0.05 and − 0.70 V for p-type) devices . NWFETs degrade the short channel characteristics much than FinFETs as the WNW is 9 and 10 nm. NSFETs, on the other hand, have smaller SS and DIBL than FinFETs even as the WNS increases up to 50 nm because the gate-to-channel controllability is maintained by GAA structure and thin TNS of 5 nm. But when the NWFETs have ultra-small WNS of 5 or 6 nm, 2-D structural confinement decreases the SS and DIBL greatly, which would be preferable for LP applications. It is not shown in this figure, but the SS and DIBL are independent of Nch.
Figure 5 summarizes the effective currents (Ieff) of n-type (top) and p-type (bottom) GAAFETs having different WNW (or WNS) and Nch. Ieff was calculated using two Ids at different Vds and gate voltages (Vgs) as
where IH = Ids (Vgs = VDD, Vds = VDD/2) and IL = Ids (Vgs = VDD/2, Vds = VDD) , and VDD is the operation voltage fixed to 0.7 V. All the Ieff were normalized to the NP, and the Ioff were fixed to 10 nA/μm for SP applications. GAAFETs need to have at least the Nch of 3 to outperform the FinFETs. As the WNW is 9 nm, both n-type and p-type NWFETs suffer from short channel effects (SCEs) and thus have smaller Ieff than the devices having smaller WNW in spite of larger Weff. NSFETs, on the other hand, have larger Ieff as the WNS is larger as the SCEs are reduced by thin TNS of 5 nm. But even though small same SS and DIBL are maintained for all the Nch, the increasing rate of Ieff as a function of Nch decreases as Nch increases.
Figure 6 shows the S/D parasitic resistance (Rsd) of the GAAFETs having the WNW or 7 nm and the WNS of 30 nm as a function of Nch. Other WNW and WNS have the same Rsd trends and thus are not shown in this work. Rsd was possibly extracted using Y-function method due to the linearity of Y-function at high Vgs . As the Nch increases, Rsd of the GAAFETs decrease but at decreasing rate. Furthermore, Rsd becomes saturated as the Nch is 3 or 4. This phenomena can be explained by 2-D schematic diagrams shown in the right of Figure 6. Since the S/D contacts reside at the top of the S/D epi, current paths start from the top toward the channels at the bottom. As the Nch increases, longer current paths are needed to flow the bottom-side channels, facing more Rsd components at the S/D epi. Thus, increasing the Nch beyond 3 or 4 does not help DC performance improvements greatly.
3.2 AC performances of NWFETs and NSFETs
Figure 7 summarizes the gate capacitances (Cgg) of all the GAAFETs. The Cgg is extracted at the Vgs and the Vds of VDD. Generally, Cgg increases as the WNW (or WNS) or Nch increases due to the increased Weff. PFETs have larger Cgg than NFETs due to larger S/D doping concentrations and penetrations into the channels. Different from the Ieff trends, the GAAFETs have Nch smaller than 3 to outperform the FinFETs, thus there are performance trade-offs between Ieff and Cgg as a function of Nch. Furthermore, the increasing rate of Cgg as a function of Nch is constant while the increasing rate of Ieff as a function of Nch decreases, which would degrade the RC delay (= IeffVDD/Cgg) as the Nch increases.
Figure 8 shows the Cgg and parasitic capacitances (Cpara) of the GAAFETs varying Nch and WNW (or WNS). Cpara is extracted at off-state for SP applications. For all the cases, PFETs have larger Cpara than NFETs due to larger S/D doping and penetrations into the channels . At the fixed Nch of 3, larger WNW or WNS, except for p-type NWFETs, decreases the Cpara/Cgg because the proportion of the channels out of the metal gate increases. For the same reason, larger Nch decreases the Cpara/Cgg. Large Cpara/Cgg at the WNW of 9 nm for NFETs is because large SS forms on state before reaching strong inversion region.
Figure 9 shows the S/D doping profiles of NFETs (top) and PFETs (bottom) having different WNW at the fixed Nch of 3. In general, NFETs have larger doping concentrations in the middle of channels than PFETs because the Ge intermixing within multi-stacked Si/Si0.7Ge0.3 layers increases the Ge concentration at the channels and assists more phosphorus dopants diffusing into the channels while it segregates boron dopants [32, 33, 34]. Both NFETs and PFETs increase the doping concentrations in the middle of channels as the WNW increases because the dopant segregations near the low-k spacer regions decrease . But PFETs increase the doping concentrations in the middle of channels much due to smaller Ge intermixing for larger WNW. This great increase of the doping concentrations in the middle of channels increases the Cpara/Cgg for p-type NWFETs (as shown in Figure 8).
Figure 10 finalizes the RC delay of all the GAAFETs for LP, SP, and HP applications. N-type FinFETs have smaller RC delay than p-type FinFETs for all the applications due to better short channel characteristics, greater Ieff (as shown in Figure 5) and smaller Cgg (as shown in Figure 8). For LP applications, n-type GAAFETs having small WNW equal to 5 or 6 nm can outperform n-type FinFETs by decreasing SS and DIBL critically. But as the Nch is 1 (or 5), the Ieff decreases greatly (or the Cgg increases greatly), thus degrading the RC delay. On the other hand, p-type GAAFETs have more WNW or WNS options to outperform p-type FinFETs because boron dopants of the GAAFETs are segregated by Si/Si0.7Ge0.3 intermixing and have more abrupt S/D doping profile than p-type FinFETs. For LP applications, both n- and p-type GAAFETs have the minimum RC delay at the WNW of 5 nm and the Nch of 4. For both SP and HP applications, both n- and p-type GAAFETs have the minimum RC delay at the WNS of 50 nm and the Nch of 3. As the WNS increases beyond 50 nm, RC delay decrease but a little (as shown in Appendix). All these RC delay are achieved by enhancing the Ieff rather than the Cgg. To outperform the FinFETs, therefore, GAAFETs should be NWFETs, showing outstanding short channel characteristics, for LP applications and NSFETs, showing superior DC performance, for SP and HP applications.
3-nm-node GAAFETs have been analyzed by changing WNW (or WNS) and Nch using fully-calibrated TCAD. Compared to FinFETs, GAAFETs have smaller and SS and DIBL as the WNW is smaller than 9 nm but irrespective of the WNS. Both Ieff and Cgg of the GAAFETs increase as the Nch increases, but the increasing rate of Ieff decreases due to the increase of Rsd at the longer S/D epi. The increasing rate of Cgg, on the other hand, is almost constant. Because of these phenomena, Minimum RC delay are formed at the middle Nch of 3 or 4. The NWFETs having the WNW of 5 or 6 nm achieve smaller RC delay than the FinFETs by achieving better gate electronics for LP applications, whereas the NSFETs having the WNS of 40 or 50 nm increase the Ieff greatly and thus decrease the RC delay for SP and HP applications. Overall, GAAFETs are possible candidates to substitute FinFETs in the 3-nm technology node for all the applications by adopting different WNW or WNS.
Conflict of interest
The authors declare no conflict of interests.
Appendices and Nomenclature
Figure A1 shows the DC/AC performances of the NSFETs as the WNS increases from 40 to 100 nm. Minimum RC delay are formed at the WNS of 50 nm and the Nch of 3 as shown in Figure 10, but much smaller RC delay can be attained as the WNS increases to 100 nm by increasing the Ieff rather than the Cgg even though larger WNS extends the device area. For the most, RC delay decrease by 5.4% for PFETs as the WNS increases from 40 to 100 nm.