In a modern mobile satellite communication (SATCOM) system, a ground terminal receiver receives a radio frequency signal that is demodulated to generate a baseband digital signal waveform containing a self-clocking bit stream of digital data. The received baseband digital signal waveform is recovered and tracked using a timing recovery loop (TRL). The traditional TRLs use early-and-late gates, digital transition tracking, filter-and-square, and delay-and-multiply functions. In bit timing detection, the bit stream is self-clocking and the timing differential dithers about correct bit timing in the TRLs. For mobile satellite communication environments, the traditional TRLs drop lock when the loop signal-to-noise ratio (SNR) is smaller than a threshold value or the residual Doppler frequency is larger than the operating loop bandwidth. After dropping lock, the traditional TRLs experience long hang up time due to the need to reacquire the timing pulses. Recently, random walk filters (RWF) have been adapted to improve the bit clock locking stability and are applied to recover bit timing information of a digital data stream. This chapter describes random walk model for timing jitter and discusses how RWF solution can address the timing recovery challenges in mobile satellite communication environments.
- random walk filter (RWF)
- timing recovery loop (TRL)
- Mobile communication
- bit clock
- phase-locked loop (PLL)
- square-TRL (STRL)
- 8PSK transmitter/receiver
1. Background and introduction
For mobile environments, current TRLs use traditional TRLs that drop lock at low signal-to-noise ratio (SNR); then, experience long hang up time while reacquiring timing pulses. A potential solution is to introduce RWF into the TRL to reduce drops, and also to shorten reacquisition time. This chapter focuses on random walk model for timing jitter and TRL using RWF .
A mobile SATCOM system includes a mobile transmitter, a satellite transponder and a ground terminal receiver as shown in Figure 1. The ground terminal receiver receives an RF signal and demodulates the RF signal to generate a baseband (BB) signal waveform containing a self-clocking binary bit stream of digital data. The generated BB signal waveform is tracked by a TRL. The TRL tracks bit timing of the BB signal waveform and generates timing pulses. The timing pulses are then used in a receiver’s data detector for sampling the BB signal waveform at the bit intervals, Tb’s, for reconstructing the digital bit stream from the received BB signal waveform. The received BB signal waveform is normally distorted by channel noise causing poorly generated timing pulses and hence poor bit timing recovery leading to poor data bit detection and Bit Error Rate (BER) performance, and hence Symbol Error Rate1 (SER) degradation. When the TRL loses track, the received binary bit stream is no longer detected. In current communication systems, the received binary bit stream is recovered using traditional TRLs that are subject to bit timing lock drop in the presence of channel noise and fading effects in mobile environment.
The traditional TRLs use Early-and-Late Gates (ELG), Digital Transition Tracking (DTT), Filter-and-Square (FaS), and Delay and-Multiply (DaM) techniques [2, 3, 4, 5, 6, 7, 8, 9, 10, 11]. In bit timing detection, the binary bit stream is self-clocking and the timing differential dithers about correct bit timing in the TRLs. For mobile environments (see Figure 1), these TRLs drop lock when the timing Loop Signal-to-Noise Ratio (LSNR) is smaller than a threshold value or the residual Doppler frequency is larger than the operating loop bandwidth. After dropping lock, the traditional TRLs experience long hang up time due to the need to reacquire the timing pulses. RWFs have been used for decades in various applications [3, 4, 5, 6, 7, 8, 9, 10, 11].
In the past, RWFs have been applied to digital phase synchronization systems. RWFs have been theoretically applied to carrier phase detection where differentials between local references and transmitter carriers results in a phase correction that is unidirectional and constantly circular over 360 degrees [3, 4, 5, 6]. Although used for decades, RWFs have not been adapted to improving the bit clock locking stability in TRLs. This chapter discusses the RWF based on the Brownian motion process for recovering bit timing information of a binary data stream. The chapter is organized as follow:
Section 2 presents related works, including PLL modeling using random walk theory2, Cramér–Rao bound, Square-TRL Using Digital RWF and Advanced TRL Using RWF.
Section 3 discusses mathematical modeling of timing jitter using random walk process and Cramér–Rao bound for timing jitter.
Section 4 describes in detail the TRL using RWF, including software implementation and performance of RWF-TRL for 8-PSK communication system.
Section 5 discusses the results and provides a conclusion of the chapter.
2. Related works
Section 2 describes existing publications related to RWF concept. Section 2.1 presents works related to performance modeling of PLL using random walk theory, Section 2.2 describes the Cramer-Rao Lower Bound that can be used to evaluate the best TRL performance in terms of variance, Section 2.3 discusses the operation and performance of square-TRL using digital RWF and Section 2.4 describes an advanced TRL using RWF approach.
2.1 Performance modeling of PLL using random walk theory
This subsection describes the use of random walk theory on the modeling of all digital PLL, the first-order Bang-Bang PLL and approximation of PLL phase error variance.
2.1.1 The all-digital phase-locked loop
One of the first uses of Random Walk Theory on modeling of phase-locked loop (PLL) was from  where the performance of an All-Digital PLL (ADPLL) was analyzed. Here a simple ADPLL for a Non-Return-to-Zero (NRZ) square wave input waveform is shown below in Figure 2, with an application to track the sub-carrier frequency for a satellite command system.
In this figure, the square wave signal y(t) is first low pass filtered with a bandwidth of W. The Analog-to-Digital Converter (ADC) will sample at Nyquist rate of 2 W so that there will be 2 W/fs per period where fs is the square wave frequency. The phase detector block consists of two elements: (1) the Transition Sampler Selector (TSS) which will output ±A at each square wave transition, since the sampling error shown as the interval τ seconds can cause the TSS output to be +A or −A depending on where τ is; and (2) an accumulator that will sum m transition samples. Following the Phase Detector, the Sign Detector will be used to add or delete one or more clock pulses, in effect shifting the sampling location of the square wave by a multiple of Δ defined as a fraction of the square wave period. The divide-by-R operation will convert the clock rate back to the ADC sample rate (R = fc/2 W) where fc is the clock frequency.
In the presence of white noise with power density N0 Watt/Hz, the clock errors normalized to Δ can take on values from −N, −(N − 1), …, −2, −1, 1, 2, …, (N − 1), N with corresponding transition probabilities. This error model forms a discrete parameter Markov chain with countable number of states, and there are 2N = 1/Δ in one square wave period. The state-transition diagram can be further reduced to N total error states from 2N, by noting that the pairs of states −1 and 1, and −2 and 2, etc., contribute the same squared error. In addition, the transition probabilities are state independent since the square wave amplitude is constant for every state. This independent homogeneous finite aperiodic Markov chain is shown in Figure 3.
The above Markov chain is referred to as a “random walk” with the transition probabilities q and p defined in Eq. (1) and (2), respectively, and in terms of signal and noise parameters as shown in Eq. (3):
Where the parameter is the SNR and the erf(.) is defined as in Eq. (4):
For this ADPLL, there are three major performance analysis results using the random walk model: the steady-state probabilities, timing error variance, and mean first slip time.
The steady-state probabilities Pk is defined as the probability that the PLL starting in state j is in state k when the number of updates goes to infinity. The expression for Pk is shown in Eq. (5),
The timing error variance also has a closed form expression by letting α = q/p,
It is observed from Eq. (6) that as SNR increases, the timing error converges to for each value of Δ.
Since it’s desirable to keep the timing error small at all times, a useful performance metrics is the Mean First Slip Time (MFST) which is defined as the expected time for the timing error to exceed some magnitude (usually π or 2π) for the first time when slipping from states ±1 to ± (N + 1). A closed form expression for this metric is shown in Eq. (7) below.
2.1.2 The first-order bang-bang PLL
The Bang-Bang Phase-Locked Loop (BBPLL) has been widely used for Clock and Data Recovery (CDR) in serial data links and in digital frequency synthesis . A common feature in BBPLL is the Binary Phase Detector (BPD) that quantizes the phase difference between the input data and Voltage-Controlled Oscillator (VCO) clock by generating the early/late phase error information for the Loop Filter (LF). A model for the first-order bang-bang PLL is shown in Figure 4(a) where the BPD is represented as a sampler with input as a reference clock and sampled by a VCO. The BBPLL operation in the phase-domain can be summarized by the discrete-time model in Figure 4(b).
In above figures, the behavior of the phase error can be described by the stochastic difference equation shown in Eq. (8) below:
and corresponding timing jitter is defined as in Eq. (9):
is the period deviation due to frequency offset3, K is the bang-bang phase step, and is a sequence of zero-mean independent and identically distributed (i.i.d.) random variables (RVs). This follows a random walk (RW) model starting at some origin (n = 0) with being the step RV with a distribution F. This RW model is sign dependent since the next step depends on the sign of the current state, thus called Sign-Dependent Random Walk (SDRW) model. Furthermore, if we assume that and are Gaussian RVs with variance then the timing jitter process can be viewed as Sign-Dependent Gaussian Random walk (SDGRW).
PLL design questions are often centered around how much jitter is transferred from the reference clock, how much jitter is generated by the loop itself, and what is the minimum Root Mean Square (RMS) timing jitter. The first two can be answered by examining the static timing offset error derived in . A static timing offset is a significant problem in a BBPLL-based CDR circuit because it results in the incoming data no longer sampled at the center of the data eye, thus increasing the bit error rate. A closed form expression for static timing offset error is shown in Eq. (10) below.
As shown in Eq. (10), the behavior of the static timing offset error vs. frequency offset at K = 1 can be determined by setting and letting to be larger than 1, the combined effect of frequency offset and clock jitter causes the static timing offset to increase from its jitter-free level. But by setting and letting be much less than 1, the static timing offset does not notably increase for a small enough , even with a moderate frequency offset.
The plot of the timing jitter error standard deviation for various values of timing jitter noise and frequency offsets can be generated using Eq. (13) as shown in Figure 5. For small jitter noise, the hunting jitter dominates so RMS timing jitter error is approximately constant and approaching an asymptote. Increasing jitter noise causes RMS timing jitter error to rise because the effect of the Gaussian clock jitter and the resulting overload jitter becomes gradually apparent. For large jitter noise, overload jitter dominates, and shows a linear increase on the logarithmic scale.
Finally, an important parameter is the optimal bang-bang phase step K to achieve a minimum timing jitter variance. The expression for the optimum phase step is:
2.1.3 Approximation of PLL phase-error variance
Approximations for the expression of phase error variance due to nonwhite frequency noise with finite loop propagation delay have been created by Norimatsu and Ishida . The PLL phase error is expressed as a summation of the phase error variance due to phase noise, , and the phase error variance due to shot noise given by :
Where is the double-sided power spectral density (PSD) of the phase noise, H(f) is the closed loop transfer function of the PLL, e [A sec] is the electron charge, [W] is the received optical power, R [A/W] is the photon detector responsivity, M is 4 for BPSK homodyne detection and 2 for other schemes and is the optical power splitting ratio to the quadrature-arm.
2.2 Cramér–Rao bound (CRB)
In information theory and statistical analysis, the Cramer-Rao Lower Bound (CRLB) is often used to evaluate the best performance in terms of variance of any unbiased parameter estimator, whether the parameter to be estimated is random or deterministic but unknown. An unbiased estimator that achieves this lower bound is said to be statistically efficient, achieves the lowest possible mean squared error among all unbiased methods and is therefore called the minimum variance unbiased estimator (MVUE). However, there is no guarantee that an estimator exists that will achieve the CRLB. This may occur if an estimator exists, but its variance is strictly greater than the CRLB.
Given that is the multiple-parameter estimator of based on the observation data vector , the CRLB for this problem is given by Eq. (18):
Where is the “total” Fisher Information Matrix (FIM), defined by:
Where is the joint probability density function (pdf) of . The estimation error variance of each estimate of can be taken from the diagonal term of the matrix. Since where is the conditional pdf of given , and is the a-priori pdf of . So the total FIM can be separated into two distinct parts representing deterministic and random parts for each type of estimator is shown in Eq. (20):
Where the deterministic FIM part is:
and the a-priori FIM for the random parameter estimator is:
For each problem, the appropriate FIM will need to be calculated accordingly. The inversion of the composite FIM will result in the CRLB.
2.3 Square-TRL using digital RWF
Digital filter with Square-TRL (DF-STRL) has been proposed and discussed in . Due to its simplicity and hang-up-free filtering features, DF-STRL has been used by satellite ground terminals for Pulse Amplitude Modulation (PAM), Quadrature Amplitude Modulation (QAM) and Phase Shift-Keying (PSK) waveforms operating at high data rates. A typical DF-STRL architecture is shown in Figure 6, where the integer N is selected to be 4.
If one assumes that the mean of the timing estimate is zero, the timing jitter (or timing variance of the timing estimate), , is defined as:
Reference 6 shows that the timing jitter, , for DF-STRL consists of three components, namely
Timing jitter generated by (Signal x Signal)–This term is referred to as self-noise term:
Timing jitter generated by (Signal x Noise)–This term is referred to as Squaring Loss (SL) term:
Timing jitter generated by (Noise x Noise):
Mathematically, the timing jitter, , for DF-STRL can be expressed as:
Analysis shown in  showed that the timing estimate is un-biased, which means that the average coincides with . The estimation accuracy depends on several loop parameters, including Symbol SNR, observation interval and the pulse shaping filter g(t). The timing jitter in Eq. (24) can be put in the form (, Section 7.6.2):
where T is the symbol duration, is the symbol SNR, and and are the coefficients depending on the symbol alphabet and the pulse shaping filter g(t). The pulse shaping filter g(t) is usually Root-Raised-Cosine filter with roll-off α.
2.4 Advanced TRL using RWF
Recently, a small team of Aerospace engineers developed an innovative approach to recover the timing information from a received binary data stream . The proposed approach uses:
A “RWF counter” for counting early, nominal and late arrivals of data transition pulses of an input binary data stream
The output of the RWF provides magnitude counts that are compared to a Threshold Value (TV) that when exceeded by the magnitude counts results in a delay adjustment of the generated Adjusted Timing Pulses (ATPs)
The ATPs are eventually catching up with the actual timing clocks
When ATPs caught up, no delay adjustment will be made allowing ATPs to synchronize with the actual bit timing for maintaining bit timing lock
The ATPs are used by a data detector for reliable data detection and reconstruction of the binary bit stream.
With the proposed RWF approach, the threshold value “TV” can be adaptively adjusted for reducing drop lock rates in the presence of changing channel environments. Figure 7 illustrates the proposed RWF approach for timing recovery. Section 4 discusses in depth the proposed RWF implementation approach and presents simulation results for 8PSK Modulator-Demodulator (MODEM).
3. Mathematical modeling of timing jitter using random walk process
The Wiener process was introduced as a mathematical model of Brownian motion describing a random, but continuous motion of a particle, subjected to the influence of a large number of chaotically moving molecules of the liquid. The simplest model of Brownian motion is a simple symmetric random walk in one dimension (aka random walk) . It also has been shown that Brownian motion with zero drift is the limiting case of random walk . This section describes the mathematical random time walk model for charactering the timing jitter in an Additive White Gaussian Noisy channel and the corresponding Cramér–Rao bound for timing jitter.
3.1 Mathematical modeling of random time walk
References [3, 5] discuss a Random Time Walk (RTW) model, which can be captured in the following Figure 8. The RTW model includes a binary data stream that is independent identically distributed data symbols (−1 or 1), a timing offsets τ timing, a channel impulse response h(t), an Additive Gaussian White Noise (AWGN) source and channel output y(t).
where T is the bit period, are the N i.i.d. and equally likely data symbols, is the channel impulse response, is additive white Gaussian noise, and is the random timing offset for the l-th symbol. This timing offset model can also be expressed as:
where is the initial timing offset and zero-mean Gaussian random variable with variance , is the frequency offset parameter zero-mean Gaussian random variable with variance , characterizes a random walk and are i.i.d. zero-mean Gaussian random variables of variance which determines the severity of the random walk.
3.2 Cramér–Rao bound (CRB) for timing jitter
The RTW model described in Section 3.1 will be used for the CRLB derivation. To eliminate out-of-band noise at the receiver, the received waveform y(t) is filtered by a front-end filter with impulse response f(t) to get the waveform r(t), which will be sampled at instant kT to get baud-rate sample given by:
Where , is the vector of signal component of , and are zero-mean i.i.d. normal random variables with variance . In this timing jitter models, the random parameters to be estimated are is the vector of transmitted symbols, and is the vector of timing offsets.
For the CRLB computation, the parameter vector and . From Section 2.2,
represent the total FIM so that the joint estimation is decoupled, and to get the CRLB on timing estimation it is sufficient to evaluate and invert which is given by
Where , , and , and . The a-priori information parameters and represent the uncertainty of the initial timing offset and frequency offset, being zero would mean perfect knowledge of these two quantities which is not practical, and the estimation problem is simply that of estimating a random walk. Inverting (30) to get the CRLB for each leads to
is the stead state value of the CRLB,
The CRLB derived applies to timing recovery systems in general. In practice, timing recovery systems usually involve phase locked loops. A traditional PLL is typically used for timing recovery, and the receiver employs a timing-error detector (TED) to arrive at timing-error estimates. For simplicity, a first-order PLL is employed which updates its estimate according to
where is the PLL gain, and is the detector estimate of the estimation error. Instead of feeding the TED decisions about the received symbols, if we allow it to have access to the actual transmitted symbols, then we have a trained PLL. The performance of trained PLL gives a heuristic lower bound for the performance of receiver structures that use the PLL for timing recovery.
In Figure 9, the steady state CRB and the performance of the trained PLL are plotted for the following system parameters: , block length N = 500, and the PLL performance being averaged over 1000 trials . As seen in the figure, the performance of the PLL is a strong function of the gain parameter , and therefore it has to be optimized for each SNR. The PLL error variance is plotted for various values of . Taking the minimum of the error variance over all gives us the best performance we can expect using the trained PLL. We see that the trained PLL is about 7 dB away from the CRB. This gap of 7 dB has to be put in perspective by the fact that the CRB is not attainable in this case. For the CRB to be attainable, the a-posteriori density needs to be Gaussian, which is not the case here.
4. Timing recovery using RWF
The most commonly used TRLs in existing wireless and satellite communications systems are DF-STRL, Early-and-Late Gate, Digital Transition Tracking, and Delay-and-Multiply TRLs [6, 9, 10, 11]. For mobile environments, these TRLs drop lock when the loop signal-to-noise ratio (SNR) is smaller than the threshold value SNR or the residual Doppler frequency is larger than the operating loop bandwidth. When “dropped lock”, these timing loops experience a long “hang-up” time due to reacquisition and locking behavior of the timing clock. As discussed in Section 2.3 on the related works for DF-STRL, a form of digital RWF was proposed for use with square TRL. This DF-STRL suffers squaring loss caused by squaring mechanism used by the loop. This section explores the advanced TRL using RWF.
4.1 RWF concept for timing recovery
The RWF-TRL concept derived from the following principles:
Principle 1: Input binary signal waveform is compared in time with locally generated and suitably delayed timing pulses to produce lead/lag signals to increment/decrement a timing counter.
Principles 2: When timing counter output exceeds a positive or negative threshold, the delay for timing pulses is adjusted accordingly.
Principle 3: Without timing errors, an appropriately selected threshold value allows the lead and lag signals to cancel out in time, thus retaining the correct timing pulses.
The block diagram, shown in Figure 10, describes the above principles pictorially. The received binary data is a square wave with amplitude varying between +1 and −1 with time duration T in second, which is inversely proportional to the communication data bit rate R in bit per second.
4.2 Software implementation of RWF TRL
The major Software Blocks (SWB) required for implementing the above three principles are:
SWB 1: Pulse detection and comparison block converts input baseband digital signal waveform to data transition pulses and compares them to timing pulses to generate lead/lag signals.
SWB 2: RWF counter block generates a running count that is incremented/decremented by the lead/lag signals.
SWB 3: Threshold comparison block generates exceedance signal when magnitude of running count is greater than a selected threshold.
SWB 4: Timing pulse delay adjustment block uses sign of running count to adjust timing pulses when triggered by exceedance signal.
Figure 11 presents a software architecture for implementation of the three principles described in Section 4.1. The threshold value is derived based on a threshold selection process that depends on the channel environment. Either a training sequence or a priori knowledge of the channel propagation conditions may be needed to set the threshold. Alternatively, an algorithm can be provided to adaptively select a threshold value to compensate for channel impairments.
Figure 12 describes the “Pulse Detection and Comparison Block”, or SWB 1. This SWB1 consists of the following functions:
Converts input baseband digital signal waveform to data transition pulses delayed by half of the search window size, W.
Generates timing pulses that are delayed by the adjusted timing pulse delay that is input to the block.
Counts number of data transition pulses that are within W from each successive timing pulse and keep track of the delay of the first data transition pulse.
Calculates lead/lag time of the first data transition pulse as the delay time minus half of the search window size, and lead/lag signal as the sign of the lead/lag time.
Outputs a non-zero lead/lag signal if there is one, and only one, data transition pulse within the search window, thus eliminating much of the noise-caused ambiguity.
4.3 Performance of RWF TRL
Signal Processing Work (SPW) implementation of the proposed RWF TRL for 8-PSK modem is described in Figure 13. The proposed implementation includes the following blocks:
8PSK transmitter block generates signals modulated by sine and cosine waveforms.
AWGN generator block adds Gaussian random noise to the 8PSK signals.
Demodulator with ideal phase tracking converts the 8PSK signals to baseband.
Combination of low pass filter (LPF) and hard-limiter generates a binary data stream from the 8PSK signals.
RWF TRL block generates clock signals (timing pulses).
Sum dump and hold block uses the clock signals to integrate the baseband 8PSK signals.
8PSK detector puts the integrated signals through 8PSK slicer to reconstruct the data stream.
SER estimator compares the original data stream with the reconstructed data stream to detect symbol errors.
SPW-simulated SER curve with imperfect timing recovery is shown in Figure 14. This SER curve was obtained under the following operational conditions, which is not optimized in terms of search window and threshold value used by the counter:
Back-to-back Modem with no transponder or amplifier in between, i.e., no Amplitude Modulation-to-Amplitude Modulation (AM-AM) and Amplitude Modulation-to-Phase Modulation (AM-PM) distortions.
Carrier frequency: 5000 Hz
Symbol rate: 1000 sps
Number of samples per symbol: 50
Search window size: 10 samples
Threshold for counter: 10 counts
where is the symbol SNR and is the Q-function given by:
As shown in Figure 14, the simulated SER curve for 8PSK with perfect phase tracking and timing recovery coincides with the theoretical SER curve for 8PSK. Simulated SER curve with imperfect timing (but perfect phase tracking) shows a symbol SNR degradation of about 0.2 dB from the theoretical curve.
5. Discussion and conclusion
Current trends in mobile communications will be impacted from operational environment, many near-by users and spectrum sharing, expanding amounts of data (such as streaming video), and increased mobility of receivers. As such, there is higher potential to drop lock, and greater impact resulting from traditional recovery times. A proposed solution is to introduce RWF into the TRL to reduce drops, and also shorten reacquisition time. Based on the RWF-TRL simulation results for 8PSK comparing to standard TRLs for similar 8PSK modem, we believe that the proposed loop has the following advantages:
Using adaptable threshold values of the RWF timing loop that is trained for specified operational environments, the “dropped lock” rate is expected to be less
Faster acquisition time due to the adaptable threshold value setting of the RWF timing loop
Can be made to be adaptive to any mobile environment using deep learning and artificial intelligent technology.
All digital and simple to implement
Expandable to accommodate a wide range of modulation schemes, namely, BPSK, QPSK, 16-QAM, 64-QAM, and possible application to continuous phase modulation, e.g., GMSK.
The authors searched for similar SER results for 8PSK Modem to compare with the simulation results presented in Section 4.3, but currently, there are no TRL using RWF available for performance comparison.
As described in Section 4, there are several features associated with RWF approach, including:
Operate at low sampling rate, which means less power consumption.
Provide excellent SER performance
Robust to mobile operational environment due to adaptable feature
Accommodate a wide range of modulation schemes
The potential markets for the proposed RWF filter approach include:
Mobile satellite industry: Mobile satellite terminals, satellite decoders, etc.
Wireless communication industry: Cellular and mobile phone industry.
The authors would like to express their appreciation to their Aerospace’s colleagues and managers for their support and encouragement during the preparation of this chapter. In particular, they want to thank Dr. James Yoh, Mr. John M. Charroux, Dr. Sumer Matsunaga, Dr. Art Dahlin and Mr. Mark Silverman.
Conflict of interest
Using the data reported in , which was performed under The Aerospace IRAD funding in early 2000’s, the authors prepared Sections 2.4 and 4 of this chapter. However, the preparation of this chapter was not funded by The Aerospace Corporation, and it was done by the authors using their own time and thus it does not represent The Aerospace Corporation’s view on the use of RWF-TRL for future mobile satellite systems.
The first author wishes to thank his wife, Thu-Hang Nguyen, for her enormous patience and boundless support during the preparation of this chapter.
- For un-coded Binary Phase Shift Keying (BPSK) the SER is identical to Bit Error Rate (BER).
- The simplest model of Brownian motion is a simple symmetric random walk
- The notation Δ T for frequency offset is not conventionally consistent but preserved from