Open access peer-reviewed chapter - ONLINE FIRST

Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications

By Mikaël Cassé and Gérard Ghibaudo

Submitted: October 15th 2020Reviewed: May 15th 2021Published: June 7th 2021

DOI: 10.5772/intechopen.98403

Downloaded: 68

Abstract

The wide range of cryogenic applications, such as spatial, high performance computing or high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperatures. In particular, the readout electronics of quantum computers operating at low temperature requires larger bandwidth than spatial applications, so that advanced CMOS node has to be considered. FDSOI technology appears as a valuable solution for co-integration between qubits and consistent engineering of control and read-out. However, there is still lack of reports on literature concerning advanced CMOS nodes behavior at deep cryogenic operation, from devices electrostatics to mismatch and self-heating, all requested for the development of robust design tools. For these reasons, this chapter presents a review of electrical characterization and modeling results recently obtained on ultra-thin film FDSOI MOSFETs down to 4.2 K.

Keywords

  • Cryogenic CMOS
  • FDSOI
  • MOSFET
  • characterization
  • modeling

1. Introduction

First MOSFET measurements at liquid Helium temperature have been reported as soon as in late 1960s [1, 2, 3], leading to some remarkable discoveries like the integer quantum Hall effect [4]. Since then, many works have been published on the electrical characteristics of MOSFETS down to 4.2 K [5, 6, 7]. The interest of operating electronic circuits at cryogenic temperatures has been demonstrated a few decades ago, and relies on the performance improvement and/or on the necessity to have electronics in cryogenic environment [5, 6, 7]. With the emerging field of quantum computing, for which read-out and control electronics of the quantum bits (qubits) is required in the proximity of the qubit itself, the study of CMOS devices at low and very low temperature, well below 100 K, has received a renewed attention [8, 9, 10]. In particular, qubit control requires high-frequency and large-bandwidth signals, as well as low-power electronics to be compatible with the cooling power of modern refrigerators [11, 12, 13, 14]. Circuits fabricated from advanced nodes CMOS are good candidates to fulfill the specifications for quantum computing applications [15, 16, 17, 18].

Key advantages of operating at low temperatures include the better electrical performance of MOSFETs, with higher carrier drift velocity and so higher on-state drain current and transconductance, steeper subthreshold slope, lower leakage current [6, 19]. Some works have studied bulk MOSFETs operation at cryogenic temperature emphasizing in particular kink behavior and freeze-out effects in those devices [7, 15, 20, 21, 22, 23, 24]. Recently, outstanding characteristics have been demonstrated at 4.2 K on advanced CMOS technologies [19, 25, 26, 27], in particular for Fully Depleted Silicon-On-Insulator (FDSOI) [28, 29, 30, 31, 32]. Ultrathin film FDSOI devices (with typically silicon thickness less than 10 nm) are immune to kink effects [33], and freeze-out has finally little impact on the DC characteristics of MOSFETs in advanced technologies [34]. Apart from the performance itself of the circuits at these low temperatures, and the figures of merit for analog or digital applications, specific attention to power dissipation has to be brought as well, as the available cooling power is limited in cryostat, and depends of the different cooling stages (typically ≈1 W at 4 K and less than 1 mW below 100mk) [11].

In that context, FDSOI technology offers a significant advantage over other available technologies, as it allows designing low power electronics, threshold voltage tunability thanks to its back bias ability, and offers low variability due to the undoped channel [35]. Extensive electrical characterization of advanced CMOS devices at deep cryogenic operation, including device electrostatics, carrier transport, mismatch and variability, or self-heating, is thus seriously needed.

Numerical issues appears with the modeling and simulation of MOSFETs at cryogenic and deep–cryogenic temperatures, in particular due to energy kBT approaching zero in equations and the extremely small intrinsic carrier density [34, 36]. Besides these difficulties, accurate models must correctly include, among other things, the temperature dependence of the main electrical parameters, such as carrier mobility, saturation velocity, threshold voltage, …, as well as thermal effects [37, 38]. On the other hand, new physical phenomena appear as the device temperature decreases that need to be characterized and properly modeled [19].

Because these aspects are essential for the development of compact models and robust design tools, this chapter presents a review of recent results obtained on 28 nm FDSOI transistors operated down to deep cryogenic temperatures. More specifically, we first discuss in Section 2 the major device electrical properties in terms of transfer characteristics and MOSFET parameters versus temperature. Then, we describe in Section 3 the self-heating phenomena, which could alter the FDSOI device performances. The matching and variability properties of scaled transistors limiting the analog applications are then addressed in Section 4. The development of compact model necessary for FDSOI circuit design at deep cryogenic temperatures is presented in Section 5. Finally, in Section 6, we illustrate the operation of elementary circuits at very low temperatures regarding inverter delay and oscillator frequency.

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2. Cryogenic FDSOI device operation

In this section, we present the measurement of the main electrical properties of FDSOI devices operating down to 4.2 K, such as the capacitance and charge control characteristics, the drain current Id(Vg) transfer curves as well as the main MOSFET parameters (threshold voltage Vth, subthreshold swing, mobility).

2.1 Devices under test

The measurements were performed on 28 nm FDSOI MOSFETs with silicon film thickness tsi = 7 nm and buried oxide (BOX) thickness tBOX = 25 nm from STMicroelectronics. NMOS and PMOS transistors were processed from (100) handle substrate, with <100> − oriented channel, and a high-κ/metal gate Gate-First architecture ( Figure 1 ) [39]. Regular-Vth (RVT) and low-Vth (LVT) transistors are available through a doped back plane (NWELL or PWELL, with typically NA,D = 1018 cm−3) below the BOX. Thin (GO1, with equivalent oxide thickness EOT = 1.1 nm) and thick oxide (GO2, EOT = 3.2 nm) devices have been characterized using a cryogenic probe station down to 4.2 K.

Figure 1.

Schematics of 28 nm FDSOI N- and PMOSFETs with regular-VTH (RVT) and low-VTH (LVT) flavors. Forward and reverse back biases (FBB and RBB) can be applied depending on the doping of the back plane.

2.2 Capacitance and charge control

The electrostatic charge control of FDSOI devices has been characterized by split C-V measurements with a conventional LCR meter. To this end, the gate-to-channel capacitance Cgc = dQi/dVg, with Qi the inversion charge in the channel, has been measured at 500 kHz frequency on large area N and P MOS devices as a function of the front gate voltage Vg with body bias Vb = 0 V for several temperatures down 4.2 K ( Figure 2 ). As can be seen, the Cgc(Vg) curves are almost temperature independent above threshold, whereas a strong improvement of the turn-on behavior is obtained at low temperature, related to the subthreshold slope increase. These characteristics have been well reproduced by Poisson-Schrodinger simulations (see Section 5.1), providing precise extraction of front oxide EOT values for GO1 and GO2 transistors [41].

Figure 2.

Cgc(Vg) characteristics (solid lines) for N- and PMOS GO1 and GO2 devices from 300 K down to 4.2 K, at VB = 0 V. the Cgc(Vg) 1D-PS modeling is shown in symbols (frequency = 1 MHz, AC level = 40 mV, W = L = 9 μm). After Cardosoet al. [40].

The influence of the AC level (Vosc) of the LCR meter oscillator used during Cgc measurements at 4.2 K has been studied and is reported in Figure 3a . Indeed, due to the strong non linearity of the Qi(Vg) curves in subthreshold region at very low temperature, the turn-on behavior of the Cgc(Vg) curve below threshold is not well captured for a too large AC level (here 40 mV, currently used at T = 300 K). However, for an AC level of 1 mV, getting closer to the thermal voltage kBT/q at 4.2 K, where kB is the Boltzmann constant and q the magnitude of the electron charge, the turn-on behavior of Cgc(Vg) below threshold is well accounted for. These results can be well modeled by integrating the ideal Cgc(Vg) curve over one period of the AC signal, providing the measured capacitance Cgc,meas as follows [42]:

Figure 3.

Experimental (a) and modeled (b) Cgc(Vg) characteristics for NMOS GO1 devices (W = L = 10 μm) at 4.2 K for two AC levels: 40 mV (red solid lines) and 1 mV (blue dashed lines).

Cgc,measVg=1Tp0TpCgcVg+δVgtdtE1

where δVg(t) = Vosc.sin(2πt/Tp) is the AC signal of period Tp ( Figure 3b ).

2.3 Drain current characteristics, threshold voltage and subthreshold slope

The Id(Vg) transfer characteristics of same devices have been measured in linear region (Vd = 50 mV) for various temperatures and are shown in Figure 4 . As usually observed in cryo-electronics for bulk CMOS devices [7], the drain current above threshold is highly increased due to mobility improvement of both electrons and holes, resulting from the suppression of phonon scattering. Similarly, the turn-on behavior of the curves below threshold is greatly improved as the temperature is lowered.

Figure 4.

Id(Vg) characteristics for GO1 N and P MOS devices for various temperatures obtained in linear region (Vd = 50 mV).

The threshold voltage Vth of the devices has been extracted by the constant current method (i.e.Vg for which Id = 10−7 × W/L) and typical variations with temperature are shown in Figure 5a . As in bulk MOS devices [7], Vth increases as the temperature is reduced, here with sensitivity around 0.7 to 1 mV/K. It should be mentioned that in FDSOI devices with undoped film as in our case, the Vth variation with T is not explained by the temperature dependence of the Fermi level in the silicon film as for bulk MOS devices [44]. Actually, a simple model for Vth read by constant current method can be derived assuming a single subband for the inversion layer with a critical inversion charge density nth as:

Figure 5.

(a) Experimental Vth extracted on NMOS GO1 transistor (W = 1 μm, L = 24 nm) as a function of T at VDS = 50 mV and 0.9 V, and at Vb = 0 V and 1.4 V. (b) Modeled Vth vs. T for Vds = 50 mV and Vb = 0 and 1.4 V. after Cardoso et al. [43].

Vth=Vsth+q.nthCox+Cb.VsthVbCoxE2

withVsth=V0+kBTq.lnenthkBT.A2D1being a threshold surface potential associated with a given constant inversion charge density nth (here 1010/cm2), and where V0 is a constant, A2D the 2D subband density of states, Cox and Cbox respectively the front gate oxide and the buried oxide capacitance and Cb = Cbox.Csi/(Csi + Cbox) the body to front channel coupling capacitance. As can be seen from Figure 5b , a good qualitative agreement between model and experiment can be achieved with Eq. (2).

An important feature of FDSOI devices is the strong Vth control allowed by the back bias, which is not possible in FinFET and NW architectures, and very limited in bulk MOS devices [7], especially in forward biasing. Typical dependence of Vth with back bias are illustrated in Figure 6 for both P and N MOS FDSOI devices of various flavors and gate oxide thicknesses (GO1 and GO2), at T = 4.2 K and T = 300 K. As can be seen from this figure, it appears that the threshold voltage control with back biasing (ΔVth/ΔVb) is insensitive to temperature down to cryogenic conditions, and that Vth can be decreased to values close to zero volt. Interestingly, this makes it possible to operate the FDSOI devices at deep cryogenic temperatures with very small supply voltage (≈0.1–0.2 V), enabling low power dissipation.

Figure 6.

Measurements of Vth vs. Vb for N- and P-type, RVT and LVT, GO1 (a) and GO2 (b) MOSFETs, at 300 K and 4.2 K, VDS = 50 mV. As T is decreased, Vb can be used to shift Vth back to its value at room temperature. After Cardoso et al. [40].

Another important parameter in FET operation is the so called subthreshold slope, S = dln(Id)/dVg, or its inverse the subthreshold swing SS, which characterizes the turn-on efficiency of the MOSFET below threshold. Typical subthreshold swing SS (mV/dec) variations with drain current in weak inversion region are shown in Figure 7a , revealing a plateau from which an average subthreshold swing can be extracted and plotted versus temperature ( Figure 7b ). Indeed, the subthreshold swing SS is varying linearly with temperature down to 25-30 K before plateauing around 10-20 mV/decade at deep cryogenic temperatures. The SS(T) linear behavior is usual for all FET devices and simply related to the Maxwell-Boltzmann statistics prevailing in weak inversion where SS = kT/q.(Cox + Cb + Cit)/Cox, Cit being the interface trap density capacitance [7]. The SS(T) plateau is generally attributed to the presence of an exponential tail of subband states, likely due to potential-fluctuations-induced disorder [46, 47, 48] and that minimizes the drain current turn-on efficiency at deep cryogenic temperatures.

Figure 7.

Extracted subthreshold currentvs. Id (a) and SS vs. T (b) for NMOS LVT from 300 K to 4.2 K. after Cardoso et al. [45].

2.4 Carrier mobility

Finally, the effective carrier mobility μeff is investigated as being a driving parameter of MOSFET in linear region. In Figure 8a and b are illustrated typical mobility variations with inversion charge Ninvas obtained by split C-V method in such FDSOI MOS devices for various temperatures. As can be seen, there is a strong improvement (up to 10 times) of the maximum mobility with temperature lowering due to phonon scattering reduction [7]. As already found for bulk Si MOSFET [7], the effective mobility exhibits a bell-shaped behavior with inversion charge at low temperature, where the mobility is limited by combined Coulomb and surface roughness scattering processes. As also shown in Figure 8 , the mobility can be well fitted by an empirical model inspired from bulk MOSFET results and written as:

Figure 8.

Experiments and analytical model of μeff vs. Ninv for NMOS GO1 (a) and GO2 (b), varying T. power law exponent (c) vs. T for N and PMOS. After Cardosoet al. [49].

μeff=μm.θ1.QiCoxn21+θ1.QiCoxn1+θ2.QiCoxnE3

where μm stands for an amplitude mobility value close to the maximum one, θ1 and θ2 are the first and second order attenuation coefficients and n is a power law exponent varying between ≈2 and ≈3 as the temperature is changed from 300 K down to 4.2 K, as illustrated in Figure 8c . It should be noted that this mobility law vs. inversion charge will be useful for compact modeling purpose (see Section 5).

As was already mentioned, a specific feature of FDSOI devices is their operation in forward back biasing condition, enabling a significant lowering of the threshold voltage as illustrated in Figure 9a for T = 4.2 K. Interestingly, for sufficiently large Vb, the drain current measured at low Vd and very low temperatures (here T = 4.2 K) is increasing above back channel threshold before to decrease significantly and then to increase again well above front channel threshold. Actually, this decrease of the drain current just happens when the front channel is opening and has been attributed to a reduction of the mobility due to remote inter-subband scattering (IS) as well explained in [50]. To better understand this behavior, we have computed the drain current of the back channel after subtraction of the front channel component, taken as being the one in absence of back channel formation i.e. when Vb = 0 V (see Figure 9b ). This assumption has been validated by Poisson-Schrodinger simulation (not shown here). Doing the same with Cgc(Vg) characteristics for various Vb’s, the inversion charge in the back channel has also been computed after integration of capacitance vs. Vg as is usual in split C-V technique ( Figure 10a ). As a result, note that the back channel charge is plateauing after the opening of front channel. The effective mobility in the back channel has been computed and plotted versus inversion charge density in the back channel or versus the front one as shown in Figure 10b and c . As can be seen, μeff first increases with the back channel inversion charge density before to decrease as the back channel charge saturates ( Figure 10b ). Instead, μeff in back channel decreases with the front channel inversion charge, which clearly indicates that the opening of the front channel is responsible for the back channel mobility decrease. This is precisely the signature of remote inter-subband scattering, which happens when carriers in the back interface 2D subband can interact with the front interface 2D subband. In this situation, some carriers at the back interface can experience scattering mechanisms in the front interface due to the overlap of the back and front subband wave functions. It should be mentioned that this phenomenon of inter-subband scattering is canceling out when the temperature is increased (T > 50 K) due to thermal broadening as well as when the drain voltage is increased due to the averaging over the channel of the conductance by integration over space [50].

Figure 9.

a) Id(Vg) characteristics at 4.2 K for various Vb (= 0, 2 V, 4 V) and b) Back channel Id(Vg) curves after subtraction of front channel component also shown in green dashed line.

Figure 10.

a) Ninv vs. Vg for Back channel for Vb = 2 V, 4 V. Green curve shows Ninv(Vg) for front channel at Vb = 0. b) Back channel μeff vs. back channel Ninv and c) Back channel μeff vs. front channel Ninv for Vb = 2 V, 4 V. Green curves show front channel μeff vs. front channel Ninv at Vb = 0 V.

3. Self-heating phenomena

In FDSOI devices or multi-gate field effect transistors like FinFETs and nanowire FETs, low thermally conductive materials such as the buried oxide (BOX) or the thin Si layer constituting the channel hinder the dissipation of the heat generated in the drain side. Consequently, the channel temperature can significantly rise when the device is in ON operation. This self-heating effect (SHE) can in turn severely affect the device performance, by reducing the carrier mobility, shifting the threshold voltage [51] or degrading the device reliability [52, 53], with implications to IC design. SHE has been widely studied for room temperature operation of circuits [54]. The thermal effects play a more fundamental role in cryogenic electronics – operating at various temperature stages with different available cooling powers –, as the temperature increase due to SH can be of the same order or even higher than the ambient temperature [55]. Furthermore, at very low temperature (well below 1 K), the cooling power drops down drastically (typically, 1 W at 1 K, 1 mW at 100mK) and thermal management thus becomes an additional constraint.

In this regard, the study of self-heating effects at cryogenic temperatures provides valuable information for performance optimization. In addition, to be accurate at cryogenic temperatures, models must take into account these thermal effects, as the device temperature can deviate significantly from the ambient one.

3.1 Self-heating characterization technique

The experimental evaluation of self-heating was performed by using the conventional DC technique based on gate resistance thermometry [56]. In this method, the gate dielectric layer is thin enough to assume that the temperature of the channel is equal to that of the gate electrode. Inset of Figure 11 shows the typical 2-terminal gate structure that we used to measure the gate resistance RG. RG is measured between two contacts G1 and G2 using an LCR-meter. By varying the ambient temperature Tamb from 4.2 K up to 300 K, we record the change in the electrical gate resistance as a function of the input power P = IDS × VDS. The temperature increase ΔT is deduced from RG values at zero power (and so without SHE). Then the differential thermal resistance, RTH * = ∂ΔT/∂P|Tamb can be defined. This differential thermal resistance relates the change of ΔT due to a change in power dissipation P at a given Tamb [55].

Figure 11.

(symbols) Differential thermal resistance RTH * measured as a function of the device temperature Tdevice = Tamb + ΔT from 450 K down to 4.2 K, with a corresponding numerical fitting curve (line).

3.2 Study of thermal resistance

In Figure 11 we have plotted the differential thermal resistance measured on an ultrathin film FDSOI transistor (tSi = 11 nm) as a function of the device temperature defined as Tdevice = Tamb + ΔT. All the RTH * data acquired for various ambient temperatures and dissipated power values merge into a single RTH * versus Tdevice curve, which thus provides a complete description of the temperature dependence of the thermal resistance for a given device. The thermal resistance depends mainly on the device geometry W and L, as well as on the BOX thickness, but not significantly on the Si film thickness in the 7 nm to 24 nm range typical of FDSOI devices ( Figure 12 ) [55].

Figure 12.

Thermal resistance RTH * versus device temperature, for wide and ultrathin FDSOI MOSFETs. After Triantopouloset al. [55].

Our results show that in thin film devices, the thermal resistance RTH * of the device is strongly temperature dependent, especially at very low temperature, as illustrated in Figures 11 and 12 . As the device temperature decreases from 300 K down to 4 K, RTH * is multiplied by 3 to 6. In FDSOI devices, the BOX tends to confine the heat in the channel, and therefore the total thermal resistance depends on both the thermal conductivity of Si and SiO2, which have different temperature dependence and magnitude ( Figure 13 ). RTH* follows the temperature dependence of the inverse of the silicon dioxide thermal conductivity in the whole range of explored temperatures [57].

Figure 13.

Thermal conductivity data versus temperature for bulk and Si-layer compared to that for bulk and SiO2-layer. After Triantopouloset al. [55].

Besides considerations over the dominant thermal path in the device, the RTH* vs. Tdevice plot can be used into thermal model in order to reconstruct the channel temperature increase ΔT as a function of operating ambient temperature Tamb and input power P using the following expression,

P=0TdTRTHTamb+TE4

Substituting a given analytical expression of RTH *(Tdevice) in Eq. (4) the value of ΔT at each Tamb and for each value of dissipated power can be calculated ( Figure 14 ). This leads in particular to a nonlinear temperature increase of the device with the dissipated power. In this specific low temperature environment, the device temperature can significantly increase and thus highly deviate from the ambient temperature, depending on the applied gate and drain voltages, as illustrated in Figures 15 and 16 .

Figure 14.

Calculated channel temperature increase ΔT (line) as a function of the dissipated power P usingEq. (4)and a fitting expression for RTH*(Tdev). Experimental data (symbols) are also shown for a direct comparison. After Triantopouloset al. [55].

Figure 15.

(a) IDS vs. VGS measured on NMOS at Tamb = 4.2 K and VDS = 0.9 V for different gate lengths, and (b) corresponding device temperature, Tdev vs. VGS.

Figure 16.

(a) IDS vs. VDS measured at Tamb = 4.2 K on NMOS with L = 60 nm for different VGS values, and (b) corresponding Tdev. Vs. VDS.

4. Mismatch and variability properties

The device mismatch is a key property to be known for the development of transistor compact models and the design of electronic circuits [58, 59, 60]. This section presents variability results obtained on FDSOI MOSFETs down to 4.2 K. To this end, an integrated on-chip matrix of individually addressable transistors has been used to increase the sample size statistics.

4.1 Devices under test

The measurements were performed on both N- and P-type transistors fabricated using the same 28 nm FDSOI technology as those described in Section 2.1. In order to provide statistical analysis on variability and mismatch at low temperature, matrices of transistors were produced with integrated addressability in an approach similar to [61]. An automated measurement system was implemented thanks to the on-chip multiplexed arrangement. The device chips were wire-bonded on a chip carrier connected to a printed circuit board (PCB) and mounted on a dipstick to reach 4.2 K in a liquid helium bath. Each die comprises 512 matched pairs of MOSFETs (256 pairs of RVT plus 256 pairs of LVT) addressable through 10-bits selection (210 = 1024 transistors).

4.2 Threshold voltage variability

Figure 17 shows typical drain current Id(Vg) characteristics for short channel N-type MOS transistors, at 300 K and at 4.2 K. Twenty four devices were measured for each MOS type at low drain voltage (|Vd| = 50 mV) to illustrate device variability. In Figure 18 the logarithmic scaled Id(Vg) emphasizes the subthreshold oscillation variability at low and high drain voltage (Vd = 50 mV and 0.9 V), at 4.2 K. The oscillations observed in the subthreshold current are a known signature of short channel MOSFETs operating at deep cryogenic temperatures, and could result from the presence of impurities in the channel [63, 64]. The threshold voltage was extracted following the constant current criterion, at Id = 10−7 W/L (A). Such current level represents the standard value used for Vth extraction, and it is well above the region where the oscillations are mainly identified, as highlighted in Figure 18 by a dashed line.

Figure 17.

Id(Vg) curves for 24 short channel (L = 28 nm) N-type LVT MOSFETs at 4.2 K and 300 K, at Vd = 50 mV. After Cardoso et al. [62].

Figure 18.

Id(Vg) curves for 24 short channel (L = 28 nm) N-type LVT MOSFETs at 4.2 K, at Vd = 50 mV and 0.9 V. after Cardoso et al. [62].

Figure 19 shows the Pelgrom plots of the standard deviation of ∆Vth, σΔVT, for NMOS devices (similar results have been obtained for PMOS). It can be seen that σΔVT well follows the area scaling linear dependence with respect to 1/W.Lat 4.2 K, as it is the case at 300 K, for all channel dimensions explored in this study (1 μm ≤ L ≤ 28 nm, 80 nm ≤ W ≤ 25 μm). This result does not reveal any specific variation with channel width and channel length due to e.g. line edge roughness (LER) for such geometries. From 300 K to 4.2 K, the extracted linear slopes, ΔσΔVT/Δ(1/W.L), indicates that the threshold voltage mismatch performance degrades by ≈25% for NMOS and PMOS, at |Vd| = 50 mV, when temperature is decreased from 300 K down to 4.2 K. Since the metal gate granularity and the local charges in the gate dielectric are the main sources of threshold voltage variability in FDSOI technology [65], the slight increase of σΔVT at 4.2 K may likely be attributed to the increase of interface charge density [63]. Moreover, in Figure 19 , it can be seen that short channel MOSFETs (L = 28 nm) exhibit higher threshold voltage variability at high drain bias (Vd = 0.9 V), which could be due to Drain Induced Barrier Lowering (DIBL).

Figure 19.

Pelgrom plot of threshold voltage variability σΔVT for NMOS at Vd = 50 mV and 0.9 V, 4.2 K (left) and 300 K (right). After Cardoso et al. [62].

Figure 20 shows the threshold voltage individual mismatch parameter, AΔVT = σΔVT .W.L, plotted as a function of 1/W.L, for 28 nm FDSOI transistors studied in this work and 40 nm bulk MOSFETs from [61], at 300 K and 4.2 K. Despite AΔVT degradation at low temperature, FDSOI remains highly competitive compared to bulk technology, mainly due to the suppression of random dopant fluctuation (RDF) induced variability in FDSOI. In Figure 20 , it can also be observed that AΔVT does not exhibit higher values for the short channel MOSFETs (i.e. high 1/W.Lvalues), for which subthreshold oscillations have been observed at low temperature ( Figure 18 ). This means that such oscillations do not have a significant impact on the threshold voltage variability, mainly because they occur below the drain current level where the threshold voltage is extracted, as discussed before.

Figure 20.

AΔVT versus 1/W.Lfor NMOS, at Vd = 50 mV, 4.2 K and 300 K. dashed lines indicate the extracted linear slope values from the Pelgrom plots. Dotted lines show typical 40 nm bulk CMOS technology data [61]. After Cardosoet al. [62].

4.3 Drain current variability

The drain current variability, σ(ΔId/Id), has also been directly measured on the 28 nm FDSOI transistors studied here and their variations with gate voltage overdrive are shown in Figure 21 for 300 K and 4.2 K. As is usual, σ(ΔId/Id) is maximized below threshold before to decrease in strong inversion, where it might slightly increase again due to the contribution of access resistance Rs variability [66]. Actually, these variations can be very well fitted by the model of Eq. (5) developed for room temperature:

Figure 21.

Measured and modeled σ(ΔId/Id) variations with Vgt = Vg-Vth. σΔRs varies from 0 to 8% of Rs = 377 Ω.μm (T = 300 K) and 266 Ω.μm (T = 4.2 K). After Cardosoet al. [45].

σIdId2=gmId2.σVT2+1gd.Rs2.σβ/β2+gd2.σRs2E5

where gm is the transconductance and gd is the output conductance. In this model, the drain current variability is controlled by three matching parameters related respectively to the threshold voltage, σΔVT, the gain factor σ∆β/β (β = W/L.Cox0, with μ0 being the low-field carrier mobility) and to the access resistance σ∆Rs. Typical matching parameters extracted from the drain current modeling, as well as their respective contributions are summarized in Figure 22 . It indicates that there is a slight degradation of variability at low temperature and that the matching is mainly dominated by threshold voltage variability in weak inversion and by gain factor and access resistance mismatch at strong inversion.

Figure 22.

Summary of matching performance and respective parameter contributions at 300 K (RT) and 4.2 K (LT) for NMOS (W = 1.39 μm, L = 28 nm). After Cardoso et al. [45].

5. Device compact modeling approach

In previous sections, we focus our efforts on understanding individual device physics and variability at cryogenic temperature. In this section, we present typical Poisson-Schrodinger simulation results for the capacitance and charge control in FDSOI structures operated down to deep-cryogenic temperatures and their application for building up an analytical compact model for charge and drain current in FDSOI MOSFET including back biasing effect.

5.1 Poisson-Schrodinger simulations

Poisson-Schrodinger (PS) simulations were conducted after solving self-consistently the Schrodinger and Poisson equations given below:

Hψ=EψE6
εrV=qnxε0E7

with H the Hamiltonian, E the system energy, ψthe electron wave function, ε0 and εr the vacuum and relative silicon permittivity, n the carrier density as a function of position xin the Si channel depth. The electrical potential V, the subband energies Ei,j and wave functions ψi,j for valley jand level iare numerically calculated in a FDSOI structure for given front and back gate voltages. Then, the electron density is obtained after summing the different valleys and subband contributions as:

nx=j=12i=1imaxgjA2D,jkBTψi,j2x.F0EfEi,jkBTE8

where kBT is the thermal energy, F0 is the zero-order Fermi-Dirac integral function, Ef the Fermi level, Ei,j the subband energy, gjthe valley degeneracy, and A2D,j the 2D density of states of valley j.

It should be noted that in order to compute the PS equations down to very low temperature (1 K), special truncation caution has been taken to avoid numerical overload in the F0 Fermi integral function accounting for Fermi-Dirac statistics. PS simulations were also possible at 0 K by replacing the F0 Fermi-Dirac integral function by a Heaviside function, thus mimicking the fully degenerate metallic statistics.

The 1D FDSOI structure used for PS simulation is depicted in Figure 23 , showing the band diagram across the stack and typical electron density profile in the channel obtained at T = 4 K for a given bias condition.

Figure 23.

Typical band diagram and electron distribution from PS simulation for a FDSOI structure (Vg = 1 V, tox = 1 nm, tbox = 25 nm, tsi = 7 nm, Vb = 0 V, T = 4 K. after Aouad et al. [41].

Figure 24 demonstrates the variations of the inversion charge Qi in the Si film as a function of front gate voltage Vg with Vb = +3 V, obtained from PS simulations for various temperatures between 0 K and 60 K. A strong increase of the subthreshold slope with temperature dropping can be noticed, reaching infinity at T = 0 K, which is an interesting feature for transistors operating at such low temperatures.

Figure 24.

Inversion charge Qi(Vg) calculated for different temperatures (tox = 1 nm, tbox = 25 nm, tsi = 7 nm, Vb = +3 V). After Aouad et al. [41].

Figure 25 shows the inversion charge control by field effect through the variations of the gate-to-channel capacitance Cgc(Vg) = dQi/dVg with front gate voltage for various back gate biases Vb. The onset of the back inversion channel for Vb = +3 V is evidenced by an additional plateau in the Cgc(Vg) curve, followed by the front channel opening. This effect clearly demonstrates the capacitive coupling, through the silicon channel, between the front gate and the back channel inversion layer, which leads to a lower capacitance.

Figure 25.

Cgc(Vg) curves for different back biases Vb (tox = 1 nm, tbox = 25 nm, tsi = 10 nm, T = 4 K). After Aouad et al. [41].

The impact of temperature on the Cgc(Vg) characteristics is shown in Figure 26 , clearly revealing the rounding of the curves with temperature rise above T = 10 K.

Figure 26.

Cgc(Vg) curves for different temperatures (tox = 1 nm, tbox = 25 nm, tsi = 10 nm, Vb = +3 V). After Aouad et al. [41].

5.2 Compact modeling

Following the PS simulation results, an analytical model has been established considering that front and back channel charges can be evaluated separately at each interface within a single subband approximation with energy level of a triangular potential well [41]. The coupling between the front and back channels is realized owing to the silicon channel capacitance Csi and the charge sheet approximation with Fermi-Dirac statistics.

In this case, the charge conservation equations at front and back interfaces are expressed by:

Vg=Vfb+Vs1+qNinv1Cox+Csi.Vs1ΔVF1Vs2+ΔVF2CoxE9
Vb=Vfb+Vs2+qNinv2Cbox+Csi.Vs2ΔVF2Vs1+ΔVF1CboxE10

where the front and back interface 2D charge densities read,

Ninv1,2=A2d.kB.T.F0Vs1,2V0ΔVF1,2kBTE11

where Vs1 (Vs2) is the front (back) interface surface potential, Cox (Cbox) the front (back) oxide capacitance, Csi the silicon film capacitance. The front and back electric field are given by:

F1=VgVs1Vfb3toxE12
F2=VbVs2Vfb3tboxE13

with the Airy subband potential shift ΔVF=KF+F02/3with K = 1.75 × 10−5 V1/3 cm2/3 [67]. As the film quantization effect is dominating when the electrical field approaches zero, an offset field F0 is added to the electric field to account for the flat band quantum confinement [41].

Typical Qi(Vg) and Cgc(Vg) characteristics obtained by this Airy-based analytical model are presented in Figures 27 and 28 , along with the PS simulation results. As can be seen, the compact model provides a good agreement with PS data, emphasizing its physical consistency in terms of charge and capacitance.

Figure 27.

Qi(Vg) curves obtained from PS simulations (solid lines) and analytical modeling (dashed lines) for various Vb = −3, 0, +3 V (T = 4 K, tox = 1 nm, tbox = 25 nm, tsi = 10 nm). After Aouad et al. [41].

Figure 28.

Cgc(Vg) curves obtained from PS simulations (solid lines) and analytical modeling (dashed lines) for various parameters Vb = −3, 0, +3 V (T = 4 K, tox = 1 nm, tbox = 25 nm, tsi = 10 nm). After Aouad et al. [41].

The total drain current in the channel can then computed, within the gradual channel approximation, by integrating the channel conductance between source and drain for the front and back channel and by adding their contribution as:

Id=WL0Vdμeff1Qi1.Qi1Vs1Uc.dUc+WL0Vdμeff2Qi2.Qi2Vs2Uc.dUcE14

where Uc is the quasi Fermi level shift between source and drain common to both channels, Qi1,2 = q.Ninv1,2 are the front and back inversion charges obtained from Eq. (11) and μeff1,2 are the front and back channel effective mobility evaluated separately using Eq. (3). In absence of inter-subband scattering, the drain current calculated using Eqs. (3) and (14) does not exhibit a decrease for Vb = 4 V when the front channel is opening, in contrast to the experimental results discussed in Section 2.3(see Figure 29 ). Inter-subband scattering can be taken into account through an additional explicit dependence of the back channel mobility with the front inversion charge density of the form, μeff2,IS = μeff2.[a + b.exp.(-Ninv1/c)], with a, band cbeing fitting parameters ( Figure 30 ). By this way, the drain current can reasonably be well modeled as shown in Figure 29 (dashed blue line), inferring the crucial role of remote inter-subband scattering in the back channel mobility.

Figure 29.

Drain current vs. front gate voltage Vg: Experimental (red solid line) and modeled with IS (dashed blue line) and modeled without IS (green dashed line) for Vb = 4 V and 0 V at T = 4.2 K.

Figure 30.

Experimental (red solid line) and modeled (dashed blue line) back channel mobility μeff vs. front channel inversion charge density Ninv1 for Vb = 4 V at T = 4.2 K. model parameters: A = 0.45, b = 0.55 and c = 1.5 × 1012/cm2.

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6. Basic circuit operation at cryogenic temperatures

Although operational cryo-CMOS circuits have been demonstrated down to 30 mK [17, 30, 68, 69, 70], unfortunately no mature models are yet available to accurately predict the behavior of passive and active devices at cryogenic temperatures [71, 72]. Due to this lack of compact models at cryogenic temperatures, designers are faced to a blind-design procedure, which reduces the optimization of cryogenic integrated circuits [12, 30, 32, 58, 73, 74, 75]. Using the extensive electrical characterizations of single FDSOI transistors at cryogenic temperatures, it is however possible to already design efficient circuits.

Among them oscillators are essential building blocks in many digital and analog circuits. They are required for example to generate a clock signal in the control circuit of quantum computers [30, 76], and so must be also efficient at cryogenic temperature. Here we have electrically characterized ring oscillator (RO) fabricated from 28 nm-FDSOI technology [30, 77]. Figure 31a shows the delay per stage of a 101-stages RO as a function of temperature from 300 K down to 4.2 K. Without any back-biases applied on the MOSFETs composing the inverter stages, decreasing the temperature results in slowing down the RO. This can be explained by the threshold voltage shift at cryogenic temperature, which leads to a decrease of the effective current evaluated from the single characteristics of NMOS and PMOS transistors.

Figure 31.

(a) Delay per stage versus temperature of a 101-stages RO (L = 34 nm, WNMOS = 420 nm, WPMOS = 600 nm) for different supply voltages VDD = 0.8, 1, and 1.2 V showing the RO slowing down due to the increase of VTH at low temperature. (b) Delay per stage versus temperature for VDD = 0.8, 1, and 1.2 V in the case of compensated VTH. The RO speeds up at low temperature due to the carrier mobility enhancement (from Bohuslavskyi et al. [77]).

The effective drive current IEFF, which is a measure of the current drive of the MOSFET during switching and correlates well to circuit delay, can be defined for a single inverter as [78],

IEFF=1IEFF,NMOS+1IEFF,PMOS1E15

with

IEFF,NMOS/PMOS=IH+IL2E16

where

IH=IDSVGS=VDDVD=VDD/2IL=IDSVGS=VDD/2VD=VDDE17

Figure 32a shows the evolution of IEFF as a function of temperature, in the case where no VBG is applied. We observed that IEFF decreases with temperature, and this decrease is stronger as VDD is decreased (3 decades degradation from 300 K to 4.2 K for VDD = 0.8 V). This IEFF variation is linked with the temperature dependence of IDS-VGS curves. A zero-temperature coefficient point (ZTC), corresponding to a gate voltage for which the drain current exhibits no temperature dependence, is systematically observed on the measured IDS vs. VGS curves, as illustrated in Figure 33 and already evidenced in Figures 4 and 17 [79]. For |VGS| < |VZTC| the drain current decreases as T decreases (∂IDS/∂T|VGS = cte > 0), whereas for |VGS| > |VZTC| the drain current exhibits an opposite temperature behavior (∂IDS/∂T|VGS = cte < 0).

Figure 32.

(a) Effective current IEFF measured on single NMOS and PMOS transistors (L = 34 nm, WNMOS = 210 nm, WPMOS = 300 nm) for different supply voltages VDD = 0.8, 1, and 1.2 V; the effective current decreases as the temperature is reduced. (b) IEFF versus temperature for VDD = 0.8, 1, and 1.2 V in the case of compensated VTH; in that case the effective current increases as the temperature is reduced (from Bohuslavskyi et al. [77]).

Figure 33.

(a) Drain current IDS measured on single NMOS and PMOS transistors (L = 30 nm, WNMOS=WPMOS = 210 nm) as a function of gate voltage VGS for different temperature from 300 K down to 4.2 K. a zero temperature coefficient (ZTC) point for which the drain current (IDS) is independent of the temperature is evidenced for NMOS and PMOS.

It is worth noticing that for the pMOS the ZTC point is located at higher |VGS| (≈1.1 V) compared to the nMOS devices (≈0.7 V). The IEFF temperature dependence is mainly driven by the region with positive T-dependence ∂ IDS/∂T|VGS = cte, i.e.for |VGS| below |VZTC|.

If a back bias VBG is applied, it is possible to shift the threshold voltage back to its room temperature value ( Figure 6 ). In that configuration, the drain current IDS increases with the temperature decrease whatever VGS and VDS values, due to mobility and saturation velocity improvement with T decrease at a given |VGS-VTH| overdrive gate voltage (see Section 2.4). Consequently, the effective current IEFF follows the same trend with respect to T ( Figure 32b ). Thus a correctly chosen forward back bias on NMOS and PMOS will lead to a speed-up of the RO as T decreases ( Figure 31b ). At a given temperature, the back biasing VBG allows to tune the frequency as illustrated in Figure 34 . Finally by playing with the supply voltage VDD and VBG it is also possible to manage power consumption and performance [30, 77]. It has been illustrated at 110mK on a VCO RO ( Figure 35 ) where back bias allows switching from low power mode (e.g.27 μW at 2GHz) to high performance mode (e.g. 6.9GHz for 268 μW).

Figure 34.

Oscillating frequency as a function of VCO voltage for a VCO RO (L = 28 nm). Forward Back-biasing increases maximal frequency (from Guevel et al. [30]).

Figure 35.

Power as a function of supply voltage VDD and back bias voltage VBGRO (L = 28 nm). Forward back-biasing decreases power for same frequency (from Guevel et al. [30]).

7. Summary and conclusions

A review of recent results obtained on 28 nm FDSOI transistors operated down to deep cryogenic temperatures has been presented. First, the main device electrical properties in terms of gate capacitance and charge control and drain current transfer characteristics have been discussed along with the temperature dependence of the major MOSFET parameters (threshold voltage, subthreshold swing and mobility). Then, the self-heating phenomena were characterized in details, providing valuable information about the actual device temperature versus power dissipation, as well as the thermal resistance that limits the heat dissipation in the FDSOI structure, especially at low temperature. The matching properties have then been studied owing to threshold voltage and drain current statistical variability analysis, revealing that the mismatch in FDSOI transistors only increases of about 30–40% at deep-cryogenic temperatures. Besides, Poisson-Schrodinger simulations have been carried out with success down to zero Kelvin, giving access to valuable information about the gate charge control in FDSOI structures versus temperature, and, providing physical insight to the development of compact model mandatory for FDSOI circuit design at deep cryogenic temperatures. Finally, the operation of elementary circuits such as ring oscillators and voltage controlled oscillators has been demonstrated in terms of inverter delay and clock frequency down to deep-cryogenic temperatures.

This work highlights the powerful advantage of FDSOI over bulk technology, led by the back biasing capability. It offers in particular an efficient way to manage power consumption and performance, thus mitigating thermal effects, which are crucial aspects in cryo-electronics.

Acknowledgments

This work was partially supported by the French Authorities within the frame of NANO2022 project, and by the ERC Synergy QuCube (Grant No. 810504 — QUCUBE — ERC-2018-SyG), and EU H2020 RIA project SEQUENCE (Grant No. 871764).

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Mikaël Cassé and Gérard Ghibaudo (June 7th 2021). Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications [Online First], IntechOpen, DOI: 10.5772/intechopen.98403. Available from:

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