Line Impedance Emulator: Modeling, Control Design, Simulation and Experimental Validation

The variation of line impedance has always been a great concern for grid operators and industrial users. The problem is that the reliability and quality of the supplied power are influenced by this variation. Indeed, several standards and grid requirements fix strict rules and rigorous standards when connecting or disconnecting from the public grid. In this context, this chapter proposes a full study of a line impedance emulator, which includes the power design and the control. The line impedance emulator is useful for small scale laboratories that develop distributed energy generation. Developed line impedance emulator is based on a three-phase power converter. For these converters, different controls are applied, including proportional integral and resonant controllers. For the generation of voltage reference values that correspond to expected line impedance, two algorithms are studied, namely, trigonometric functions-based algorithm and voltage drop-based algorithm. The theoretical study is supported by simulation and experimental results.


Introduction
Nowadays, with the tremendous increase of distributed energy generation (DEG), the concept of power quality (PQ) has become a growing concern for grid operators around the world [1][2][3][4]. Many research teams working on this topic are developing small or large-scale DEG laboratories (Figure 1) [3][4][5][6][7][8][9] as well as algorithms for critical situations is the grid emulator. This grid emulator is also used to confirm the compliance with standards and different grid codes [10][11][12][13].
This chapter covers one of the functionalities of the grid emulator, which is the line impedance emulation. Indeed, line impedance deviation can be caused by several circumstances, such as, a remote grid fault, or a connection disconnection of a large load in the distribution network [14].

Line impedance emulator presentation
The line impedance emulator is installed between the grid and the EUT and used for the emulation of variable line impedance. The structure of the studied line impedance emulator system is shown in Figure 2. It incorporates two power converters joined by dc-link capacitor: an EUT side converter (EsC) and a grid side converter (GsC). The GsC and the EsC are AC/DC and DC/AC converters, respectively. To mitigate switching harmonics, an LCL filter is employed at the output of the EsC. The EsC control aims to maintain the voltage through the LCL filter capacitor V c(abc) equal to the programmed references. The GsC has the intention of regulating the system power factor (PF) and the voltage at the DC bus V dc . As presented in Figure 2, the line impedance emulator output V out(abc) is equal to V c(abc) , while its output V in(abc) is considered comparable to the grid voltage V g (abc) .
The flowchart of the line impedance emulator process is given by Figure 3. The first step of this flowchart consists in initializing the different functions and the microcontroller peripherals such as the ADC, Timers and the General Purpose Input/Output (GPIO) as well as the analog-to-digital conversion of the measured voltages and currents. The next step is to control of the GsC. The objective of this control is voltage at the DC bus regulation. In parallel with these steps, the impedance emulation algorithm provides the capacitor voltage references V c(a,b,c) * according to programmed impedance. Once V dc is equal to its reference and the capacitor voltage references V c (a,b,c) * are generated, the operator proceeds to the control of the EsC. The desired line impedance is consequently achieved. Figure 4 summarizes the different steps of the line impedance emulator design. As mentioned, the first step consists in modeling the two power converters of the line impedance emulator giving the system equations and transfer functions. After that, the operator selects the appropriate control converters control in terms of dynamic response, THD value, steady state error and sensitivity to perturbation and parametric variation. In this chapter, the control of the line impedance emulator converters employed resonant controllers and PI regulators. This choice is due to  their simple use (tuning parameters and implementation), while ensuring simultaneously acceptable dynamic response, THD value and steady state error. Then, based on the obtained system transfer functions, the control parameters are deduced. After that, the operator should select the appropriate line impedance emulator algorithm. In this chapter, two impedance emulator algorithms will be presented. The next step of the design methodology consists in simulating the whole system including the power converters, the control strategy and the line impedance emulation algorithm. When the simulation results verify the proper system operation, the control will be implemented on a digital board. The last step of the design methodology consists in the experimental validation of the line impedance emulator.

Line impedance emulator modeling
The GsC power circuit single phase representation is depicted on Figure 5, where L g denotes the grid impedance. According to this figure, the GsC electric equation in the abc reference frame is given by Eq. (1).
The EsC power circuit single phase representation is given by Figure 6. Based on this Figure Figure 8 shows the GsC control. It incorporates two control loops. The internal loop controls in the abc reference frame the grid currents i g(abc) and it is based on   resonant controller. The external loop regulates, via a PI regulator, the voltage at the DC bus V dc and provides grid current reference on d axis i gd * . The grid current reference on the q axis i gq * is selected to have the desired PF. For the abc grid current reference components i g(abc) *, they are obtained via the application of Park transformation to i gd * and i gq *. In the following, the tuning of the PI and the resonant controller parameters will be detailed.

Tuning of the PI regulator of the voltage at the DC bus
Based on Figure 9, the current i dc at the output of the GsC is expressed as in Eq. (6). By applying the Laplace transform to Eq. (6), Eq. (7) is obtained.
Since the current i dc is instantaneously equal to AEi g and the current regulation loop time constant is insignificant compared to the one of the DC bus voltage regulation loop, Figure 9 gives simplified DC bus voltage regulation loop block diagram.
The transfer function of the PI regulator is given by Eq. (8). Based on this equation and neglecting the load current i s , the closed-loop transfer function of the V dc control is given by Eq. (9).
The transfer function of Eq. (9) is a second-order system whose denominator can be written in the canonical form of a second-order system given by the righthand side of Eq. (9). By identifying the terms of Eq. (9), the obtained transfer function is characterized by a damping ratio ξ c and a natural frequency of oscillation ω nc that satisfy Eq. (10) and Eq. (11). Then, the form and the dynamics of the response of the DC bus voltage V dc are imposed by setting the natural frequency of the oscillations ω nc and a damping coefficient ξ c . Thus, the gains K pdc and K idc can be obtained based on equations Eq. (12) and Eq. (13).

Tuning of the resonant controller of the grid side current
The use of the PWM makes it possible to have a fundamental of the voltage U i equal to its reference U i * . Thus, based on Eq. (1), we obtain the simplified single-phase block diagram the grid side regulation loop given by Figure 10.
Considering Figure 10, the closed-loop system transfer function (T cig ) is given by Eq. (14).
For the synthesis of the resonant controller parameters, we consider the pole placement method and more precisely the Naslin criterion [20][21]. The n order polynomial of this criterion is expressed by Eq. (15).
The identification between the system characteristic polynomial P ig and the second order Naslin polynomial makes it possible the deduction of resonant controller parameters K pig , et K iig as shown in Eq. (17) and Eq. (18).

EUT side converter control
The control based on resonant controller for the EsC is depicted on Figure 11. This control includes an external and an internal loops. The external one controls the voltages through the filter capacitor V c(a,b,c) . The internal one controls the inverter side current i 1(a,b,c) and generates then the inverter voltages references V i(a,b,c) . For the external loop, a resonant controller is adopted. For the internal loop, the resonant controller is replaced by a constant gain (G) in order to ensure a faster loop than the external one. In the following, the tuning of the resonant controller parameters will be detailed and discussed in order to ensure good control performances.

Tuning of the resonant controller of the voltage through the LCL filter capacitor
For reasons of simplification, it is assumed that the internal loop of the current is faster than the external loop of the voltage. Thus, we can approximate it equal to the unity by associating the PWM function. Consequently, the block diagram of the voltage regulation loop is given by Figure 12.
Hence, the closed loop system transfer function (T c ) is given by Eq. (19).

Numerical Modeling and Computer Simulation
The method chosen for the computation of the resonant controller parameters is based on the generalized stability criterion [22]. In this case, the n order polynomial is expressed as in Eq. (20).
On the other hand, based on Eq. (19), the system characteristic polynomial P c is given by Eq. (21).
The identification of P c and second order generalized stability criterion polynomial allows the deduction of the resonant controller parameters as shown in Eq. (22).

Tuning of the gain of the current i 1
The simplified internal current regulation loop block diagram is given by Figure 13.
Hence, the transfer function of the closed-loop system T i1 (s) is given by Eq. (23).
G is chosen so that the real part of the inverse of the closed-loop time constant (1/τ c ) is greater than the stability margin chosen for the synthesis of the voltage external loop in order to ensure that the internal loop is faster than the external one.

Line impedance emulation algorithms
In this section, two methods of the line impedance emulator algorithm synthesis are presented: the trigonometric functions-based algorithm and the voltage drop-based algorithm.

Trigonometric functions-based algorithm
The impedance emulation conception is based on the phasor diagram depicted on Figure 14 According to this Figure, the apparent power S is expressed as in Eq. (24).
According to Figure 14, the reactive power Q and active power P are given by Eqs. (25) and (26), respectively. These equations allow the deduction of tanδ and the voltage magnitude V out given, respectively, by Eqs. (27) and (28). On the other hand, the Q and P can be also written as a function of αβ output current and voltage components as shown in Eqs. (29) and (30), respectively. Figure 15 shows the trigonometric-based line impedance emulation algorithm. The first step consists in measuring the grid voltage V g(a,b,c) and computing its RMS value. From the obtained value, we compute the phase shifting δ relatively to the grid voltage. After that, the emulated impedance is computed based on the previous equations.

Voltage drop-based algorithm
This algorithm is based on a voltage drop V v that matches with the emulated line impedance Z as shown in Figure 16 This voltage is a function of programmed inductance and resistance variations as presented in Eq. (31). The voltage dropbased line impedance emulator algorithm is presented in Figure 17.

Figure 14.
Line impedance and phasor diagram.

Simulation and discussion
Simulation tests were performed under PSIM software. The proposed control was applied to a 20kVA line impedance emulator. Table 1 gives the line impedance emulator parameters. In Figure 18 is presented the V dc response to a step reference of 100 V. Based on this result, the steady state error of the V dc voltage becomes null in the steady state, which prove that this voltage is well regulated. Figure 19 shows that the voltage V c(abc) is well regulated in both transient and steady state operation even reference magnitude change at 0.9 s. To show the voltage drop-based line impedance emulation algorithm performances, a control scenario is presented in Figure 20. This scenario consists in imposing in the interval [0, 1 s] equivalent real impedance in series with L 2 and in the interval [1 s, 1.5 s] the line impedance emulator is activated. Figure 21 shows results for a line impedance Z characterized by X = 1.5 Ω and R = 1 Ω in case of real and emulated impedance. As shown in this figure, the same current value is generated for real and programmed line impedances.           with 0.3 Ω internal resistors; (3) a 20 kVA AC/DC converter (GsC); (4) a dc-link capacitor (1100 μF/800 V); (5) a 20 kVA DC/AC converter (EsC); (6) an LCL filter (composed of three inductors (2 mH/10 A) with 0.1 Ω internal resistors, three capacitors (4 μF/400 V) and three inductors (2 mH/10A) with 0.1 Ω internal resistors); (7) a measurement board (LEM LA55 and LEM LV25 for currents and voltage measuring, respectively); and (8) the STM32F4-Discovery digital solution. It is worth noting here that two STM32F4-Discovery cards were used in the experimental test bench; the first one is dedicated to the GsC control and the second one is dedicated to the EsC control.
For both GsC and EsC controls, the switching frequency was fixed equal to 10 kHz. For experimental tests, the switching frequency is equal to 10 kHz, the voltage at the DC bus V dc is initially charged at 55 V. Figure 24 presents the voltage at the DC bus V dc response. As shown is this figure, V dc is well controlled during steady state operation. Figure 25 presents the response of the line impedance emulator output for a reference change from 20 to 10 V. This test shows that the EsC control ensures an acceptable dynamic response and it is well controlled at steady state. Figure 26 presents the line impedance emulator input and the output that matches with various values of line impedance.

Conclusion
In this chapter, line impedance emulator was studied. This equipment is used in small scale laboratories studying distributed energy generation. It ensures power tests with variable line impedance. Presented line impedance emulator is based on two power converters connected via a dc-link capacitor. Theoretical study is detailed and validated by simulation and experimental tests. The proposed study describes in detail the control design of each power converter. In addition, two variants of line impedance emulator algorithms were synthesized. To prove the efficiency of the presented study, a test with a real impedance and an emulated one was performed and obtained results show the similarity of system responses with both equipment.