Modeling of Nano-Transistor Using 14-Nm Technology Node

Latest process technologies in transistor development demonstrate massive changes in the size of transistor chip. In this chapter, a 14-nm technology node is used to model nanosize transistor. The 14-nm technology node consists of multiple numbers of carbon nanotube. Carbon nanotube is a very good energy efficient and low-cost material. Carbon nanotube demonstrates excellent characteristics in metallic and semiconducting characteristics by analyzing electrical properties. At first, the nanotube device physics and material properties are briefly explained in this chapter. Further, a nanotube device is designed for semiconducting properties. The gate length of nanotube is 14 nm which is placed on the gate channel. Finally, the model of 14-nm nano-transistor will be demonstrated for lowenergy consumption which can be considered as a better replacement of CMOS.


Introduction
Nanoelectronics research is upgrading due to the increases of consumer demand of electronics device in small scale.Nanotechnology research area encourages the researchers to work on nanomaterials as an immerging technology for future.Carbon nanotube (CNT) is a potential material in the field on nanotechnology that has the ability to overcome almost all the limitations of other nanomaterials for its excellent electrical and mechanical properties.Therefore, one of the potential uses of CNT is to place as gate channel of a FET is called carbon nanotube field effect transistor (CNTFET).Silicon-based circuit is moving towards its physical limitation point according to the proven experiment [1].Due to similar ballistic transport and high career portability of silicon material, CNTFET can be a good replacement of silicon [2] while CNT can be acted as a semiconducting material [3,4].Nanotube is able to show its excellent electrical properties in designing digital devices [5,6] in small scales.Another special characteristic also to be highlighted for nanotube is I-V features which enable to use the CNT in MOS transistors [7][8][9][10].According to device physics, the performance of the chip can be improved by reducing the size but there is a limitation about the reduction of silicon device size.Nano-hardware, which was created from the 1990s, has turned out to be a standout amongst the most dynamic research subjects in this day and age.The nanoelectronics innovation, which can fundamentally diminish the transistor measure, is particularly alluring to individuals.Single-walled carbon nanotube is mostly used in transistor [11].Ballistic transport properties of MOS transistor are unchanged while the gate channel Si is substituted by nanotube [12].In perspective of the outstanding sizelessening issues of traditional Si-based hardware, there have as of late been serious examinations on new advances in light of nano-organized materials which are shaped by sorted-out development and self get-together strategies.CVD process was used in the laboratory to grow nanotube from dielectrophoresis in early ages of its generation [13].The first CNTFET was fabricated for prototype testing [14] which allows the researchers to work on this promising field of nanotechnology.CNTFET shows good performance in designing logic gates for integrated circuit modeling [15,16].Therefore, CNTFET can be a promising research in the near future.

Carbon nanotubes properties 2.1. Geometry of carbon nanotubes
A carbon nanotube can be characterized by chiral vector and its length and a vector called the chiral vector.Chiral vector is the sum of the multipliers of the two base vectors, like Eq. (1) [17][18][19][20] The coordinates of the graphene sheet (m,n) allows finding the chiral vector (C h ) of the nanotube.
The two-dimensional graphene lattice in real space can be created by translating one unit cell by the vectors T ¼ na 1 þ ma 2 with integer combinations (n, m), where a 1 and a 2 are basis vectors and is shown in Figure 1, a 0 ¼ 3a cc is the length of the basis vector, and a cc ≈ 1:42 Å is the nearest neighbor C-C bonding distance.

Design, Simulation and Construction of Field Effect Transistors
To all the more decisively acquire the moment vector T, we can get it from the m, n segments of the C h vector.On the off-chance that we demonstrate the parts of T with t 1 and t 2 ,a sTi s opposite to the C h , the inward result of these vectors is equivalent to zero and we can conclude Eq. ( 3) The briefest vector t 1 and t 2 that are legitimate as per Eq. ( 3) can be isolated t 1 and t 2 by their most prominent normal devisor or in short shape most noteworthy basic divisor (gcd), to acquire the briefest nuclear site vector towards the path, opposite to the C h vector.d R as in Eq. ( 4), t 1 ,t 2 can be accomplished in Eqs. ( 5) and ( 6) The angle between the chiral vector and the a 1 base vector is called the chiral angle, the twist angle or the helix angle and is denoted by θ c and can be obtained in Eq. ( 7) Modeling of Nano-Transistor Using 14-Nm Technology Node http://dx.doi.org/10.5772/intechopen.76965 Here, we should take note of that to consider a one of a kind chiral plot for each nanotube; the point is expressed by an incentive in the locale (0, 30 ).Utilizing these definitions, the breadth of the tube can be processed utilizing the balance of the length of the C h and the nanotube's periphery; lastly, we can acquire the measurement characterized by The length of the chiral vector is the peripheral length of the nanotube: The bandgap of a single wall nanotube (SWNT) is defined by From Eq. ( 4), if (n-m) is divisible by 3, then nanotube is metallic, otherwise the nanotube is semiconducting.
Now, the number of atom of the nanotube is defined by

Classification of carbon nanotubes
Carbon nanotube (CNT) is classified into three groups as shown in Figure 2: (1) armchair, (2) zigzag and (3) chiral, based on the geometrical arrangements of the graphene during the form tube formation.
If the C h is defined as n; 0 ðÞ ,itisgiventhenamezigzagnanotubeandiftheC h is defined as n; n ðÞ , then the tube is called armchair, and these refer to the form shaped on the circumference of the tube.

Armchair tubes
If the chiral indices (m, n) of a nanotube in a zone-folding region can be divisible by 3, then it becomes metallic.These nanotubes are called 'zone folding metallic', or shortly, Z F-M tubes.

Zigzag tubes (semiconducting tubes with bandgap)
The primary band gap of a nanotube is considered as semiconducting material if the Chirality (m, n) in the zone folding area is not divisible by 3. We should allude to these nanotubes as 'zone collapsing semiconducting', or in a matter of seconds, ZF-S tubes.
Design, Simulation and Construction of Field Effect Transistors

Electrical properties
Carbon nanotubes (CNTs) have outstanding electrical properties based on the chirality.There are two types of carbon nanotube, such as single-walled carbon nanotube (SWCNT) and multiple-walled carbon nanotube (MWCNT) based on the requirements of the CNT in the integrated circuit (IC) design [21][22][23].Figure 3 shows the different types of carbon nanotube.A single-walled carbon nanotube has only one shell with a small diameter usually less than 2 nm.As well as multi-walled carbon nanotube consists of two or more concentric cylindrical shells with the diameter of 2-30 nm.
The electrical properties of a nanotube can be realized from its bandgap.Semiconducting nanotube is a novel choice for the transistor development.Thus, Figure 4 shows bandgap versus radius for semiconducting (zigzag) nanotubes.The bandgap decreases inversely with an increase in diameter.The points with a zero bandgap correspond to metallic nanotubes which satisfy n = 3i, where i is an integer.

Modeling process of 14-nm CNTFET
This research consists of the design and verification of the CNTFET device's small signal model.Figure 5 shows a solid model of CNTFET with a built-in circuit model in this work.

CNTFET biasing
Three different types of biasing structure are seen in the CNTFET device.They are commondrain, common-gate and common-source structure.Common-source transistor circuit is considered in this modeling.The common-source circuit is shown in Figure 6; the DC shows bias on drain and gate with an AC signal present as the input at the gate.

CNTFET small signal model
This section describes about the design and analysis of the small signal model circuit for CNTFET.The proposed small signal model of a CNTFET is shown in Figure 7.I nFigure 7, C g-CNTS refers to the capacitance between gate electrodes to source, C g-CNTD refers to the capacitance between gate electrodes to drain, C g-CNTS refers to the capacitance between gate electrodes to source, and Ri represents the internal resistance.Furthermore, g m refers to the intrinsic transconductance and g d refers to the drain conductance of the circuit as shown in Figure 7.In this circuit, the parasitic elements are excluded for the analysis purpose.shows the simulation results of frequency versus transconductance while the transconductance is increased linearly.This is as a result with μS through the stage of the lower frequency as well as mS through the stage of increasing frequency.Therefore, highfrequency small signal model of CNTFET is obtained in 10 THz with 1.8 mS.On analyzing the data, we first calculate and simulate the transconductance value in μS and in mS.Tables 1 and 2 show the selected values of transconductance necessary for the small signal model obtained from the analysis of the model as shown in Figure 8(a) and (b).By comparing the two tables, transconductance in mS performs the higher frequency rather than to use in μS.Therefore, we consider transconductance in mS in this research.

I-V characteristics of CNTFET
The proposed CNTFET circuit model is implemented in PSpice.A CNTFET DC characteristic is analyzed and simulated to check the output characteristics.Modeling of CNTFET with the I-V characteristics analysis is obtained from the channel length of 14 nm and width of two times the length of the proposed CNTFET.The I-V characteristic curves validate the proposed circuit model by getting drain current of 6.9 Â 10 5 A at the applied gate voltage of 0.4 V as shown in Figure 9.

Gm (μS)
F T (Hz)   To validate the output characteristics of the current development of proposed CNTFET, we compare the work with other researches.Table 3 shows the comparison of the performance of the proposed model.From this performance comparison, we would like to conclude that the proposed CNTFET model is capable of operating in high frequency.

Conclusion
This chapter discussed the development of the CNTFET model using 14-nm technology.We delineated a short examination of the proposed plan of CNTFET little banner show.The arrangement contains a suitable blueprint of the little banner procedure and demonstrated the displays by re-enacting little banner parameters for CNTFET with respect to that of 45 dB.The inherent capacitance of 14 aF and transconductance of 1.8 mS are used as a piece of this examination.A benchmark is showed up for the immense execution of the exhibit made by differentiating and late research data.Particular characteristics are showed up by a course of action of multiplication.Besides, this system has familiar capacitance with survey, the charge defending capacitance at the repeat of 10 THz.

Figure 5 .
Figure 5. Perspective view of the CNTFET 3D solid model.

Figure 8 (
Figure 8(a) shows the plot for the value of transconductance in μS and Figure 8(b) shows the plot for the value of transconductance in mS.

Table 1 .
Frequencies for different current gain of small signal model while transconductance in μS.

Table 2 .
Frequencies for different current gain of small signal model while transconductance in mS.