Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues

of parameter variation in the optimization methodology for design centering must be implemented.


Introduction
The design of analog integrated circuits is complex because it involves several aspects of device modeling, computational methodologies, and human experience. Nowadays, the well-stablished CMOS (Complementary Metal-Oxide-Semiconductor) technology is mandatory in most of the integrated circuits. The basic devices are MOS transistors, whose manufacturing process is well understood and constantly updated in the design of small devices. Detailed knowledge of the devices technology is needed for modeling all aspects of analog design, since there is a strong dependency between the circuit behavior and the manufacturing process.
Contrary to digital circuits, which are composed by millions (or even billions) of transistors with equal dimensions, analog circuits are formed by tens of transistors, but each one with a particular geometric feature and bias operation point. Digital design is characterized by the high degree of automation, in which the designer has low influence on the resulting physical circuit. The quality of the CAD (Computer-Aided Design) tools used for circuit synthesis is much more important than the designer experience. These tools are able to deal with a large number of devices and interconnections. Digital binary circuits have robustness characteristics in which the influence of non-linearities and non-idealities are not a major concern. Furthermore, mathematical models of devices for digital circuits are relaxed and computationally very efficient.
On the other hand, analog design still lacks from design automation. This is a consequence of the problem features and the difficulty of implementing generic tools with high design accuracy. Thus, the complex relations between design objectives and design variables result in a highly non-linear n-dimensional system. Technology dependency limits the design automation, since electrical behavior is directly related to physical implementation. In addition, the large number of different circuit topologies, each one with unique details, makes modeling a very difficult task.
In general, the traditional analog design flow is based on the repetition of manual optimization and SPICE (Simulation Program with Integrated Circuit Emphasis) electrical simulations. For a given specification, a circuit topology is captured in a netlist containing devices and interconnections. Devices sizes, such as transistors width and length, or resistors and capacitors values, are calculated manually. The verification is performed with the aid of SPICE models and technology parameters in order to predict the final performance in silicon. Specific design goals such as dissipated power, voltage gain, or phase margin are achieved by manual calculation and then re-verified in simulation. Once the final performance is met, the design is passed on to a physical design engineer to complete the layout, perform design rule checks, and layout versus schematic verification. The layout engineer passes the extracted physical design information back to the circuit designer to recheck the circuit operation on the electrical level. When physical effects cause the circuit to miss specifications, several more iterations of this circuit-to-layout loop may be required. This process is repeated for each analog block in the circuit, even for making any relatively simple specification change. The amount of time and human resources used can vary, depending on the design complexity and the designer experience. However, even for a large and most skilled design team, the short time-to-market and strict design objectives are key issues of analog designs. Improvements in the analog design automation can save design time and effort.
In this chapter we analyze the Simulated Annealing (SA) meta-heuristic applied to adjust circuit parameters in transistor sizing automation procedure at electrical level. Previous works have been done in the field of analog design automation to enable fast design at the block level. Different strategies and approaches have been proposed during the evolution of analog design automation, such as simulation-based optimization [5,9,17], symbolic simulation [10], artificial intelligence [6], manually derived design equations [4,21], hierarchy and topology selection [11], geometric programming [12,16] and memetic algorithms [15]. The main difficulty encountered for wide spread usage of these tools is that they require appropriate modeling of both devices (technology dependent) and circuit topologies in order to achieve the design objectives in a reasonable processing time.
Moreover, the option of choosing different circuit topologies is also difficult to implement in a design methodology or tool, since most approaches work with topology-based equations, limiting the application range. The possibility of adding new block topologies must also be included in the methodology, since it is critical to the design. The usage of optimization algorithms combined with design techniques seems to be a good solution when applied to specific applications. This is because a general solution most often proves to have short comings for fully exploiting the capabilities of the analog CMOS technology. The key requirements of an analog synthesis tool are: interactivity with the user, flexibility for multiple topologies and reasonable response time. The interface with an electrical simulator and with a layout editor is also convenient [8].
The remaining of this chapter is organized as follows. Section 2 explains the Simulated Annealing meta-heuristic, its parameters, and functions. Circuit modeling, as well as the parameters and functions involved, are described in Sec. 3. Afterward, Sec. 4 presents a basic circuit used to explain the usage of SA, how the searches occur, and the results achieved. In Sec. 5, Simulated Annealing is used to seek solutions to a more complex circuit, in which we could analyze the impact of SA parameters and functions as a mean to automate circuit design. Finally, Sec. 6 conclude this chapter with our final remarks and future works.

Simulated annealing
The Simulated Annealing (SA) is a well known random-search technique that exploits an analogy with the way a metal heat and slowly freezes into a minimum energy crystalline structure, the so called annealing process. In a more general system, like an optimization problem, it is used for searching the minimum value of a cost function, avoiding getting trapped in local minima. The algorithm employs random searches which, besides accepting solutions that decrease (i.e. minimize) the objective cost function, may also accept some that increase it. The latter are called "indirect steps", and are allowed in order to escape from local optima.
The SA algorithm uses a cooling function T(t), which maps a time instant t to a temperature T, decreasing T as t increases. At each iteration, new steps are randomly taken, based on a probabilistic state generation function g(X), leading to new states in the solution space. In this context X is a vector of d parameters, where d is the dimensionality of the solution space. If a step leads to a state with a worse solution, it is only effectively taken, i.e. the new state is accepted, with a probability less than 1. States with better solutions are always accepted. This probability is given by an acceptance function h(ΔF): Here, ΔF = F t+1 − F t represents the variation of the cost function calculated at two consecutive times steps F t+1 and F t .
The algorithm is able to reach an optimal solution on the choice of the cooling function and probabilistic state generation function. If the temperature in cooling function decreases too fast, the search will run faster, but the SA algorithm is not guaranteed to find the global optimum anymore [13]. This may be acceptable if a solution is needed in a small amount of time and the solution space is well-know or presents high dimensionality. This is called Simulated Quenching (SQ) [1], and is useful when an approximate solution is sufficient. There are some common sets of options to choose from when implementing an SA algorithm. They are described below.

Boltzmann annealing
The Boltzmann annealing is the classical simulated annealing algorithm, using physics principles to choose the probabilistic state generation function in order to ensure convergence to a global minimum. It employs a Gaussian distribution for generating new states: Here, ΔX = X − X 0 and d is the number of dimensionality of the search space. The Boltzman cooling function is described as: where T 0 is the initial temperature, and t is the time step.
Geman and Geman in the classical paper [7] have proved that using Gaussian distribution to generate new states (Eq. 3) with the Boltzman cooling function (Eq. 2) is sufficient to reach global minimum of an optimization function at infinite time.

Fast annealing
Fast Annealing is a variant of the Boltzmann Annealing [20] that uses as probabilistic state generation function the Cauchy distribution: One advantage of the Cauchy distribution over the Gaussian distribution is its fatter tail. When the temperature decreases, the Cauchy distribution generates new states with a lower dispersion than states generated by a Gaussian distribution. In this way the converge using Cauchy distribution becomes faster.
However, in order to guarantee that the algorithm reaches the global minimum, a special cooling function is used: Where T 0 is the initial temperature, and t is the time step. It is important to show that the cooling function used in Boltzmann Annealing (equation 3) decreases more slowly than the cooling function used in Fast Annealing (equation 5). This characteristic turns the convergence of Fast annealing faster than Boltzmann annealing.

Reannealing
The reannealing method [14] raises the temperature periodically after the algorithm accepts a certain number of new states or after a given number of iterations. Then the search is restarted with a new annealing temperature. The reannealing objective is to avoid local minima, which presents interesting results when applied in nonlinear optimization problems.

Simulated Quenching
Simulated Quenching (SQ) [1], described before, is useful when an approximated solution is sufficient and there is a need of faster execution time. An example of the function that can be used to decrease the temperature faster is the exponential cooling function shown below.
Using this cooling function with Boltzmann state generation function (Eq. 2) or Fast state generation function (Eq. 4) will turn the optimization faster, but without convergence guarantee.

Circuit modeling
In order to design an analog integrated circuit with Simulated Annealing optimizations it is necessary to develop a cost function describing the analog circuit behavior. There are two ways to analyze a circuit behavior. One is based on simplified equations as cost functions, which represent the circuit. This is the faster alternative, but has low precision and limits the solutions in some regions of circuit operation. The other way is to use an external SPICE electrical simulator to evaluate the circuit with a complete model. This alternative provides better accuracy, but demands more computational power.
In this work the second alternative is used, with the electrical simulation performed by Synopsys HSpice ®. In the optimization procedure of analog integrated circuit design, the heuristic parameters are the MOSFET transistor sizes W (channel width) and L (channel length), voltage and current sources bias, and capacitors and resistor values. The design flow using Simulated Annealing proposed in this chapter is shown in Figure 1 .
The proposed methodology has three specification structures as inputs: • Design constraints that represent all functions of circuit specifications and variable bounds; • A technology file containing simulation model parameters for the MOSFET transistors; and • SA Options for the configuration of the SA heuristic, such as temperature function, annealing function and stop condition.
The methodology starts with the initial solution generation that is provided by random generated numbers according to the variables bounds values. The circuit specifications of the generated solution are then evaluated by the cost function, which uses the external electrical SPICE simulator. Thereafter, the SA temperature parameter is initialized with the value specified in the SA options.
Thereafter, a new solution is generated by the SA state generation function (see Section 2), and evaluated by the cost function by means of electrical simulations. The new solution is compared with the current solution and, if it has a lower cost function value, it replaces the current solution. Otherwise, a random number is generated and compared with a probability parameter: if it is greater, the current solution is replaced by the new solution; if smaller, the new solution is rejected.
Finally, the stopping conditions are verified and, if satisfied, the optimization process ends. If not satisfied, the temperature parameter is reduced by the cooling function and the procedure continues. The stopping conditions usually include a minimum value of temperature, a minimum cost function variation, and a maximum number of iterations.
For analog design automation, a multi-objective cost function is necessary to aggregate different -and sometimes conflicting -circuit specifications. A typical multi-objective cost function can be: In this function, the first sum represents optimization specifications (design objectives) and the second one the design constraints. S i (X) is the i th circuit specification value and R j (X)) is the j th constraint function. Both are functions of the vector X of design parameters and are normalized and tuned according to the desired circuit performance.
R j (X) is a function that is dependent on the specification type: minimum required value (R min (X)) or maximum required value (R max (X)) [3]. These functions are shown in Fig. 2, where a is the maximum or minimum required value and b is the bound value between acceptable and unacceptable performance values. Acceptable but non-feasible performance values are that points between a and b. They return intermediate values for the constraints functions in order to allow the exploration of disconnect feasible design space regions. These functions return additional cost for the cost function if the performance is outside the desired range. Otherwise, the additional cost is zero.

Basic analysis of the search space
This section presents a simple case study, a differential amplifier, to introduce and explain the usage of Simulated Annealing to automate the design of analog integrated circuit. Section 4.1 describes the features of the differential amplifier. Sec. 4.2 explains the modeling of the differential amplifier that allows its simulation and the usage of the SA. Finally, to improve the automation process, some optimization options on SA are applied and their results are discussed in Sec. 4.3 .

Case study: Differential amplifier
A differential amplifier is a basic analog building block used in general as the input stage of operational amplifiers. Perhaps its simplicity, it is very useful as a first voltage Feasible Acceptable Unacceptable amplification stage of many electronic devices and has become the dominant choice in today's high-performance analog and mixed-signal circuits [19]. Ideally, it amplifies the difference between two voltages but does not amplify the common-mode voltages. An implementation of the differential amplifier with CMOS transistors and active load is shown in Fig. 3 . It is composed by a differential pair formed by two input transistors (M1 and M2), an active current mirror (M3 and M4) and an ideal tail current source I re f . The output voltage V out depends on the difference between the input voltages V in1 and V in2 . For a small difference between V in1 and V in2 , both M2 and M4 are saturated, providing a high gain. Otherwise, if |V in1 − V in2 | is large enough, M1 or M2 will be off and the output will be stuck at 0V or at V DD .
The output voltage of the differential amplifier can be expressed in terms of its differential-mode and common-mode input voltages as where A VD is the differential-mode voltage gain and A VC is the common-mode voltage gain. An ideal operational amplifier has an infinite A VD and zero A VC . Although practical implementations try to find an approximation to these values, the implementation of physical circuits insert some non-idealities that limit A VD and A VC .
Another important characteristic of a differential amplifier is the input common-mode range (ICMR). We can estimate ICMR by setting V in1 = V in2 and vary input common-mode voltage (DC component of V in1 and V in2 ) until one of the transistors in the circuit is no longer saturated [2]. The highest common-mode input voltage (ICMR + ) is Here, V SG3 is the source-voltage of transistor M3 and V TN1 is the threshold voltage of M1. The lowest input voltage at the gate of M1 (or M2) is found to be The voltage at node 1 (V 1 ) is determined by the physical implementation of the current source I re f , which in general is a single transistor whose drain current is controlled by its gate voltage. V GS2 is the gate-source voltage of transistor M2.
The small-signal properties of the differential amplifier can be accomplished with the assistance of the simplified model shown in Fig. 4, which ignores body effect. In this figure, gm is the gate transconductance given by the derivative of the drain current in relation to gate-source voltage: The series resistance rds is the inverse of the output conductance gds and can be estimated in small-signal analysis as 1 Schematics of a CMOS differential amplifier. Figure 4. Simplified small-signal model for the CMOS differential amplifier.
The small-signal voltage gain A vo , i.e., the relationship between V out and the differential input voltage V in1 − V in2 , can be estimated in low frequencies by For higher frequencies, the voltage gain is modified due to the various parasitic capacitors at each node of the circuits, modeled by C 1 , C 2 and C 3 , which are calculated as follows: Considering C 3 approximately zero, the voltage-transfer function can be written as where ω 2 is given as The pole ω 2 determines the cut-off frequency of the amplifier and is also called as ω −3dB . Assuming that gm 3 C 1 then the frequency response of the differential amplifier reduces to This first-order analysis leads to a single pole at the output given by −(gds 2 + gds 4 )/C 2 . Some zeroes occur due to C gd1 , C gd2 and C gd4 , but they can be ignored in this analysis. The gain-bandwidth product (GBW), which is the equal to the unity-gain frequency, can be expressed as The slew-rate (SR) performance of the CMOS differential amplifier depends the value of I re f and the capacitance from the output node to ac ground and is given by where C is the total capacitance connected to the output node (approximated by C 2 in our analysis).
Other important specifications for the electrical behavior of the differential amplifier includes power dissipation P diss = I re f · (V DD − V SS ) and total gate area, calculated as the sum of the product of gate width and lenght of all transistors that compose the circuit: All analog design has a target fabrication technology and a device type, in which the set of transistor model parameters is unique. These parameters determines the electrical characteristics -such as drain current, gate transconductance and output conductance -of the active devices that are part of the circuit. The specifications described before are function of these parameters, together with W and L. Since the parameters are fixed for a given fabrication technology, the designer has as free variables only the gate sizes. Gate sizing is, in effect, the task of analog design.

Modeling the differential amplifier for automatic synthesis
The modeling of the differential amplifier of Fig. 3 for automatic synthesis is straightforward. Using a simulation-based approach, the circuit specifications are calculated by SPICE electrical simulations. As an example, let us consider the multi-objective design of a differential amplifier that must be optimized in terms of voltage gain A v o and positive input common-mode range ICMR + . Also, there is a list of constraints containing a series of specifications that must be met hardly. Table 1 summarizes the design objectives and constraints for this problem. Table 1. Design specifications and constraints for the differential amplifier of Fig 3 . The cost function f c (X) is than formulated as a sum of design specifications and constraints in terms of the vector of the design variables X:

Specification Value
The specifications are calculated for a given X and normalized by a reference value. In this example, ICMR + re f = 1.3V and A vo(re f ) = 20dB. The ponderation of each specification can be implemented with individual weights which indicate the relative importance of the parameter. In this example, we choose a weight of 3 for ICMR + and 1 for A v o. R(X) is a constraint function which is also a function of X, calculated as follows: Here, R max (S(X), S re f ) and R min (S(X), S re f ) are constraint functions of maximum and minimum, respectively, in terms of the specification S(X) and the reference value S re f . For example, the constraint of gate area is related to R max (S(X), S re f ), because it can not be larger than a reference value of Area re f . The same occurs for GBW, which can not be smaller than GBW re f , whose constraint is modeled by the function R min (S(X), S re f ). Both constraint functions insert a penalty value in the cost function f c (X) if the specification is outside the expected range. Otherwise, they return zero. The following equations show how the constraint functions are implemented: We used in this example the constraint reference values shown in Tab. 1 . In order to simplify the analysis, we consider that all transistors of the circuit are of the same size. It is not a practical approach, since transistor M1 must be equal to M2, but not necessarily equal to M3 and M4. However, this simplification allows the 2-D visualization of the problem and can be used to explain design trade-offs and automatic optimal search, providing an intuitive notion of the problem. So, we will consider in this analysis two free variables: The design space for Eq. 24 was fully mapped by electrical simulation varying W and L from 1μm to 100μm with a step of 1μm. The target technology node was 0.35μm 3.3V CMOS. Fig.  5 shows the plotted design space as a function of W and L. It is possible to note the highly non-linear nature of the generated function and the existence of a valley in which is localized a minimum value. The optimal solution for this sizing problem, i.e., the minimum value of the design space, is known exactly in this case and is located at W = 8μm and L = 20μm, with the value of −1.9623.

Optimization of a differential amplifier
For the analysis of Simulated Annealing options and the influence over the automatic sizing procedure of analog basic blocks, we will explore different configurations of temperature schedule, state generation function and reannealing for global optimization and further local optimization. Due to the random nature of some parameters of SA, an statistic analysis is needed to understand the search behavior. We performed 1000 optimization runs for each temperature schedule function described before: Boltzman, Exponential and Fast. The state generation function was kept fixed as g Boltz (X) (Eq. 2). Each execution started with a different seed for the random number generator function. The same parameters were used for the three functions, including the same random number vector for a fair comparison. A MATLAB script was implemented and the native SA method (simulannealbnd) was used as the main bound constrained optimization function.

Global followed by local optimization
In order to improve the results obtained by global optimization with Simulated Annealing, we apply a local optimization algorithm over the previous set of solutions generated by SA with the three temperature schedule functions. We choose the interior point algorithm [18], which is suitable for linear and non-linear convex design spaces. We suppose that the design space region near the solution provided by the global optimization and evolving the global optimum solution is convex and can be explored by this method. The algorithm was implemented by using the MATLAB native function fmincon. The results can be seen in Tab. 4 . It is clear the improvement obtained by the local optimization. The mean final cost of the 1000 executions for the three temperature schedules are close to the known global optimum of −1.960306. The total execution time (including global followed by local execution times) was increased by about 50%, but it is still in a reasonable value, near 20 seconds. Optimum value 8.00 20.00 Table 5. Mean W and L values achieved by local optimization procedure of the differential amplifier over the results obtained by global optimization shown in tab. 3.  In terms of the number of optimal solutions found over the 1000 executions, the local search also demonstrate an improvement. Fig. 7 shows the results obtained, in which we can see that, for Boltzman schedule, almost 90% of the final solutions are optimal, an improvement of more than 50% over the global optimization. The same occurs for the other temperature schedules.
We can observe the improvement in the number of optimal solutions with local search in Fig. 8, which presents the frequency histogram of the resulting final cost provided by global search (Fig. 8(a)) and global search followed by local search (Fig. 8(b)) for the 3 different temperature schedules. Besides the increase in the number of optimal solutions found, the inclusion of local search after global search also approximated the remaining non-optimal solutions in the direction to the best known value.

Global optimization with reannealing
For the analysis of the influence of reannealing in the optimization process, we performed some experiments executing Simulated Annealing with reannealing intervals of 200, 450, 700 and 950 iterations. Again, 1000 executions were done in order to guarantee a statistical analysis for the three temperature schedule functions described before. Fig. 9 shows the relation between the number of optimal solutions found by Boltzman schedule function versus the execution time for reannealing intervals from 200 to infinite (i.e., no reannealing). Reannealing interval affects the number of optimal solutions in this case. As the interval decrease, the number of optimal solutions decrease too. The best configuration is with no reannealing, demonstrating that it is not interesting to use reannealing with T Boltz . It happens because the temperature decreases slowly at the beginning of the annealing process. With the reannealing, the temperature increases for higher values before the search in the design space reaches a path trending to the optimal solution.
When the temperature schedule function is modified to Exponential, the behavior is opposite. As the reannealing interval decreases, more optimal solutions are found. Fig. 10 shows the relation between optimal solutions found and execution time for this temperature schedule configuration.
The same occurs for the Fast temperature schedule function, shown in Fig. 11. As the reannealing interval diminishes, the number of optimal solutions increases. This behavior is maintained for ever small intervals. A high improvement in the number of optimal solutions is obtained for reannealing intervals in the order of 100 iterations, as shown in Fig. 12. As the temperature decreases very fast, the reannealing allows to avoid local minima. Thus, it increases the chances of finding the correct path to the optimum solution. Also, we can observe the existence of an optimum value for the reannealing interval which returns the maximum number of optimal solutions.

Analysis of state generation function
The variation of the state generation function is also a factor that can change the convergence of the Simulated Annealing algorithm. Two of these functions are analyzed here: Boltzman and Fast. The combinations of temperature schedule function and state generation function produce distinct results for the synthesis of the differential amplifier. Fig. 13 shows  the number of optimal solutions returned by the algorithm after 1000 executions for 6 combinations.
We can notice that there are a great improvement in the quality of the solutions using Boltzman temperature schedule together with Boltzman state generation function. This is the best combination, according to that was theoretical predicted in Section 2.

Analysis of best SA options for the differential amplifier
Results presented before allow us to suppose that the temperature schedule function affects directly the quality of the solutions generated by the global optimization algorithm. The Boltzman schedule, followed by a post-processing with a local search algorithm, demonstrate best convergence to the optimal point, at the expenses of a larger execution time. This additional time, however, is not a problem if we consider that the chances of finding the optimal (or near the optimal) solution are increased. For our 2-variables problem, this additional time is irrelevant (about 10s for 1000 executions). For more complex circuits with dozens of variables, the execution time can be a factor of concern. It is increased exponentially with the number of free variables, since the design space grows fast with the number of free variables. We can estimate the design space size D s (X) as: where x i(ub) and x i(lb) are upper an lower bounds of variable x i , respectively, and x i(step) is the minimum step allowed for variable x i . It is clear that the exploration of the entire design space is hard for a problem with several free variables. An alternative, in this case, is to use the Fast temperature schedule with reannealing, which is also efficient in the design space exploration. Both Boltzman followed by local search and Fast with reannealing achieved the optimal solution in about 90% of the cases. These configurations are candidates to be tested in a larger circuit.

Operational amplifier design
In order to apply simulated annealing in a more realistic and practical operational amplifier, we syntesized a folded cascode in CMOS IBM 0.18μm, regular Vt, 1.8V technology node. The schematics of this amplifier is shown in Fig. 14. The modeling of this circuit for the proposed optimization process is simple and similar to the previous described modeling of the differential amplifier. The SPICE netlist and the testbench are the information necessary to describe the circuit and bias. The specifications are simulated by an external electrical simulator (HSpice), which returns, for a given set of variables, the electrical characteristics of the circuit. In our design there are 15 free variables, summarized in Tab. 6. It leads to a very large 15-dimensional design space, which is difficult to explore and find the minimum cost value. It is possible to limit the design space inserting constraints in the cost function related to the operation region of each transistor, forcing the devices to operate at saturation (V DS > V GS − V T ) and strong inversion (V GS > V T ) regions. The specifications and design goals for this circuit are shown in Tab. 7. In the output is connected a capacitive load of 3pF. We expect to size the circuit optimizing gate area and power dissipation while maintaining the constraints of GBW, low-voltage gain, phase margin and slew rate inside a given range.
Using Boltzman for both temperature schedule function and state generation function, followed by local search with interior point algorithm, we find the final results shown in the third and fourth columns of Tab. 7 for global and global followed by local searches, respectively. It is possible to note that all design objectives were reached, while keeping all devices in the specified operation region. There is an improvement in the multi-objective design goal with the post-processing local search. dissipated power is 133.2μW. The advantages of this approach is that the resulting circuit is already validated by electrical simulations and does not need to be verified in another design stage.
We can make a direct comparison of the results obtained by this work using SA with other approaches, such as the tools that use genetic algorithms as main optimization heuristic. Although it is difficult to perform a fair comparison with other works in the literature, mainly because the experimental setup in general can not be reproduced with the provided information and there is no standard benchmarks in analog design automation, it is still interesting to compare the general performance of our methodology with other results over similar circuits and design objectives.
In this sense, the results presented by [3] with the GENOM tool are passible to comparison, because the same experimental setup can be reproduced -although some implementation details are not available, such as the parameters of the electrical model. This tool is based on a variation of genetic algorithm as the main optimization heuristic. The folded cascode was implemented in UMC 0.18μm technology. The final results obtained by GENOM for the same circuit synthesized by our approach are summarized in the fiftieth column of Tab. 7.
We can see that both methodologies present similar results for the design constraints. By the other side, both power dissipation and gate area depicted by our approach using Simulated Annealing are about half the final values provided by GENOM. Power dissipation was decreased in 45.5% and gate area in 49%, a great improvement in circuit performance. These results prove that SA is a powerful heuristic for the design of micro-power operational amplifiers. Again, it is important to note that the comparison between the results can not be exact because some parameters in the device electrical model and other configurations are not equal. The final values for the free variables are shown in Tab. 6. We can see that the gate widths of the transistors trend to be larger than the gate lengths and that the magnitudes are similar in both approaches.

Conclusion
The design of analog integrated blocks and the search for an optimum design point in a highly non-linear design space evolve different approaches and choices. Simulated Annealing and its variations are a good option for the exploration of this kind of problem. This chapter presented some implications of the algorithm tuning over the final results. We could demonstrate that the correct configuration of SA options can lead to good solutions near the optimality in reasonable execution time. Although it is not clear that some configuration is suitable for sizing all types of analog blocks, it is possible to notice that the approach is correct and, with minimum adjusts for different circuits, SA can be used as a general optimization algorithm, providing good solutions. A direct comparison with a tool based on genetic algorithms for the synthesis of a folded cascode operational amplifier showed that better results can be obtained with the correct design space exploration with SA. As future work, the analysis of parameter variation in the optimization methodology for design centering must be implemented.