Analysis and Modeling of Clock-Jitter Effects in Delta-Sigma Modulators

The quest for higher data rates in state-of-the-art wireless standards and services calls for wideband and high-resolution data-converters in wireless transceivers. While modern integrated circuits (IC) technologies provide high cut-off frequencies ( ) for transistors and hence allow the operation at higher speeds, the main limitation against increasing speed of operation of data-converters is the problem of clock-jitter. Clock-jitter is a common problem associated with clock generators due to uncertainty in the timing of the clock edges caused by the finite phase-noise (PN) in the generated clock waveform. Particularly, noise components induced by several noise sources in the system providing the clock (e.g. phaselocked loop, PLL) add to the clock waveform and cause uncertainty in the timing of the zero-crossing instants from cycle to cycle. Figure 1 shows a survey chart of the analog-todigital converter (ADC) implementations reported in IEEE International solid-state circuits conference (ISSCC) and VLSI Symposium since 1997 [1]. The straight lines show the limitation on the achievable signal-to-noise ratio (SNR) by clock-jitter for jitter root-mean square (rms) values of 1ps and 0.1ps. As can be seen from the chart, the performance of most ADCs falls below the line corresponding to 1ps rms jitter, few ADCs reside in the range between 1ps and 0.1ps, and almost all ADC implementations reported so far are beyond the 0.1ps rms jitter line. This means that the main limitation on increasing the ADC performance in terms of SNR and speed is the specification on the clock-jitter of 0.1ps.


Introduction
The quest for higher data rates in state-of-the-art wireless standards and services calls for wideband and high-resolution data-converters in wireless transceivers. While modern integrated circuits (IC) technologies provide high cut-off frequencies ( ) for transistors and hence allow the operation at higher speeds, the main limitation against increasing speed of operation of data-converters is the problem of clock-jitter. Clock-jitter is a common problem associated with clock generators due to uncertainty in the timing of the clock edges caused by the finite phase-noise (PN) in the generated clock waveform. Particularly, noise components induced by several noise sources in the system providing the clock (e.g. phaselocked loop, PLL) add to the clock waveform and cause uncertainty in the timing of the zero-crossing instants from cycle to cycle. Figure 1 shows a survey chart of the analog-todigital converter (ADC) implementations reported in IEEE International solid-state circuits conference (ISSCC) and VLSI Symposium since 1997 [1]. The straight lines show the limitation on the achievable signal-to-noise ratio (SNR) by clock-jitter for jitter root-mean square (rms) values of 1ps and 0.1ps. As can be seen from the chart, the performance of most ADCs falls below the line corresponding to 1ps rms jitter, few ADCs reside in the range between 1ps and 0.1ps, and almost all ADC implementations reported so far are beyond the 0.1ps rms jitter line. This means that the main limitation on increasing the ADC performance in terms of SNR and speed is the specification on the clock-jitter of 0.1ps.
Delta-sigma (ΔƩ) ADCs are the convenient choice in low power and state-of-the-art multistandard wireless receivers for two main reasons. First, they trade DSP for relaxed analog circuit complexity. Particularly, ΔƩ ADC implementations span analog and digital domains (ΔƩ pulse density modulation + digital decimation and filtering, as shown in Figure 2) and hence exploit DSP to relax hardware requirements on analog blocks. Thus, the simplified analog part (ΔƩ modulator) and the digital filtering can be efficiently reconfigured to fulfill performance requirements of different standards at minimum power consumption. Second, ΔƩ modulators use oversampling and hence trade speed for resolution. Specifically, for a given ΔƩ modulator and channel bandwidth (BW), higher effective number of bits (ENOB) can be achieved by increasing the oversampling ratio (OSR). This qualifies ΔƩ ADCs to benefit from increasing speeds of operation offered by advanced deep submicron CMOS technologies (maximum cutoff-frequency > 300 i n 4 5 n m [ 2 ] ) t o m e e t h i g h e r resolution requirements for modern and future wireless services at minimum power overhead. Continuous-time (CT) ΔƩ ADCs are widely used in wideband low power wireless receivers [3,4]. The CT operation of the loop filter relaxes the requirements on the gain-bandwidth product (GBW) of the adopted amplifiers and hence allows the operation at higher speeds or lower power consumption compared to discrete-time (DT) implementations. Also, CT loop filters offer inherent anti-aliasing and thus save the need for explicit anti-aliasing filter before the ADC. The requirements on the sample-and-hold (S/H) circuitry are also relaxed because the sampling is performed after the loop filter and hence the sampling errors experience the maximum attenuation offered by the loop (similar to quantization noise). However, CT ΔƩ modulators suffer from high sensitivity to clock-jitter in the sampling-clock of the digital-to-analog converters (DACs) in the feedback.
In this context, this chapter is intended to provide a comprehensive background and study for the effects of clock-jitter in the sampling-clocks of ΔƩ modulators. Also, Matlab/Simulink models for additive errors induced by clock-jitter in ΔƩ modulators are given so that to help designers characterize the sensitivities of various types of ΔƩ architectures to clock-jitter. The material in this chapter is organized as follows. Section 2 gives a general background about the types of errors caused by clock-jitter in different classes of switched circuits and signal waveforms. The critical sources of jitter induced errors in a ΔƩ loop are identified for DT and CT ΔƩ modulators and a comparison between the two types, in terms of sensitivity to clock-jitter, is done in Section 3. Section 4 provides detailed sensitivity analysis for CT ΔƩ modulators to clock-jitter in the feedback DAC sampling-clock. In Section 5, Simulink models, based on the analysis of Section 4, for the additive errors generated by clock-jitter in CT ΔƩ modulators are shown and the robustness of these models is verified by CT simulations in Matlab/Simulink. Simulations results show good agreement with the theoretical expectations. Finally, conclusions are drawn in Section 6.

Jitter problems: Background
Since digital data is always available in DT form, then any process of converting information from analog form to digital bit-stream or vice versa entails sampling. However, the clock signals driving sampling switches suffers clock-jitter due to the noise components that accompany the clock waveform. Figure 3 shows the PN density in a typical voltagecontrolled oscillator (VCO) 1 . In the time-domain, the integrated effect of these noise components results in random variations in the phase of the generated clock signal. In dataconverters, the problem of clock-jitter is a very critical issue and can significantly deteriorate the achievable SNR by several dBs. The problems resulting from clock-jitter are classified as follows:

Aperture jitter: Voltage sampling errors
In ADCs, it is desirable to convert CT voltage signals into DT form. Figure 4(a) shows a common track-and-hold (T/H) circuit based on a switch driven by a clock signal (samplingclock) and a sampling capacitor . Errors in the sampled voltage (during the tracking phase) value is one of the most common problems resulting from timing uncertainty ∆ (clock-jitter) in the sampling-clock. Particularly, on sampling an input voltage signal, random variations in the timing of the clock edges can result in an incorrect sampled signal, as illustrated in Figure 4(b). This effect is called aperture jitter. The noise induced by aperture jitter can be illustrated as follows. Suppose that a sinusoidal signal ( ), where is the amplitude and is the angular frequency, is to be sampled using a T/H circuit. Then, the error in the n th sample of the sampled signal due to a timing error ∆ ( ) is given by where is the sampling-period. If is the variance of the timing error ∆ , then the error power is given by Since the signal power of the sinusoid is given by 2 , the SNR due to aperture jitter is given by where = / 2 is the frequency. From (3) the SNR has the worst value at the edge of the signal band (largest value of frequency, ). The plots in Figure 5 show the limitation on the achievable SNR vs. the signal frequency due to aperture jitter for different values of the rms jitter .

Charge transfer jitter
Another effect of clock-jitter, called charge transfer jitter, shows up in circuits whose operation is based on charge transfer by switching. In particular, switched-capacitor (SC) circuits commonly used in DT ADCs and DACs suffer from charge transfer errors due to clock-jitter in the sampling clocks. Consider the simple non-inverting SC integrator in Figure  6(a). As shown by the time-domain waveforms in Figure 6(b), during integrating phase ∅ , the charge stored in a sampling capacitor is transferred to an integrating capacitor through the ON resistance ( ) of the switch. The discharging of takes place in an exponentially-decaying rate.
For a given clock-cycle , the instantaneous exponentially-decaying current ( ) resulting from the charge transfer from to can be derived as follows: where is the value of the peak current at the beginning of the pulse, and are the start and end times of the exponentially-decaying pulse normalized to the sampling period and is the discharging time-constant and is given by the product . The values of and are determined by the duty-cycle of the clock. In typical SC circuits, =0 . 5 and = Recall that the input voltage is sampled on during the first clock half-cycle (when ∅ is high) and then the charge on is transferred to during the second clock half-cycle (when ∅ is high). For a total charge of to be transferred during ∅ of clock-cycle , Thus, Substituting with (6) in (4) yields However, in presence of timing error ∆ ( ) in the pulse-width of the discharging phase ∅ , the resulting error in the integrated charge in the n th clock-cycle is given by which for ∆ ≪ can be approximated by If the variance of the timing error ∆ ( ), then the error power is given by where is the rms charge sampled on the sampling capacitor . Thus, the SNR due to charge transfer jitter caused by charge transfer jitter is given by  .
The plots in Figure 7 show the limitation on the achievable SNR vs. the signal frequency due to charge transfer jitter for different values of the rms jitter . Typical values of =0 . 5 and =1 have been considered. The results are provided for = 0.05 ,0.1 , and 0.2 . As can be seen from the plots in Figure 7, for a given clock frequency, the SNR limitation due to charge transfer jitter is much more relaxed compared to the aperture jitter error ( Figure 5). This result was expected because from equation (11), the effect of the jitter induced noise is reduced by an exponential factor indicating that charge transfer error in SC circuits should be less critical. This also can also be explained intuitively by noting that for the exponentially-decaying waveform in Figure 8, the amplitude of the pulse is rather low at the end of the clock-cycle and hence the amount of charge that varies over one clock period due to jitter is significantly reduced. However, for a given rms jitter and sampling frequency, the SNR limitation due to charge transfer jitter degrades as the discharging time-constant increases. This is because the value of the charge transfer current at the end of the clockcycle (discharge phase) is varying exponentially with , thus for a given timing error ∆ , the error in the amount of charge transferred is higher.

Pulse-width jitter
Continuous-time current-steering DAC, shown in Figure 9(a), is used to convert digital signals into CT analog pulses. Clock-jitter in the sampling-clock of a CT DAC modulates the pulse-width of the waveform at the DAC output. Called pulse-width jitter (PWJ), this problem generally shows up in circuits whose operation is based on current-switching, e.g. current-steering DACs, charge sampling circuits, and charge pumps. In systems using CT DACs (e.g. audio transmitters and CT ΔƩ modulators), the DAC is loaded by a CT filter stage that integrates the output current pulse from the DAC. The error in the amount of integrated charges is directly proportional to the timing error ∆ in the pulse-width, as illustrated by the time-domain waveform in Figure 9(b). If the clock-jitter causes timing errors ∆ with variance and the switched-current levels are ± , the variance of the charge transferred per clock-cycle is For a sinusoidal signal, the maximum signal power in terms of the integrated charge signal per clock-cycle is given by Thus, the maximum SNR against PWJ is given by   Thus, the SNR degradation by PWJ is less than that of the aperture jitter by a factor of 2 . The plots in Figure 10 show the limitation on the achievable SNR vs. the signal frequency due to PWJ problem for different values of the rms jitter . Figure 11 provides a comparative insight about the SNR limitation imposed by each one of the clock-jitter induced problems discussed above. It is worth noting that these plots are for Nyquist-rate sampling; however the foregoing analysis and results can be easily extended to include the effect of oversampling in oversampled circuits. As can be observed from the plots in Figure 11, for a given sampling frequency, the maximum limitation on the achievable SNR is caused by aperture jitter. However, the charge transfer jitter limits the SNR at very high frequencies; for example for an SNR of 80 dB, the charge transfer jitter starts to limit the achievable SNR at sampling frequency ≥1 for = 0.1 , and as mentioned before more robustness to charge transfer jitter at high frequencies can be obtained by reducing the discharging time-constant .

Sensitivity of ΔƩ modulators to clock-jitter
The purpose of this section is to address the effects of clock-jitter in the two main classes of ΔƩ modulators, shown in Figure 12, and provide a comparison between them in terms of sensitivity to clock-jitter. In order to determine the performance sensitivity to clock-jitter in DT and CT modulators, the critical sources of jitter induced errors in the loop should be identified in each one. The most critical clock-jitter errors in a ΔƩ modulator are those generated at the modulator input and in the feedback path through the outermost DAC feeding the first stage in the loop filter (recall that errors generated at inner nodes in the loop are suppressed by the previous stages of the loop filter).
The feedback signal is carrying a digital data (coming from the loop quantizer) and hence it is robust to aperture jitter 2 . However, depending on the type of the adopted feedback DAC, the feedback signal in a ΔƩ loop can suffer one of the other two kinds of jitter induced errors (namely, charge transfer jitter and PWJ). The effect of feedback jitter can be further discussed in the frequency domain with the aid of Figure 13 as follows. Recall that the modulator feedback signal includes the in-band desired signal (input signal) and the high-pass shaped noise. Since the sampling process ideally is a multiplication in time, the spectra of the analog input signal and the clock signal convolve. Thus, the error generated by DAC clock PN has two main components, as illustrated by Figure 13. First, the clock PN components close to the clock frequency modulates the in-band desired signal resulting in signal side-bands in the same manner like the PN of an upfront sampler [5]. Second, the wideband clock PN, modulates the high-pass shaped noise components and the modulation products fall over the desired band and hence elevate the in-band noise level.

DT ΔƩ modulators
In DT ΔƩ modulators, the sampling takes place at the modulator input. The SC integrator in Figure 14 is commonly used as an input stage for DT loop filters in ΔƩ modulators. The sampling aperture jitter errors due to the sampling switch (S1) will be added to the signal at the input and hence will directly appear at the modulator output without any suppression. As mentioned earlier, the feedback signal (VDAC) doesn't experience aperture jitter because the feedback signal is DT and also it has discrete amplitude levels. Thus, timing errors cannot result in a sampled value that is different from the original feedback one. Timing errors at switch S2 cause charge transfer jitter errors being added at the input stage. However, the charge transfer jitter errors at S2 are very small owing to the high robustness of the exponentially-decaying waveform to clock-jitter and moreover of the switches are usually very small resulting in a small time-constant which gives more jitter robustness to the waveform (recall the analysis given in the previous section).
According to the above discussion, the jitter induced noise in DT ΔƩ modulators is mainly dominated by the aperture error at S1. At a given sampling speed, the only way to improve the performance of DT ΔƩ modulators is to improve the jitter performance of the clock generator which translates into significant increase in the total power consumption in case of ΔƩ ADCs targeting high resolution. On the other hand, for a given rms jitter, if the sampling frequency is reduced for the sake of improving tolerance to jitter errors, then to achieve high resolution at the resulting low OSR, the filter order and/or the quantizer levels need to be increased. This translates into significant power penalty too. Moreover, this approach wouldn't work for state-of-the-art wireless standards with continuously increasing channel bandwidths.

CT ΔƩ modulators
In CT ΔƩ modulators, sampling occurs after the loop filter and hence sampling errors including aperture jitter are highly suppressed when they appear at the output because this is the point of maximum attenuation in the loop. However, CT ΔƩ implementations suffer from jitter errors added to the feedback signal. Particularly, in a CT ΔƩ modulator the DAC converts the quantizer output DT signal into CT pulses. The waveform coming from the CT DAC is fed to the loop filter to be integrated in the CT integrator stages. Thus, PWJ in the DAC waveform causes uncertainty in the integrated values at the outputs of the loop filter integrators. Rectangular waveform DACs are commonly used in CT ΔƩ structures due to their simple implementation and the relatively relaxed slew-rate (SR) requirement they offer for the loop filter amplifiers. Return-to-zero (RZ) DACs are the most sensitive to feedback PWJ because the random variations are affecting the rising and falling edges of the waveform at every clock-cycle. The jitter sensitivity can be slightly reduced by using a NRZ DAC because in this case, the clock-jitter will be effective only during the clock edges at which data is changing. The equivalent input-referred errors induced by clock jitter in RZ and NRZ waveforms for a certain sequence of data are illustrated in Figure 15.
As mentioned earlier, clock-jitter errors added in the feedback path are the most critical because they entail random phase-modulation that folds back high-pass shaped noise components over the desired channel. For typical wideband CT ΔƩ modulators with NRZ current steering DACs in the feedback, the error induced by the PWJ in the DAC waveform can be up to 30% -40% of the noise budget [3,4,6].
Convenience for low power implementations: CT ΔƩ modulators have gained significant attention in low power and high speed applications because they can operate at higher speed or lower power consumption compared to DT counterparts. Recall the relaxed gain bandwidth (GBW) product requirements they add on the loop filter amplifiers compared to DT implementations in which the loop filter is processing a DT signal and hence a GBW requirement on the amplifier is typically in the range of five times the sampling frequency.
Moreover, sensitivity of CT ΔƩ modulators to DAC clock-jitter can be minimized by processing the DAC pulse or modifying its shape so as to alleviate the error caused by the DAC clock jitter [7]. That is, the achievable SNR of a CT ΔƩ modulator can be improved against clock-jitter without having to improve the jitter performance of the clock generator or to reduce the sampling speed and increase the order of the loop filter or the quantizer resolution. This definitely translates into power savings because it avoids increasing the complexity of the clock generator or the ΔƩ modulator and hence avoiding extra power penalties 3 . 3 This is provided that the solution adopted to improve the DAC tolerance to clock jitter errors is not adding high power overhead and thus not increasing the total power consumption.

Analysis of jitter effects in CT ΔƩ modulators
This section provides detailed analysis for the effects of DAC clock-jitter on the performance of CT ΔƩ modulators for the most commonly used DAC types.

Return-to-zero DAC waveforms
Return-to-zero DAC waveforms are known to be robust to even-order nonlinearities resulting from mismatch between rise and fall times, as well as less sensitive to excess loop delay in the quantizer compared to NRZ waveforms [3]. However, as mentioned in previous section, they are the most sensitive to PWJ because the additive jitter induced errors are linearly proportional to the random timing errors at the rise and fall edges every clock-cycle, as illustrated in Figure 15(a). The equivalent error induced by PWJ in a RZ DAC waveform is given by where ∆ ( ) is the area difference resulting from the error in the total integrated charge per one clock period between the ideal and the jittered waveforms, ( ) is the modulator output at the n th clock cycle, is the duty-cycle of the RZ pulse, and ∆ ( ) and ∆ ( ) are the random timing errors in the rise and fall edges, respectively, of the n th DAC pulse. The amplitude of the DAC pulse varies inversely proportional with the pulse duty-cycle so that to supply a constant amount of charge (determined by Full-Scale (FS) voltage level of the quantizer) to the loop filter per clock-cycle. Following the procedure in [7], for a single tone • ( ) at the input of the ΔƩ modulator, the integrated in-band jitter-induced noise power (IBJN) for a RZ DAC is given by where is the rms jitter in the DAC sampling-clock, is the oversampling ratio of the modulator, ∆ is the quantization step of the loop quantizer, and is the noise transferfunction of the modulator. From equation (16), the expressions for the IBJN due to input signal and shaped quantization noise can be written as follows (17) From the expression in (16), it is evident that the IBJN decreases proportionally with the OSR and the duty cycle of the DAC pulse. Particularly, 1) as the OSR increases, the power spectral density (PSD) of the PWJ induced errors is reduced and hence the resulting integrated in-band noise is decreased accordingly, 2) the additive error in the amount of integrated charge in the loop filter varies linearly with the PWJ at the rise and fall edges by a factor roughly equal to the pulse amplitude (Figure 15(a)), which is inversely proportional to . The IBJN due to inband signal component, given in (17), causes sidebands of the input signal to appear in the desired band. Also, from (18), PWJ randomly modulating shaped noise results in noise folding back over the desired band and hence elevating the in-band noise level. In (16) and (18), the effect of the quantizer resolution is implicitly included in ∆ .

Non-return-to-zero DAC waveforms
Non-return-to-zero DACs are known to be highly sensitive to excess loop delay and also they result in even-order nonlinearities due to mismatch between rise and fall times, in contrast to RZ DAC waveforms. However, they are commonly used in CT ΔƩ modulators due to their simple implementation, relaxed SR requirement on the integrating amplifiers, and lower sensitivity to clock-jitter compared to RZ DACs. As illustrated by Fig. 15(b), in NRZ waveforms the clock-jitter will be effective only during the clock edges at which data is changing. Equivalent error induced by clock-jitter in a NRZ waveform is given by where ∆ ( ) is the random timing error in the clock edge of the n th clock-cycle. From [7], for a single tone • ( ) at the input of the ΔƩ modulator, the total IBJN for a NRZ DAC is given by where is the input signal bandwidth, is the ratio of the sampling frequency to double the input signal frequency, and , = •(1−cos ) .
Thus, the expressions for the IBJN due to input signal and shaped quantization noise can be written as follows From the expression in (21), the IBJN due to signal is inversely proportional with the OSR because, intuitively, as the OSR increases, less signal-related transitions will occur at the modulator output and hence less additive jitter noise will be generated. This note is applicable only to transitions at the modulator output in the frequency range of the input signal. For example, in case of DC inputs, the modulator output will exhibit limit cycles and yields discrete tones at the output spectrum [8]; however, these transitions at the output waveform are due to the shaped quantization noise and not the input signal. On the other hand, from (22), the IBJN due to shaped noise increases proportionally with the OSR because a higher OSR means more OOB shaped noise components will be modulated and fold back over the desired channel by the PN components at their respective frequencies.
Therefore, the OSR needs to be optimized for better robustness to PWJ according to the contribution of each component (in-band signal and shaped noise). Also, the IBJN due to shaped noise is proportional to , , and thus to minimize the PWJ, the aggressiveness of the NTF needs to be relaxed. This gives a trade-off between quantization noise suppression and sensitivity to PWJ and hence a compromise is needed.

Switched-capacitor-resistor DACs with exponentially-decaying waveforms
A commonly used solution to alleviate DAC sensitivity to PWJ is the switched-capacitorresistor (SCR) DAC with exponentially-decaying waveform, shown in Figure 16. The exponentially-decaying waveform (Figure 8) of the SCR DAC makes the amount of charge transferred to the loop per clock-cycle less dependent on the exact timing of the DAC clockedges [4,9]. For a given clock-cycle , the instantaneous exponentially-decaying current ( ) resulting from the charge transfer is given by equation (4). Recall that the feedback value is sampled on during the first clock half-cycle (when ∅ is high) and then the sampled voltage is transferred to loop filter during the second clock half-cycle (when ∅ is high). For a total integrated charge of • ( ) • to be delivered by the SCR DAC during ∅ of clock-cycle , where is the feedback DAC gain coefficient. Therefore, However, in presence of timing error ∆ ( ) in the pulse-width of the discharge phase ∅ in the n th clock cycle, the equivalent input-referred additive error in the integrated charge is given by which for ∆ ( ) ≪ can be approximated by If is the variance of the timing error ∆ ( ), then for a single tone • ( ) at the input of the ΔƩ modulator, the power of the input-referred IBJN is given by The expressions for the IBJN due to input signal and shaped quantization noise are given by As expected, the sensitivity of SCR DACs to PWJ, given by (27)-(29) is the same as the RZ DAC case (16)-(18) but exponentially reduced. However, the increased peak current of the SCR DAC, given by (28), adds higher requirements on the SR and the GBW of the loop filter integrator [4,10]. Moreover, CT ΔƩ modulators using SCR DACs have poor inherent antialiasing compared to those using current-steering DACs [11] due to the loading of the SCR DAC on the integrating amplifier input nodes. The hybrid SI-SCR DAC solution in [12] provides suppression to PWJ noise equivalent to that offered by SCR DACs without adding extra requirements on the SR or GBW of the integrating amplifier.

Modeling and simulation of Jitter effects in CT ΔƩ modulators using Matlab/Simulink
In this section, Matlab/Simulink models for the jitter induced errors in different DAC types are shown. The models are based on the expressions of the additive jitter errors developed in the previous section and will be verified by simulations. Figure 17 shows the Simulink models for RZ, NRZ and SCR DACs, including the additive jitter errors based on the expressions in (15), (19), and (25), respectively. Note that these additive errors in the feedback should be multiplied by the gain coefficient of their respective feedback path. These models are examined through simulations in Matlab/Simulink to verify their accuracy and compliance with the developed analysis. The feed-forward third-order single-bit CT ΔƩ modulator in Figure 18 is used as a test vehicle for the system-level simulations. The modulator operates at an OSR of 100 with a target ENOB of 13 bits over a baseband channel bandwidth of 1.92 MHz for the WCDMA standard. The noise budgeting for the ADC to achieve the required ENOB is given in Table 1. Table 2 lists the specifications and summary of the achievable performance of the modulator when an SCR DAC model is used with DAC time-constant = 0.1 . Recall that an SCR DAC is a convenient option to provide robustness to clock-jitter and maintain the low percentage of the jitter induced noise in the noise budget. The dynamic-range (DR) and PSD plots of the modulator are given in Figure 19 and Figure 20. The maximum signal-tonoise-plus-distortion ratio (SNDR) is calculated as 80dB.
To examine the sensitivity of the modulator to clock-jitter for different DAC types by simulations, the appropriate model for the feedback DAC including the additive jitter errors is chosen from the ones in Figure 17, according to the adopted DAC type (RZ, NRZ, or SCR), and is added to the Simulink model of the complete modulator. The plots in Figure 21 imply that for sufficiently large rms jitter in the DAC sampling-clock, the IBJN increases significantly and dominate the total in-band noise (IBN). For the SCR DAC, it can be seen from the plots in Figure 21(c) that the robustness to clock-jitter degrades proportionally with the DAC time-constant , as discussed earlier in the analysis. To compare the robustness to clock-jitter in the three DAC types, IBJN plots are combined together in Figure 22, and it is evident that the SCR DAC is the most tolerant to DAC jitter while RZ DAC is the most sensitive. Figure 18. Adopted modified feed-forward CT single-bit ΔƩ modulator.  Table 2. Modulator specifications and performance summary Figure 19. Dynamic-range of the adopted ΔƩ modulator.

Conclusion
In this chapter, the effects of clock-jitter in the sampling-clocks of ΔƩ modulators are analyzed and studied in details. The critical sources of jitter induced errors in a ΔƩ loop are discussed for ΔƩ modulators with DT and CT loop filters. The comparison between DT and CT modulators showed that CT architectures are more sensitive to clock-jitter than DT counterparts due to PWJ in the feedback signal caused by clock-jitter in the DAC samplingclock. In essence, PWJ in the feedback waveform entails random phase-modulation that folds back high-pass shaped noise components over the desired channel bandwidth. Thus, a detailed analysis for the sensitivities of various signal waveforms provided by different types of CT DACs to clock-jitter is given thereafter. Also, efficient Matlab/Simulink models for additive errors induced by clock-jitter in the feedback DACs are shown so that to help designers characterize the sensitivities of various types of CT ΔƩ architectures to clock-jitter and obtain the specification requirement on the rms jitter of the sampling-clock for a given target performance. Furthermore, modeling of jitter induced errors is beneficial for systemlevel simulations adopted in the process of developing efficient solutions and modulator or DAC architectures that can remedy the effects of clock-jitter on the ΔƩ modulator performance. The robustness of these models is verified by CT simulations in Matlab/Simulink and simulations results show good agreement with the theoretical expectations.