Sum-Product Decoding of Punctured Convolutional Code for Wireless LAN

The next generationwireless Local AreaNetwork (LAN) standard (IEEE802.11n) aims for high rate data transmission such as 100Mbps to 600Mbps. In order to implement that rate, high speed decoder for the convolutional code for the wireless LAN standard is necessary. From the viewpoint of high speed decoder, sum-product algorithm is an attractive decoding method, since decoding rule of sum-product algorithm is simple and sum-product algorithm is suit for parallel implementation. Furthermore, sum-product decoding is a soft-in soft-out decoding. The combined use of sum-product algorithm and another soft-in soft-out processing may provide good performance such as turbo equalization (Douillard et al., 1995; Laot et al., 2001). However, sum-product decoding for the convolutional code of the wireless LAN can not provide good performance. To improve the performance, the sum-product decoding method for the non-punctured convolutional code of the wireless LAN has been proposed (Shohon et al., 2009b; 2010). In the wireless LAN, however, punctured convolutional codes are also used. Therefore, this paper proposes sum-product decoding methods for the punctured convolutional codes of the wireless LAN.


Introduction
The next generation wireless Local Area Network (LAN) standard (IEEE802.11n)aims for high rate data transmission such as 100Mbps to 600Mbps.In order to implement that rate, high speed decoder for the convolutional code for the wireless LAN standard is necessary.From the viewpoint of high speed decoder, sum-product algorithm is an attractive decoding method, since decoding rule of sum-product algorithm is simple and sum-product algorithm is suit for parallel implementation.Furthermore, sum-product decoding is a soft-in soft-out decoding.The combined use of sum-product algorithm and another soft-in soft-out processing may provide good performance such as turbo equalization (Douillard et al., 1995;Laot et al., 2001).However, sum-product decoding for the convolutional code of the wireless LAN can not provide good performance.To improve the performance, the sum-product decoding method for the non-punctured convolutional code of the wireless LAN has been proposed (Shohon et al., 2009b;2010).In the wireless LAN, however, punctured convolutional codes are also used.Therefore, this paper proposes sum-product decoding methods for the punctured convolutional codes of the wireless LAN.
A sum-product decoding method for convolutional codes has been introduced in (Kschischang et al., 2001).The sum-product algorithm uses a Wiberg-type graph that represents a code trellis with hidden variables as code states and visible variables as code bits.In this case, the Wiberg-type graph is equivalent to the code trellis and the sum-product algorithm becomes precisely identical to BCJR algorithm (Berrou, C. et al.;C;Kschischang et al., 2001).This method only gives interpretation of BCJR algorithm as sum-product algorithm.To avoid confusion, the method of (Kschischang et al., 2001) is referred to as BCJR.This paper deals with sum-product algorithm that uses a Tanner graph that represents a parity check matrix of the code.This sum-product algorithm is the same as that for Low-Density Parity-Check code (Gallager, 1963;MacKay, 1999).The sum-product decoding method for recursive systematic convolutional codes has been proposed in (Shohon et al., 2009a).In the wireless LAN, the non-systematic convolutional code is used.For the non-punctured convolutional code of the wireless LAN, the sum-product decoding method has been proposed in (Shohon et al., 2009b;2010).In this paper, for punctured codes of the wireless LAN, sum-product decoding methods are proposed.

Non-punctured code
The convolutional code for the wireless LAN is a non-systematic code with rate 1/2 (IEEE Std 802.11, 2007).Let a sequence of information bits be denoted by x 0 , x 1 , ••• , x N−1 ,as e q u e n c e of parity bits 1 be denoted by p 1,0 , p 1,1 , ••• , p 1,N−1 , and a sequence of parity bits 2 be denoted by p 2,0 , p 2,1 , ••• , p 2,N−1 .Polynomial representation for each sequence is as follows. (1) Parity bit polynomials are given by For the wireless LAN standard, G 1 (D) and G 2 (D) are given by Polynomials X(D), P 1 (D), P 2 (D) are also represented by X, P 1 , P 2 in this paper.

Punctured code
In this section, puncturing method for wireless LAN will be explained.Puncturing is a procedure for omitting some of the encoded bits in the transmitter.The effect from puncturing will reducing the number of transmitted bits and increasing the coding rate.From Equation 4∼ Equation 5, we can obtain following equations.
Let left parts of Equation 8 and Equation 9 be defined as parity check polynomial.
The degree of a parity check polynomial is denoted by ν, that is the maximum degree of coefficients of the polynomial.For example, since coefficients of H org,1 (X, P 1 ) are {G 1 (D),1}, the maximum degree is ν = 6 that is the maximum degree of G 1 (D).

Tanner graph of convolutional code
From Equation 12, parity check equations at k and k + 1 time slots are given by Those equations are corresponding to check nodes C k and C k+1 , of the tanner graph.The part of tanner graph corresponding to those parity check equations is as shown in Fig. 2.

Algorithm
For convenience, bit node is denoted by u n such that where information bit is x n and parity bits are p  Each message V m,n is set to the initial value as follows.
where, r n denotes received signal, σ 2 denotes variance of additive white Gaussian noise and λ n is channel value.
Step2.Message from check node to bit node Each check node C m updates the message on bit node u n by gathering all incoming messages from other bit nodes that connected to check node C m .Message U m,n is calculated by following equation (Gallager, 1963;Hagenauer, 1996;Richardson et al., 2001).
where, N (m) denotes the set of bit node numbers that connect to the check node C m and f s is a scaling factor.This factor is used in the proposed method described later.When f s is not specified, f s = 1.
Step3.Message from bit node to check node Each bit node n propagates its message to all check nodes that connect to it.
where M(n) denotes the set of check node numbers that connect to the bit node, u n .
Step4.Tentative estimated code word computation By summing up all the messages from all check nodes connected to a bit node, the a posteriori value Λ n can be obtained by 4 Advanced Wireless LAN www.intechopen.com The extrinsic value, L e (u n ),ofbitnodeu n can be obtained by The tentative estimated bit u ′ n can be obtained by Step5.Stop criterion Tentative estimated code word u ′ obtained in Step 4 is checked against the parity check matrix H.I fH multiplied by Tentative estimated code word u ′ T equal to zero vector, the decoder stop and outputs u ′ , if not, it repeats Steps 2-5.
If maximum iteration number of decoding is set, the tentative estimated code word u ′ outputs after decoding procedure repeat the process until the maximum iteration is reached.

Sum-product decoding for wireless LAN (conventional method)
This section will give summary of (Shohon et al., 2009b;2010).Sum-product decoding can be performed by using Equation 10and Equation 11as parity check polynomials.However, the decoding provides bad performance.Since the code under consideration is a non-systematic code, there are no received signals corresponding to information bits and channel values for information bits are zero.It can be seen from Equation 10, Equation 11 that each check node has more than one information bit connections.Therefore reliability increment at check node cannot be obtained.Consequently, conventional sum-product algorithm cannot realize good performance.To improve the sum-product decoding performance, I have proposed the 2-step decoding method (Shohon et al., 2009b;2010).

2-Step decoding
The 2-step decoding method is as follows.
(1) Only parity bits are decoded by sum-product algorithm.

Decoding parity bits
The parity check equation is derived from Equation 4∼ Equation 5 as follows.
The left part of the equation is defined as parity check polynomial H(P 1 , P 2 ).
Parity bits P 1 and P 2 can be decoded by sum-product algorithm based on parity check polynomial given by Equation 25.By using the decoded parity bits, information bits can be regenerated.

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Sum-Product Decoding of Punctured Convolutional Code for Wireless LAN www.intechopen.com

Decoding information bits
Decoded information bit X can be obtained by Equation 26with decoded parity bits P1 , P2 . where, From Equation 26, Equation 27, and Equation 28, it can be seen that information bit can be regenerated by using a non-recursive convolutional encoder with input P1 , P2 and output X as shown in Fig. 3.

Higher degree parity check polynomial
I have proposed to use higher degree parity check polynomial to obtain further performance improvement (Shohon et al., 2009b;2010).
The method is a sum-product decoding with higher degree parity check polynomial than that of the original parity check polynomial.In this section, the method is applied to improve the sum-product decoding performance for parity bits.The higher degree parity check polynomial is denoted by H ′ (P 1 , P 2 ),thatisgivenby where M(D) is a non-zero polynomial.Among possible higher degree parity check polynomials, we aim to select the optimum higher degree parity check polynomial by experiments and to use it for sum-product decoding.However, the number of prospective objects becomes too much when we include all possible higher degree parity check polynomials in the experimental objects.Therefore, we limit the range of degree of higher degree parity check polynomials (ν ≤ 16).For those higher degree parity check polynomials, we further limit the prospective objects by using n fc , that is the number of four-cycles per one check node (Shohon et al., 2009a).For every degree of higher degree parity check polynomial, we select the higher degree parity check polynomial that has the minimum n fc among higher degree parity check polynomials of object degree and include it in the experimental objects.By this means, Experimental result shows that higher degree parity check polynomial of degree ν = 13 provides the best performance.The higher degree parity check polynomial is given by

Simulation results for non-punctured code
Simulation condition is shown in

Simulation results for punctured codes
For non-punctured code, higher degree parity check polynomial with degree ν = 13 provides the best performance.With that higher degree parity check polynomial, for punctured codes with code rates 2/3 and 3/4, the sum-product decoding simulation were executed.The simulation results are shown in Fig. 5 and Fig. 6.
From Fig. 5 and Fig. 6, it can be seen that the conventional method, that is sum-product decoding with higher degree parity check polynomial with ν = 13, can not provide good performance for punctured code with code rates 2/3 and 3/4.I inferred that the bad sum-product decoding performance for punctured codes is caused by more than one punctured bits included in the parity check equation at time slot k.T h er e a s o n is as follows.Since received signals are not available for punctured bits, the channel values for punctured bits are zero.This causes that every messages from punctured bit node to check node are zero.In this case, like stopping set (Di et al., 2002), messages from the check node to bit nodes are zero.Therefore, sum-product algorithm does not work.
In order to improve the sum-product decoding performance, this paper proposes to use parity check equation that includes single punctured bit.The condition to include single punctured bit in parity check equation is referred to as single punctured bit condition.If single punctured bit is included in a parity check equation at time slot k, the message to the corresponding bit node can be obtained from the corresponding check node C k .I nt h i sc a s e , sum-product algorithm can work.Therefore, we expect that using higher degree parity check polynomial such that parity check equation includes single punctured bit, brings performance improvement of sum-product decoding of punctured codes.

Higher degree parity check polynomial satisfying single puncture bit condition
In this section, single punctured bit condition is derived for higher degree parity check polynomial.A higher degree parity check equation is given by From Equation 36, Equation 37 and Equation 38, parity check equation at time slot k is represented by

Code rate 2/3
For code rate 2/3, punctured bits are From Equation 39and Equation 40, it can be seen that punctured bits included in parity check equation at time slot k satisfies Therefore, we obtain For time slot k = 2l, l = 0, 1, 2, •••, Therefore, the set {α i | (α i mod 2)=1} in higher degree parity check polynomial corresponds to punctured bits in the parity check equation at time 46is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot k = 2l, l = 0, 1, 2, •••.
where #{x} denotes the number of elements in the set {x}.
Advanced Wireless LAN www.intechopen.comTherefore, if either Equation 46or Equation 47 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition.

Code rate 3/4
For code rate 3/4, punctured bits are From Equation 39and Equation 48, it can be seen that punctured bits included in parity check equation at time slot k satisfies Therefore, we obtain 51) From Equation 52, it can be seen that the set {β i | (β i mod 3)=1} in higher degree parity check polynomial corresponds to punctured bits of parity bit P 1 in the parity check equation at time slot k = 3l, l = 0, 1, 2, •••.From Equation 54, it can be seen that the set {α i | (α i mod 3)= 2} in higher degree parity check polynomial correspond to punctured bits of the parity bit P 2 in the parity check equation at time slot k = 3l, l = 0, 1, 2, •••.
Similarly, if either Equation 57 or Equation 58 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot 11 Sum-Product Decoding of Punctured Convolutional Code for Wireless LAN www.intechopen.com Similarly, if either Equation 59or Equation 60 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot k = 3l + 2, (l = 0, 1, 2, •••).

Search of higher degree parity check polynomial for decoding
In this paper, basically, the higher degree parity check polynomials for decoding are searched as follows.
Step.1 Select higher degree parity check polynomials with degree ν ≤ 21 that satisfies single punctured bit condition.
Step.2Among those higher degree parity check polynomials, select the higher degree parity check polynomial that provides the best sum-product decoding performance by using computer simulation.

Code rate 2/3
In the Step.1, 208 higher degree parity check polynomials satisfy single punctured bit condition.Since many higher degree parity check polynomials are selected, they are limited by n fc .In this paper, among those higher degree parity check polynomials, 9 higher degree parity check polynomials with lower n fc are selected.They are shown in Table 3.The simulation results of Step.2 with higher degree parity check polynomials in Table 3 are shown in Fig. 7. Simulation condition is shown in Table 2 and E b /N 0 = 5.0 [dB].From Fig. 7, it can be seen that higher degree parity check polynomial of No.5 with scaling factor f s = 0.9 provides the best performance.For code rate 3/4, there are both puncture bits of parity P 1 and parity P 2 .Decodable punctured parity bit by sum-product algorithm with certain parity check equation is either parity P 1 or parity bit P 2 .From the viewpoint of decodable parity bit, single punctured bit condition can be arranged as follows.
1.If either Equation 55 or Equation 57, or Equation 59 is satisfied, the higher degree parity check polynomial includes single punctured bit of parity P 1 .Therefore, with the higher degree parity check polynomial, punctured bits of parity P 1 can be decoded.That higher degree parity check polynomial is referred to as higher degree parity check polynomial for P 1 .56or Equation 58 or Equation 60 is satisfied, the higher degree parity check polynomial includes single punctured bit of parity P 2 .Therefore, with the higher degree parity check polynomial, punctured bits of parity P 2 can be decoded.That higher degree parity check polynomial is referred to as higher degree parity check polynomial for P 2 .

If either Equation
Therefore, for code rate 3/4, both higher degree parity check polynomials for P 1 and P 2 are necessary to decode.
For code rate 3/4, there are 16 higher degree parity check polynomials for P 1 and 16 higher degree parity check polynomials for P 2 .The number of combination of higher degree parity check polynomial for P 1 and that for P 2 is many.Therefore, they are limited by n fc .H i g h e r degree parity check polynomials that have lower n fc are selected as shown in Table 4 and Table 5.A block diagram of the decoder for code rate 3/4 is shown in Fig. 8.It is similar to a turbo decoder.In Fig. 8, DEC1 is sum-product algorithm decoder with higher degree parity check polynomial for P 1 and DEC2 is sum-product algorithm decoder with higher degree parity check polynomial for P 2 .Channel value is denoted by λ n .Extrinsic values of DEC1 and DEC2 are denoted by L e1 (u n ) and L e2 (u n ), respectively.A posteriori value of DEC2 is denoted by Λ 2,n .
In DEC1, L e2 (u n ) is added to λ n as follows.
The value λ ′ n is used as initial value of λ n in Equation 17.Similarly, in DEC2, L e1 (u n ) is added to λ n and that value is used as initial value of λ n .I n computer simulation, the number of iteration of sum-product algorithm at each decoder was set to 1.The maximum number of iteration between two decoders was set to 200.Other simulation conditions are the same as shown in Table 2. From Fig. 9, it can be seen that the combination of higher degree parity check polynomials No.2 and No.3 with scaling factor f s = 0.5 provides the best decoding performance.From Fig. 10 it can be seen that the parity bit error rate performance of the single punctured bit method is 1.12[dB] superior to that of the conventional method (higher degree parity check polynomial of ν = 13) at bit error rate 10 −5 .The parity bit error rate performance of the single punctured bit method is only 0.83 [dB] inferior to that of BCJR.
From Fig. 10, information bit error performance of the single punctured bit method is 1.28 [dB] superior to that of the conventional method at bit error rate 10 −5 .The information bit error rate performance of the single punctured bit method is only 0.98 [dB] inferior to that of BCJR. Figure 11 shows parity bit error rate performance of the single punctured bit method for code rate 3/4.From Fig. 11 it can be seen that the parity bit error rate performance of the single punctured bit method is 0.82 [dB] superior to that of the conventional method (higher degree parity check polynomial of ν = 13) at bit error rate 10 −5 .The parity bit error rate performance of the single punctured bit method is 3.24[dB] inferior to that of BCJR.
Figure 12 shows information bit error rate performance of the single punctured bit method.From Fig. 12, it can be seen that the information bit error rate performance of the single punctured bit method is 1.11[dB] superior to the conventional method at bit error rate 10 −5 .The information bit error rate performance of the single punctured bit method is 4.11 [dB] inferior to that of BCJR at bit error rate 10 −5 .

Switching parity check method (proposed decoding method (2))
For code rate 3/4, the proposed method (1) can not provide good performance.Therefore, this paper try to improve the sum-product decoding performance for code rate 3/4.
Single punctured bit BCJR Fig. 12. Information bit error rate performance of single punctured bit method for code rate 3/4 I inferred that the bad decoding performance is caused by the four-cycles of higher degree parity check polynomial, since n fc of higher degree parity check polynomial satisfying single punctured bit condition tends to be larger than n fc of higher degree parity check polynomial that does not satisfy single punctured bit condition.Therefore, this paper proposes following method.Only at first iteration, the higher degree parity check polynomial satisfying single punctured bit condition is used to decode and after first iteration, another higher degree parity check polynomial without single punctured bit condition is used to decode.By decoding, only at first iteration, with higher degree parity check polynomial satisfying single punctured bit condition, the a posteriori values of punctured bits are obtained.After obtaining the a posteriori values of punctured bit, the higher degree parity check polynomial with lower n fc may provide good bit error rate performance.
Figure 13 shows a block diagram of decoder of the switching parity check method.In Fig. 13, DEC1 is a sum-product algorithm decoder with higher degree parity check polynomial for P 1 , DEC2 is a sum-product algorithm decoder with higher degree parity check polynomial for P 2 and DEC3 is a sum-product algorithm decoder with higher degree parity check polynomial with lower n fc for iteration.Chanel values for DEC1, DEC2 and DEC3 are λ 1,n , λ 2,n and λ 3,n , respectively.A posteriori values of DEC1, DEC2 and DEC3 are Λ 1,n , Λ 2,n and Λ 3,n , respectively.Decoders DEC2 and DEC3 use the a posteriori value of previous decoder as the channel value.

Search of higher degree parity check polynomial for decoding
This paper searches higher degree parity check polynomials for DEC1, DEC2 and DEC3 by computer simulation.In this paper, the higher degree parity check polynomials for DEC1, DEC2 and DEC3 were selected from Table 4, Table 5 and Table 1, respectively.There are many number of combination of the higher degree parity check polynomials.Therefore, this paper searches the higher degree parity check polynomials as follows.
Step.1 At first, the higher degree parity check polynomial for DEC3 is determined by decoding simulation with only DEC3.
Step.2With the determined higher degree parity check polynomial for DEC3, the higher degree parity check polynomials for DEC1 and DEC2 are determined by decoding simulation with DEC1, DEC2 and DEC3.
Figure 14 shows the simulation results of Step.1 at E b /N 0 = 6[dB].From Fig. 14, it can be seen that the higher degree parity check polynomial with ν = 15 provides the best performance.Therefore, that higher degree parity check polynomial is used.
Figure 15 shows the simulation results of Step.2 at E b /N 0 =7 [dB].From Fig. 15, it can be seen that the combination of higher degree parity check polynomials No.2 and No.5 with scaling factor f s = 0.1 provides the best performance, where scaling factor f s = 0.1 is used for DEC1 and DEC2, and DEC3 uses fixed scaling factor f s = 1.

Fig. 8 .Figure 9
Fig. 8. Block diagram of decoder of single punctured bit method for code rate 3/4 Figure 9 shows the simulation results of Step.2 for code rate 3/4 at E b /N 0 = 6[dB].

Fig. 11 .
Fig. 11.Parity bit error rate performance of single punctured bit method for code rate 3/4

Fig. 13 .
Fig. 13.Block diagram of decoder of switching parity check method for code rate 3/4 Fig. 14.Simulation results of step.1 in switching parity check method at E b /N 0 = 6[dB]

Table 1 .
Table 1 was obtained.Examined higher degree parity check polynomials for code rate 1/2

Table 2
. Hereafter, this condition was used, if simulation condition is not specified.Figure4shows simulation results.The figure shows that the performance for information bits of 2-Step Decoding with higher degree parity check polynomial (denoted by conventional) is only 0.7[dB]inferior to that of BCJR at bit error rate 10 −5 .

Table 2 .
Simulation condition

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Sum-Product Decoding of Punctured Convolutional Code for Wireless LAN www.intechopen.comGenerally, polynomials G ′ 1 (D) and G ′ 2 (D) are given by

Table 3 .
Examined higher degree parity check polynomials for code rate 2/3

Table 4 .
Examined higher degree parity check polynomials for P 1