Nanowires: Promising Candidates for Electrostatic Control in Future Nanoelectronic Devices

The microelectronics activity regroups the study, design, and manufacturing of very small electronic components. These devices are essentially based on interconnected transistors, sort of “switches” which allow controlling the electric current, and are made of semiconductor materials. Depending on the voltage applied to its “gate” electrode, a transistor is in ON state (high current) or OFF state (smallest possible current and low power consumption). Since the invention of the first transistor in 1948, technological progress allowed miniaturizing drastically electronic circuits, and the industry grew fast up to now. For example, the first microprocessor of INTEL (the “4004”) contained 2300 transistors while the Pentium 4 in the early 2000’s got 55 millions of transistors and the dual core more than 150 millions. To have a clear idea on the fast growing of this industry, in the 60’s and 70’s, the number of transistors in integrated circuits was doubled every year. Since the 80’s, the standard rule is a factor 2 every 18 months. This evolution is more known as the “Moore’s law”. Of course, such an industry implies several companies. Microelectronics is become very competitive in performances as well as for economical aspects. The price of 1 million of transistor was 75000 € in 1973, while it was of 6 cents in 2000 then 0.5 cent in 2005. The common objective in microelectronics is so to go ahead with the improvement of transistor in all aspects (electronic performances and economical).


Introduction
The microelectronics activity regroups the study, design, and manufacturing of very small electronic components.These devices are essentially based on interconnected transistors, sort of "switches" which allow controlling the electric current, and are made of semiconductor materials.Depending on the voltage applied to its "gate" electrode, a transistor is in ON state (high current) or OFF state (smallest possible current and low power consumption).Since the invention of the first transistor in 1948, technological progress allowed miniaturizing drastically electronic circuits, and the industry grew fast up to now.For example, the first microprocessor of INTEL (the "4004") contained 2300 transistors while the Pentium 4 in the early 2000's got 55 millions of transistors and the dual core more than 150 millions.To have a clear idea on the fast growing of this industry, in the 60's and 70's, the number of transistors in integrated circuits was doubled every year.Since the 80's, the standard rule is a factor 2 every 18 months.This evolution is more known as the "Moore's law".Of course, such an industry implies several companies.Microelectronics is become very competitive in performances as well as for economical aspects.The price of 1 million of transistor was 75000 € in 1973, while it was of 6 cents in 2000 then 0.5 cent in 2005.The common objective in microelectronics is so to go ahead with the improvement of transistor in all aspects (electronic performances and economical).
To follow this endless race, the well-known concept of downscaling is required consisting in continuously shrinking the geometrical dimensions of the transistor.However, for small device length, the electrostatics of the device is affected, which degrades the control of the electric current.So, to keep the performances under control, the device architectures have evolved by, for example, improving the gate (controlling electrode) or using thin-film transistor.This article focuses on MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) made on silicon, since it is the technology used since decades for microprocessors.The main part of the MOSFET is its semiconducting "channel" coupled to conducting "source" and "drain" regions, and surrounded by one or several gate electrodes which control the current through the channel.The gate is separated from the channel by a thin insulating oxide.Figure 1 shows transmission electron microscopy (TEM) images of several MOSFET architectures (a) and schematics of these devices and of their potential for channel length reduction (b).(Barral & al., 2007a), Double Gate (Barral & al., 2007b), finFET (Dupre & al., 2008) and stacked nanowires (Dupre & al., 2008)); b) schematics of the downscaling concept.
The essential parameter used to analyse the electrostatic behaviour (so to compare MOSFET architectures) is the natural length λ (Collinge, 2007).It represents the perturbation induced by the transistor source and drain junctions on the gate control.Numerical simulations establish that a device is relatively free of electrostatic perturbations if λ has a value smaller than 5-10 times the gate length. .. .
where ε si and ε ox are the silicon and oxide permittivity, t si and t ox the silicon and oxide thickness and N represents the number of gates of the architecture.Thus, for a given value of silicon thickness and oxide (t si =10 nm and t ox =1.5 nm) the corresponding minimum length for the bulk, thin BOX FDSOI, and nanowire are 20 nm, 15 nm and 10 nm respectively.That is why ITRS recommends nanowires for technology node sub-22nm (International Technology Roadmap of Semiconductor [ITRS], 2009) and regarding the advanced processing technologies, the literature provides a wide range of devices based on nanowires, stacked (Dupre & al., 2008), twin (Hwi Cho & al., 2007) or single Ω-FET nanowires (Tachi & al., 2009).In the following, a complete study of the electrostatics of nanowire MOSFETs is performed including all the ultimate physical phenomena which can occur in future electronic devices.

The electronic structure of silicon nanowires
Standard silicon layers used in microelectronics are crystallographic.Silicon atoms are disposed in a periodical lattice similar to the diamond structure: each atom is tetrahedrally bonded to its four neighbours (see figure 2).The cubic unit cell parameter a 0 equals 5.43 Å, corresponding to an interatomic distance of 2.34 Å. Ideal silicon nanowires are thus periodic along their axis, and the length L of their unit cell depends on the crystallographic orientation:  L=a 0 for <100> oriented nanowires,  L=a 0 / 2 for <110> oriented nanowires,  L=a 0 3 for <111> oriented nanowires.
The orientation and diameter of the nanowire determines its electronic structure, from which result its electrical and optical properties.In the following of this work, we will consider cylindrical nanowires oriented along the <100> axis, as the one represented in figure 2.
The electronic structure of bulk silicon is expressed by the dispersion relations E n (k), which give the energy of an electron wavefunction with wavevector k in band n.A schematic of low energy electrons in the conduction band is shown in figure 3. It represents the isoenergy surfaces in the first Brillouin zone (wavevector space).For conduction bands, we can count six energy minima, named the six "Δ valleys" of bulk silicon.Each valley is characterized by an effective mass m l along its orientation axis and m t along its transverse directions.The longitudinal mass is m l equal to 0.919m 0 and m t is equal to 0.196m 0 where m 0 is the free electron mass.
In the following, we consider transport along the x-axis.So, projecting bulk valleys on the nanowire axis (x for the transport, y and z for the perpendicular direction), we can define two different valleys of the nanowire characterized by a conduction and a confinement masses.The valleys 1 and 2 of the figure 3 correspond to the longitudinal valley while the valleys 3, 4, 5 and 6 refer to the transverse valley.The table 1 gives the corresponding masses of the two nanowire valleys.The confinement mass of the transverse valleys is approximated by a "cylindrical mass", which preserves cylindrical symmetry in the calculations.This effective mass approach is only valid for thick nanowires (diameter > 5 nm) and low electron energy (a few tenths eV).The band structure of silicon is described more accurately by atomistic models, which allow modelling thinner nanowires.A tight-binding model is used here.It consists in developing the wavefunctions on an atomic orbital basis set.The sp 3 model developed by (Niquet & al., 2000) is used here and in previous studies (see section 3.4).This model is fitted on first principles calculations based on the density functional theory (DFT) and so-called "GW" corrections for the bandgap.It contains one s orbital and three p orbitals per silicon atom and describes accurately electron (conduction band) and hole (valence band) dispersion relations.When studying nanostructures, the surface is passivated with hydrogen atoms (see figure 2).This model choice is due to the lack of a convenient tight-binding model for the Si/SiO 2 interface.Passivation avoids unrealistic surface states and should not modify much the electronic structure of the nanowire.The tight-binding calculations are performed with the code TB_Sim (TBSIM, 2011), which solves the Schrödinger equation in nanostructures containing up to 10 7 atoms (Niquet & al., 2006).
For thin nanowires (diameter < 5 nm), the obtained electronic structure differs from the effective mass calculation (see section 3.4).TB_Sim also allows Poisson-Schrödinger calculations, which give the repartition of the charge density in the nanowire under the influence of the gate voltage.Again, corrections of the effective mass approach are needed for thin nanowires.

Definition of the threshold voltage
As said previously, the MOSFET transistor is defined by two states (ON or OFF) depending on the voltage applied at the gate.In fact, this polarization creates an electric field in the active region of the transistor which makes carriers concentrate near the interface with the oxide.Increasing the gate voltage, conduction bands start to fill with carriers from lower energy bands to higher energy bands up to saturation.In this regime, the semiconductor is then analog to a metal and forms a conduction layer between contacts (source and drain) of the transistor.Commonly, the threshold voltage is so defined as the frontier of the two states of the transistor and represents its capacity to switch from one state to the other.It is essentially dependent on the electrostatic characteristics.That is why, it is necessary to fully describe the potential ψ everywhere in the device active region.For this purpose, the Poisson equation, given here in cylindrical coordinates, is solved: where N A is the channel doping, n is the electron density, ε Si the silicon permittivity, and q the elementary charge.Note that n depends on  via the Fermi-Dirac occupation of electronic states.
Two approaches can be used to obtain the solution of such an equation.The first one is the double integration solving (Jimenez & al., 2004;Yu & al., 2007); however the solution is not totally analytical which is not convenient in our case.The second approach is to make an assumption on the potential description along the nanowire radius.In the following, we assume a parabolic potential along the radius of the nanowire cross-section described as: where the parabolic terms β i are x-dependent functions.
To define these terms, the general expression of the potential (eq. 3) is injected in boundary conditions specific to nanowires (eq.4): the potential at the position r=D/2 is equal to the potential at the position r=-D/2 (symmetry condition) and is defined as the surface potential ψ s :

i lin
where Q i,lin is the charge integrated along the nanowire radius and ψ s is the surface potential.
It is important to note that the parabolic assumption is valid at threshold, but could lose its validity in other operation regimes (for example in the strong inversion regime).Figure 4(a) shows the schematics of the nanowire with the longitudinal polarization (V DS ) along the xaxis (transport).The starting point of the threshold voltage modelling is the boundary condition at the Si/SiO 2 interface: .
where V FB is the flat-band voltage, ζ S is the electric field at the interface,  F is the Fermi potential and C ox is the oxide capacitance in cylindrical coordinates expressed in (Dura & al., 2010).
In our case, we consider the threshold voltage defined as the gate voltage for which the inversion charge reaches its threshold value fixed to (Munteanu & al., 2005): where k is the Boltzmann constant and T is the temperature.Under this condition, the surface potential reaches its threshold value, called ψ s,th .The threshold voltage is then obtained as: , . .
In equation ( 9), only the surface potential is unknown and has to be modeled taking into account the physical phenomena specific to nanowire MOSFETs described below: quantum confinement, short channel effect, and band structure effect.

Quantum mechanical confinement (QE)
In silicon nanostructures such as nanowires, the wavefunctions related to the different valleys are modified and kinetic energy is quantized along the confinement directions, leading to a set of energy subbands for each valley.Previous works highlight the necessity to consider quantum confinement in the transport modelling of planar architectures (Munteanu & al., 2005), for which the confinement is one-dimensional.For nanowire devices, quantum confinement is two-dimensional (leading to a 1D electronic gas) and its impact is expected to be stronger (Autran & al., 2005).Figure 5 shows the wavefunction in the first five subbands for the longitudinal valley and for two different nanowire diameters (5 and 10nm).These wavefunctions are calculated using an effective mass Schrödinger-Poisson solver (TBSIM, 2011).The associated energy represents the difference between each energy subband and the first subband level.To extract numerically the impact of the diameter on the quantization of carriers, the same calculation has been done for the tranverse valley and for different nanowire diameters.We can note that for low diameters, the quantized levels are higher.So, regarding the targeted MOSFET downscaling to a few nanometers, quantum-mechanical effects have to be included in the previous analytical model of threshold voltage in order to assess their impact up to circuit performances.
For this purpose, the 1D quantum charge integrated along the radius Q i,lin has to be used: , ( ,,) where the factor 2 accounts for the number of equivalent valleys, j is the valley index, i is the subband index, Ec = E i j is the subband bottom energy, ρ 1D (E,E c ) is the 1D density-of-states of the subband, and f(E) is the Fermi-Dirac distribution function: . .
where m j is the 1D density-of-states effective mass in valley j and E F is the Fermi level.The general expression of the charge is then: Under non-degenerate condition (valid at threshold), the Fermi-Dirac distribution can be approximated by a simple exponential (corresponding to the Boltzmann distribution).The expression of the charge becomes (Autran & al., 2004): where Eg is the silicon bandgap, and g(j) is the degeneracy of the valley j (equal to 2 for each valley).The charge is then obtained by a sum over the different silicon valleys (index j) and a sum over all quantized levels (index i) of each valley (in practice limited to 5).The quantum energy levels are needed in (17) and have to be calculated analytically.For a cylindrical cross-section of the nanowire, the analytical expressions of the transversal (index t) and longitudinal (index l) quantum energy levels are given by (Baccarani, 2008): where α is a numerical parameter (Baccarani, 2008).We can note a good agreement between (18) with α=2.1 and a self-consistent cylindrical 1D Schrödinger-Poisson solver (ATLAS, 2010) for the first energy level (transversal and longitudinal) (Dura & al., 2010).
From equation ( 16), the surface potential at threshold voltage is given by: , , * .ln( ) with Q ith,lin the inversion charge at threshold defined by (8).Including this expression in (9), the quantum threshold voltage for long channel transistor is easily obtained.Figure 6 plots the difference between quantum and classical threshold voltage versus the nanowire diameter; as expected, this difference increases when reducing the nanowire diameter, due to a stronger quantization of carrier energy when the nanowire 123 diameter is reduced.Figure 6 also shows a very good agreement between the analytical model and data obtained by a Schrödinger-Poisson numerical solving (ATLAS, 2010).

Short-Channel Effect (SCE)
As said in the introduction, the downscaling of transistor is required.That is why the gate length is continuously reduced.However, from a certain dimension, the transistor junctions (source and drain) have an impact on the electrostatic control of the device.Previously 1D (only the gate voltage), it becomes 2D because gate and drain polarizations compete to control the device.And this strongly affects the device characteristics.Thus, MOSFET architectures are considered to be impacted by the short channel effect when the channel length is the same order of magnitude as the depletion-layer widths of the source and drain junction.The main result is the modification of the threshold voltage (or the loss of electrostatic control) due to the shortening of the channel length.It is attributed to two phenomena: SCE (Short Channel Effect) and DIBL (Drain Induced Barrier Lowering).The first one is coming from the superposition of the depletion-layer widths of the source and drain junction.The second phenomenon is a secondary effect on the charge sharing due to higher drain voltage.Nanowire transistors being expected for ultimate technology node, consideration of short channel effect is required in a realistic modeling of this architecture.
To fully describe 2D electrostatic effects (SCE and DIBL) in short channel devices, we propose a full analytical model describing the threshold voltage impacted by SCE and DIBL.The x-dependence (transport direction) of the surface potential has to be know.Applying the Gauss law on a nanowire slice as illustrated in figure 4(a), the following equation is obtained (Munteanu & al., 2005) where ζ is the electric field expressed by: η is a fitting parameter which models the lateral electric field variation (Banna & al., 1995).It depends on the channel doping, the channel length, the nanowire diameter and the polarization.An empirical formula for η, obtained from numerical simulations, will be presented below to include these both effect.Introducing ( 21) in (20), we find a second order equation for the surface potential: The solution of this equation is given by (Munteanu & al., 2005): .. 3 12 .. ² 4. ..
where K 1 , K 2 and K 3 are functions resulting from the Poisson equation solving: where V b is the built-in potential depending on the channel doping N A , the source/drain doping N SD and the intrinsic carrier density n i as: 2 ..ln The position where the surface potential is minimum x min and the value of ψ S (ψ s,min ) at the position x min are obtained by forcing the first derivative of equation ( 23) to be equal to zero (Munteanu & al., 2005): We assume that the transistor switches on when ψ s,min = ψ s,th .By inserting this expression in the general expression of the threshold voltage (9), we obtain: We can, by analogy to (Suzuki & al., 1996), distinguish two different terms.The first one (independent from the channel length) refers to the long-channel threshold voltage V th,long ; the second term, which tends to zero for long channel length, represents the threshold voltage roll-off and describes the impact of SCE/DIBL: 3 , 2 ..

  
where the variation of the threshold voltage is defined as: At threshold, V GS =V th in (26) and, considering (33), K 3 will depend on ΔV th .Moreover K 1 and K 2 depend on K 3 , they will also depend on ΔV th .Then, developing (33) leads to a second order equation of ΔV th as: 2 .. 0 Finally, the threshold voltage roll-off is the solution of (34) given by: We can note that to find this term, we have to take into account the long-channel threshold voltage (see coefficient D in eq.35) which includes the dependence on the quantum confinement.Consequently, this model includes both the impact of quantum confinement on the long channel and the threshold voltage roll-off.The most common model (such as references (Banna & al., 1995;Suzuki & al., 1996)) does not include the effect of quantum confinement on the evolution of the short channel effect in analytical modeling which becomes dominant in nanoscale device such as nanowire (this aspect will be detailed later in paragraph 4).Fig. 7. Threshold voltage roll-off versus channel length for low (V DS =50mV) and high (0.7V) drain voltage obtained by the analytical model and TCAD simulations for a 5 nm nanowire diameter; t ox =1 nm.
The threshold voltage roll-off is represented in figure 7 for nanowire diameters of 5 nm (calculated in the classical case, i.e. without quantum confinement).TCAD numerical simulations have been done for a cylindrical structure using a drift-diffusion model in order to obtain drain current characteristics as a function of the gate voltage.The threshold voltage is extracted from these current-voltage characteristics using the classical constant current method.The threshold voltage data extracted from TCAD simulations for different diameters have been used to derive an empirical expression of the parameter η including the dependence on the channel length, nanowire diameter and drain to source voltage: where f 0 , f 1 and f 2 are constant fitting parameters, calibrated on numerical simulations.Equation ( 37) is valid for a wide range of nanowire diameter (down to 2 nm) and channel lengths (down to channel length equal to the nanowire diameter).The results in figure 7 show a good agreement between the analytical model and threshold voltage data obtained from TCAD simulations.

Band Structure Effect (BSE)
Advanced atomistic numerical simulations (Neophytou & al., 2008;Niquet & al., 2000Niquet & al., , 2006;;Sarrazin & al., 2009;Nehari & al., 2006) have shown that a strong reduction of the silicon thickness impacts the material properties by modifying the band structure.Indeed, the dimensions targeted in ultra-scaled devices are those of a few tens atomic layers (several nanometers).At these dimensions, the electronic properties differ from the calculations shown in section 3.2 and based on the bulk effective masses.In (Sarrazin & al., 2009), atomistic tight-binding (TB) Schrödinger-Poisson simulations have been performed for the case of [001] oriented silicon nanowire in order to highlight the variation of the band structure with the nanowire diameter.The code TB_Sim (TBSIM, 2011) has been used with a sp 3 tight-binding model (Niquet & al., 2000).Figure 8 shows the valence and the conduction bands for Si nanowire width of 2nm and 10nm.We can note that when thinning the silicon film the minimum of the conduction band is increased and the general shape of bands becomes smoother (Sarrazin & al., 2009).However, the bandgap increase is smaller than the effective mass result of section 2.4.
In order to include these modifications in the previous threshold voltage modelling, analytical expressions of parameters affected by the band structure effect (band gap and effective masses) are proposed here.Diameter-dependent analytical functions (fitted on numerical simulations as illustrated in figure 9) are found for the bandgap and effective masses (inspired from (Niquet & al., 2000): where A, B and K are fitting constants.(Sarrazin & al., 2009).

Results and discussion
We have just presented the modeling of all the physical phenomena which affect the electrostatics of nanowire MOSFETs.In this part, the impact of each mechanism is assessed at different levels of interest: threshold voltage, drain current and small-circuits performance.

Long-channel transistors
Figure 10 shows the long-channel threshold voltage increase due to quantum confinement, without BSE (i.e., considering bulk value for the band gap and the conduction masses) and with BSE (i.e., considering equations ( 37) and ( 38)).The analytical model has been compared to both numerical simulations (Sarrazin & al., 2009) and experimental data (Suk & al., 2007). .Difference between quantum (V th,q ) and classical threshold voltage (V th,cl ) with and without BSE versus nanowire diameter (long channel transistors).Comparison between the analytical model, atomistic simulations (Sarrazin & al., 2009) and experimental data (Suk & al. 2007).
We can note that the band structure effects tend to limit the impact of the quantum confinement on the threshold voltage of the nanowire.This is coherent with equation ( 18).Increasing the effective masses, the quantum energy levels are lowered and the energy quantization decreases; then the quantum threshold voltage is lower.Figure 10 highlights the importance of considering BSE especially for thin film where the difference between threshold voltage with BSE and threshold voltage without BSE increases when reducing the nanowire diameter.

Short-channel transistors
In the following, we investigate the impact of the quantum confinement on SCE, then the impact of BSE on SCE.As stated previously, the threshold voltage roll-off depends on quantum confinement through the long-channel threshold voltage which includes quantum confinement effects.Comparison with data extracted from numerical simulations using a cylindrical Schrödinger-Poisson solver (Munteanu & Autran, 2003).
Figure 11 shows the impact of quantum effect and BSE on SCE as a function of the nanowire diameter.The curves plot the threshold voltage roll-off for a channel length equal to the nanowire diameter for the three approaches: classical (i.e., without quantum confinement and BSE), quantum without BSE, and quantum with BSE.Quantum threshold voltage obtained using the analytical model is validated in Fig. 11 with numerical simulation data obtained with a cylindrical Schrödinger-Poisson solver (Munteanu & Autran, 2003;Zervos & Feiner, 2004).We can note that the quantum confinement tends to limit SCE.This is due to the enhanced electrostatics control of the active area due to carrier energy quantization.As expected, the difference between quantum and classical approaches increases when reducing the nanowire diameter (due to the increase of energy quantum level for thinner films).When considering quantum confinement, the carrier energy is higher than for classical approach.That is why it is less affected by the longitudinal source to drain electric field, which generally strongly impacts the transistors performances at these channel length values.Moreover, figure 11 shows that BSE tend to amplify the impact of quantum effects on SCE: the threshold voltage roll-off is reduced when considering quantum confinement with BSE compared to the case when only quantum confinement is considered.For long channels, the threshold voltage decrease when considering BSE was due to the increase of the effective masses which lowered the quantized levels.In the case of short channels, the reduction of SCE when BSE are taken into account is the consequence of the band gap increase.A wider band gap means a higher energetic barrier, leading to a better electrostatics control which is less impacted by source-channel and drain-channel junctions when reducing the nanowire channel length.Moreover, we can note that below a certain diameter (depending on the modeling approach), the diameter thinning has a stronger impact on the threshold voltage roll-off than the channel length reduction.For the same channel length to diameter ratio, the threshold voltage roll-off is higher for D=5 nm than for D=2 nm.Indeed, for ultra-thin films, the quantization of carrier energy is very strong and the carrier concentration is mainly controlled by quantum confinement.In the case of D=2 nm, the strong electrostatic control due to the ultra-thin diameter completely overcomes the increase of SCE expected for these ultra-short channel lengths.

Impact on the injection velocity
Another parameter affected by the BSE is the thermal velocity which depends on masses along the transport direction.Indeed, in our case, for a transport along the (001) direction, the expression of thermal velocity is: Figure 12 (Dura & al., 2011) shows the thermal velocity evolution with respect to the nanowire diameter.We can note a non-negligible reduction for ultra-thin nanowires up to a 20% decrease for D = 2 nm.

Impact on ballistic drain current of nanowire MOSFET
In previous works, we have demonstrated the analytical model of drain current in GAA nanowire MOSFETs in the ballistic transport regime (without interactions).We remind that this ballistic drain current is derived from the flux method initiated by McKelvey et al (McKelevey & al., 1961), doing a balance in the active region between the different carrier fluxes.In the degenerate case, the ballistic drain current is given by the following expression: where D is the nanowire diameter, v th is the thermal velocity discussed above, V GS is the drain to source voltage, V DS is the drain to source voltage, C ox is the oxide capacitance, η F is the Fermi level, 0  and 1/2   are the Fermi integral of order 0 and -1/2 respectively and V t is the threshold voltage modeled above.(Barraud & al., 2009)).
Figure 13 shows the result at the device level for a long channel transistor and for two different nanowire diameters (3 and 5nm) (Dura & al., 2011).The ballistic drain current model is compared to numerical simulations based on a deterministic Wigner equation solver (Barraud & al., 2009).We can note a strong impact of BSE on the current in the sub-threshold regime for 3nm-diameter due to the V t variation while the ON-state current stays almost unchanged.From this graph, we can highlight the necessity to take into account the correction due to bands variations in the modeling if we expect to provide predictive devices performances.Indeed, at 3nm, the off-state current is increased by more than one decade when BSE is considered.

Impact on performances of small circuits based on nanowire MOSFETs
After implementation in a Verilog-A environment, the model presented above has been used to simulate a CMOS inverter and then a complete 11 stages-ring oscillator.In order to build-up the CMOS inverter a p-type nanowire MOSFET is considered symmetrically to the n-type transistor in the inverter setup.The impact of BSE can be addressed at the circuit level through the study of the commutation characteristics of the inverter or the oscillation frequency of a ring oscillator.
Figure 14 shows the input/output characteristics of the inverter for the classical case (i.e., without QE), with quantum effects (QE) and with band structure effects (QE+BSE).We can note that the inverter characteristic is more abrupt when considering only QE.Similarly to the results obtained for the threshold voltage, BSE tends to limit the impact of quantum confinement by smoothing the CMOS inverter switch.Regarding the ring oscillator, the results seem opposite to the inverter case.The better performances are for the classical case and introducing quantum confinement reduces the oscillation frequency.This is due to the fact that the ring-oscillator frequency is directly proportional to the ON-state current in strong inversion regime Vdd=1.5V(far from the threshold voltage).QE increases V th and consequently reduces the current.The injection velocity also impacts directly the current and then the oscillation frequency is affected.The result is a reduction of the oscillation frequency when BSE are taken into account.

Conclusion
In this chapter, the potential of silicon nanowires for microelectronics applications was evaluated.Regarding the evolution of transistor architectures, they appear as the best configuration for the gate control of the device.The particular shape with a surrounding gate provides an ideal electrostatic control to immunize transistors against perturbations generated by the scaling down of dimensions.In this work, we have developed a complete model of the electrostatic of transistors based on nanowires.The physical phenomena affecting the electrostatics was considered: short-channel effects due to the channel length reduction or the quantum mechanical effects due to the diameter thinning.Moreover, ultimate mechanisms as the modification of the band shape of silicon material is studied based on advanced simulations (essentially tight-binding Schrodinger-Poisson solving).All this physics (thanks to analytical model development) is transposed to higher simulation levels as characteristics of transistor or small-circuit performances.Following this idea, we have seen the impact of short-channel, quantum or band structure effect on the threshold voltage.For ultra-thin nanowires, we highlighted the necessity to consider all these phenomena to be as close as possible to experimental data.Then, a study of their impact on transport was performed with the analysis of ballistic drain current of single transistor and performances of inverters or ring oscillators.In all cases, the evaluation of performances is inaccurate if quantum or band structure effects are not considered.For example, one decade and a half of difference on OFF-state current or a reduction of factor 2 or 3 on the oscillation frequency show the importance of the electrostatics (and so a realistic modeling) if we envisage nanowires as the future technological solution in microelectronics.

Fig. 2 .
Fig. 2. Atomistic representation of a <100>-oriented nanowire.Blue: silicon atoms, grey: hydrogen atoms (necessary to passivate the surface in the tight-binding model), red: highlight of the tetrahedral structure of silicon.The nanowire is 1.5nm thick and 5nm long.

Fig. 3 .
Fig. 3. Iso-energy surfaces of the conduction band of bulk silicon in wavevector space, and definition of longitudinal and transverse valleys for transport along a <100>-oriented nanowire.

Fig. 4 .
Fig. 4. (a) Schematics of a nanowire device (for a better view the gate oxide and material are not shown), indicating the specific area used in the Gauss law.(b) Band diagram along a vertical cut-line in the nanowire.The term β 3 is found by including (5) into the Poisson equation (2) and integrating along the nanowire radius from 0 to D/2: Figure 4(b) shows the band diagram along a transverse cutline in the nanowire for an applied gate voltage V GS .The potentials are defined with respect to the intrinsic Fermi level as illustrated in figure 4(b).

Fig. 5 .
Fig. 5. Square modulus of the wavefunction for the five first levels in the longitudinal valley of a 5 and 10nm nanowire diameter.Energy increase of each subband with respect to the first level.

Fig. 6 .
Fig. 6.Threshold voltage shift between quantum (Vth,q) and classical (Vth,cl) approaches versus nanowire diameter in long channel transistors.Comparison between the analytical model and data obtained from Schrödinger-Poisson numerical solving (ATLAS, 2010).

Fig. 11 .
Fig. 11.Impact of band structure variations on SCE.Threshold voltage roll-off versus nanowire diameter for a channel length equal to the nanowire diameter.Comparison with data extracted from numerical simulations using a cylindrical Schrödinger-Poisson solver(Munteanu & Autran, 2003).

Fig. 12 .
Fig. 12. Impact of the band structure effect on the thermal velocity with respect to the silicon nanowire diameter.

Fig. 15 .
Fig. 15.Impact of BSE on the ring oscillator frequency versus the nanowire diameter.Comparison between classical, quantum (QE) and low dimensions effects (QE+BSE).

Table 1 .
Definition of the longitudinal and the transverse masses for the <100> oriented nanowire.