Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc.


Introduction
As the VLSI technology goes into the nanometer era, the device sizes and supply voltages are continually decreased. The smaller supply voltage reduces the power dissipation but also decreases the noise margin of devices. Therefore, the power integrity problem has become one of the critical issues that limit the design performance (Blakiewicz & Chrzaniwska-Jeske, 2007;kawa, 2008kawa, & Michael et al., 2008. Most of the power supply noises (PSNs) come from two primary sources. One is the IR-drop and the other is the simultaneous switching noise (SSN). Figure 1(a) illustrates a typical RLC model for power supply networks, which is the combination of on-chip power grids and off-chip power pins. The IR-drop is a power supply noise when the supply current goes through those non-zero resistors and results in a I·R voltage drop. The simultaneous switching noise (SSN) is the supply noise which happens when large instantaneous current goes through those non-zero inductors on power networks and generates a L·(di/dt) voltage drop. When the supply voltage is reduced , the noise margin of devices also decreases as shown in Fig.1(b). It may induce worse performance because the driving capability of devices becomes week due to smaller supply voltage. If serious power supply noise occurs, the logic level may be changed, which causes function error in the circuit. The worst situation is the electronmigration (EM) effects. Supply wires are shorten or broken because a large current travels through the small supply wires. Therefore, the power supply noise analysis is reguired at design stages to evaluate the effects caused by power supply noise. While esimating the power supply noise, both the magnitude and slope of supply currents are required. Traditionally, accurate supply current waveforms can only be obtained from the transistor-level simulation. Therefore, in the present design flow, the power supply noise (PSN) check is mostly performed at very late design stage. Although the analysis results are accurate at transistor level, this approach may be impractical for large designs because simulating the entire design at transistor level requires great computation resources. If any problem is found, the designers often tune the width of the supply lines or add another current path to fit the specification. However, if the supply current waveforms are obtained at early stage, more efficient low-power technologies, like multiple supply voltages and powergating, can be used to reduce the supply power and noise (Chen et al., 2005;Juan et al., 2010;Kawa, 2008;Michael et al., 2008;Popovich et al., 2008;Xu et at., 2011& Zhao et al. 2002. The primary reason of lacking tools for checking the power integrity problems at gate level or higher levels is the limited design information, that current cannot provide waveforms directly. In this research, we propose the gate-level IR-drop analysis method with limited design information to build the missing link of the traditional design flow. The most popular format to store the gate-level information is the liberty format (LIB) (Synopsys, 2003). The LIB file of a cell library keeps the information of all cells and is widely used in the synthesis and timing analysis at gate level and RT level. However, due to the format limitation, only timing information and average energy consumption are kept in LIB files. They cannot provide instantaneous supply current information directly. One straightforward approach is to approximate the instantaneous supply current using the average power divided by the user-given time interval as illustrated in Fig. 2(a). However, even if the average power is the same, the waveforms can be quite different with different time intervals. It may not be accurate enough to estimate real instantaneous supply current.
Several advanced library formats have been proposed for recording voltage waveforms (ECSM) (Candence, 2006) or current waveforms (CCSM) (Synopsys, 2008) to provide the more accurate timing and power information. These formats need large storage space to record these piece-wise-linear waveforms. Therefore, those new formats are only used in very advanced process, like 65 nm technology. Typically, the libraries with new formats are used to support the static timing analysis to obtain more accurate estimation. It may also support the gate-level power estimation to obtain more accurate peak power. However, because the peak power is often evaluated in the cycle-accurate basis at gate level, it will suffer the same time-interval issue. In the literature, the authors in (Boliolo et al., 1997) propose an approach to estimate power supply noise at gate level. In their approach, the capacitance of each internal node in a cell, the energy consumption of each transition, and several regression equations representing the timing behavior, are required to estimate the supply current waveforms. Given an input pattern to a cell, its supply current will be approximated as a simple triangle, whose area is the total energy. The base and the height of this triangle are obtained from the regression equations. Then, combining all triangles of every changed cell in time obtains the overall supply current waveform. This approach is a practical solution that can be combined with logic simulation tools. The results shown in the paper are also accurate. However, the required timing behaviors of supply current waveforms are not available in standard library files. Extra characterization efforts for different cell libraries are still required before using this approach, which is a very time-consuming process.
In anthor work (Shimazaki et al., 2000), the authors propose an EMI-noise analysis approach based on a rough supply current waveform. Although their approach also uses standard library infotmation, their current waveform estimaiton approach is too simple to provide accurate supply current waveforms. Most importantly, their approach can be used in combination caircuits only, which is not feasibal for modern complex designs. Therefore, an accurate gate-level supply current model using standard library information, even for sequential circuits, is propsed to avoid addtional charcterization process (Lee et al., 2008).
The proposed current model has provided the solutions to estimate the ideal supply current waveforms without noise effects. However, the estimated waveforms cannot be directly used to analyze IR-drop effects because the supply currents will have significant difference with non-zero resistance on the supply lines. Figure 2(b) shows an example obtained from the c432 circuit suffering from different supply noises. In typical cases, the current with supply noise is less than the ideal current. If the ideal supply current waveforms are used to calculate the IR-drop, the results are often overestimated. The direct solution to consider the effects of IR-drop is to extend the libraries with different supply resistors. However, this approach will greatly increase the storage space and characterization efforts for library information, which may be not a good solution. Therefore, a library adjustment method is also proposed to consider the IR-drop effect on supply current modeling with standard library information . The proposed gate-level IR-drop analysis flow is illustrated in Fig.3. According to the cell switching from gate-level activity files, the corresponding supply current waveform of each cell can be constructed by using standard library information. The supply current waveforms obtained from the original standard libraries are then modified to consider IR-drop effects. Second, the estimated supply current waveforms of all switching cells are summarized in time to obtain the supply current waveforms of the whole circuit. Finally, the IR-drop voltage caused from the supply resistor can be derived from the current waveform.
The rest of this article is organized as follow. In Section 2, the most popular library format, the liberty format, is presented. A gate-level supply current waveform estimation method using standard library information is proposed in Section 3. A correction method of the library information is also proposed to modify the IR-drop effect in Section 4. The experimental results of this work are demonstrated in Section 5 and a simple conclusion is presented in Section 6.

Standard library: Liberty format (LIB)
Liberty format (LIB) (Synosys, 2003) is the most popular library format at gate level to store the timing information and the average energy consumption of each cell in the standard library. Those data are stored using some look-up tables. The definitions of some commonly used variables are listed as follows. They will be used later to derive the proposed current waveform model.
Transition Time: This is defined as the duration time of a signal from 10% to 90% VDD in the rising case and from 90% to 10% VDD in the falling case. TR(X) is defined as the transition time of the node X in the rising case. TF(X) is defined as the transition time of the node X in the falling case.
Propagation Time: This is defined as the duration time from the input signal crossing 50% VDD to the output signal crossing 50% VDD. TDR(X Y) is defined as the propagation delay from the related pin X to the output Y when the output Y is rising. D represents the propagation delay and R represents the rising case. TDF(X Y) is defined as the propagation delay from the related pin X to the output Y when the output Y is falling. F represents the falling case.
Setup Time: This is a timing constraint of the sequential cell, which is defined as the minimum time that the data input D must remain stable before the active edge of the clock CK to ensure correct functioning of the cell. In other words, it is the duration from D crossing 50% VDD to CK crossing 50% VDD if the output value can be evaluated successfully. TSR(D) is defined as the setup time when the data input D is rising. S represents the setup time and R represents the rising case. TSF(D) is the setup time when the data input D is falling. F represents the falling case.
Load: This is the total capacitance at a node. Load(Y) is defined as the capacitance at the node Y.
Internal Power: This is the internal energy consumption of a cell without the energy consumed on its output loading. E INT is defined as the internal energy consumption of the cell.
Changing Time: T(X) is defined as the time that the signal X is crossing 50% VDD, which is the signal transition point in logic simulators recorded in VCD (Value Changed Dump) files.
Voltage Definitions: VDD is defined as the supply voltage. VT is defined as the threshold voltage of the transistor.

Current waveform estimation using library information
In order to avoid extra characterization efforts while migrating to new cell libraries, a supply current model is proposed based on standard library information. The key idea is using a triangular waveform to approximate the real supply current waveform generated by a cell switching as shown in Fig. 4. Then, the parameters of the triangle are calculated by standard library information only. Finally, the overall supply current waveform can be obtained by combining all triangles of every changed cells in time. Before presenting the proposed approach, some variables must be defined first. For each triangle shown in Fig. 4, four variables, T START , T END , T PEAK and I PEAK , are defined to represent the triangular waveform. T START and T END are the start/end time of the supply current waveform. These two variables define the duration of the waveform. T PEAK and I PEAK are the location and current value when the maximum supply current occurs. Although there are a lot of cells in a cell library, most of them can be classified into three categories in our approach. In the following sections, the formulas to construct the current waveform model in each category will be presented. During the formula construction, this work assumes that only the LIB file is available. Therefore, the transistor-level netlist and detailed device sizes are avoided. If some general structures are required to build the formulas, only the information provided in the library data sheet will be used. While applying the proposed methodology to different libraries, users can make necessary adjustment easily from that public information.

Simple logic cells
If the CMOS implementation of a cell is a single layer structure, it is called a simple logic cell in this work, such as INVERTER, NAND, NOR as shown in Fig. 5. Those cells can be modeled as an equivalent inverter with two parts, the equivalent PMOS and NMOS. Therefore, in the following discussion, an inverter is used as an example to discuss its supply current model in the charging period (the output signal is rising) and the discharging period (the output signal is falling).

Charging period
In the charging period, the relationship between the input signal X, the output signal Y and the timing parameters of the triangular waveform can be illustrated in Fig. 6. T START is defined as the time that the input voltage achieves (VDD-VT) because the equivalent PMOS turns on at this time. The corollary of T START is shown as follows.
(1) Fig. 6. The parameters of a simple cell in the charging period In typical cases, the shape of the charging current for a simple logic cell is similar to a RC charging behavior. Therefore, the exponential RC charging function is used to approximate this behavior. Theoretically, T END is defined as the time when the output loading is charged to VDD. However, due to the long tail of the RC charging curve, T END is defined as the time that the output loading is charged to 95% VDD in this work to reduce the error while the waveform is simplified to a triangle. The corollary of T END is shown as follows, where τ is the RC time constant.
In this paper, two points (X1, Y1) and (X2, Y2) on a plane are used to define a line. Then, the slope (a) and intercept (b) can be calculated as follows.

Under this definition, the time t that the equation Y(t) is larger than the equation X(t) with
VT can be calculated as follows.
In the charging period, T PEAK is defined as the time that the operation mode of NMOS is in the saturation mode and the operation mode of PMOS is changing from the saturation mode to the linear mode, which is the point that allows most current to flow through PMOS. In other words, T PEAK happens at the time when the voltage difference between the output Y and the input X is equal to VT (VSG=VT). Therefore, T PEAK can be obtained when Y(t) − X(t) = VT. Because the definitions of TF(X) and TR(Y) are the signal duration from 10% to 90% VDD, using them to calculate the signal duration from 0% to 50% VDD should be multiplied by 0.625(=0.5/(90% − 10%)) instead of 0.5. Finally, the corollary of T PEAK is shown as follows.
If the total consumed energy is used as the area of this triangle and the base of this triangle is (T END -T START ), I PEAK can be obtained from the formula of the triangle area. Please note that the energy stored in the LIB file is the internal energy consumption (E INT ) of the cell only.

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The energy consumed on the output loading (E LOAD ) should be added to obtain the correct area of the triangle. The corollary of I PEAK is shown as follows.

Discharging period
Because the supply current does not charge the output loading in the discharging period, most of the supply current can appear only when NMOS is turned on but PMOS is not completely turned off yet. Therefore, in this case, T START is defined as the time that input voltage achieves VT because NMOS is turned on at this time. T END is defined as the time that the input voltage achieves (VDD-VT) when PMOS is turned off. Using these definitions, the duration of the supply current waveform in the discharging period can be decided. Following the same assumption in Section 3.1.1, T PEAK is still defined as the time that the operation mode of PMOS is changed from linear to saturation. Figure 7 shows their relationship to the input/output waveforms. Because there is no current charging the output loading, the E INT obtained in the LIB file can be used as the triangle area in the discharging period to obtain the T PEAK value. The corollary of T END is shown as follows. www.intechopen.com Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis

Composite logic cells
As shown in Fig. 8, some cells are composed of two or more simple logic cells, such as BUFFER, AND, and OR cells. Those cells are called "composite logic cells" in this work. In the following descriptions, a BUFFER is used as an example to explain the proposed approach for those cells. Because the information of the internal signal I in Fig. 8(a) cannot be obtained in the LIB file, an assumption is made in this work that the input signal of the second stage in a composite cell will start rising/falling when the output voltage of its first stage achieves 50% VDD. With this assumption, the internal signal I can be rebuilt using existing library information as shown in Fig. 9. Since the timing information of the internal node can be estimated, the methods proposed in Sect. 3.1 can be used to handle the two simple cells respectively and the total current waveform of this composite cell can be estimated.

Charging period
If the output of the composite cell is rising, the internal node I will be in the falling case as shown in Fig. 10. Therefore, the simple-cell methods in the discharging period are used to calculate T START_1stF , T END_1stF and T PEAK_1stF of the first stage. Then, the simple-cell methods in the charging period are used to calculate T START_2ndR , T END_2ndR and T PEAK_2ndR of the second stage. Because there is only one energy value in the library and no proper method to split it into two parts, an assumption is made that the transition of the two stages are very close such that the composition of the two triangles still approximates to a triangle. While combining the triangles of the two stages, the T START , T PEAK and T END of the composed triangle are defined as the average values of the two triangles in this work for easier calculation. Then, I PEAK can be obtained in the same way from those timing information and the stored energy information. The detailed formulas to construct the current waveforms in this case are summarized as follows.

Discharging period
If the output of a buffer is falling, the internal node I will be in the rising case. Therefore, the simple-cell formulas in the charging period are used to handle the first stage. The simplecell formulas in the discharging period are used to handle the second stage. Then, using the similar approach for the case in charging period, T START , T PEAK and T END can be obtained from the average values of the two triangles. The rebuilt voltage waveforms and timing parameters are shown in Fig. 11. Because the energy of the reversed supply current at the second stage can be eliminated by the energy of the first stage, the internal power in the discharging period can be used directly to estimate the I PEAK of this cell. The detailed formulas to construct the current waveform in this case are listed as follows. www.intechopen.com

Sequential elements
In real applications, most circuits contain sequential cells. For a feasible solution, it is important to develop proper approaches to handle sequential cells. Like composite cells, sequential cells are often composed of several simple cells. In a standard library, the information of the internal nodes in a sequential cell is not stored, either. In order not to use extra information, some assumptions are made to rebuild the internal signals of a sequential cell. In the following descriptions, a positive-edge-triggered D-flip-flop (DFF) is used as an example to explain the proposed approach on sequential cells. Other flip-flops in the standard cell library, such as the flip-flops with set/reset, can be handled by using similar methods for their normal operations. The special set/reset behaviors can be characterized as a special case since they do not appear very often. Figure 12 shows the typical architecture of a DFF. It can be divided into three blocks, which are clock generator, setup block and evaluation block. The total supply current waveform of the DFF is the summation of the waveforms from the three blocks. Since the operation modes of a DFF are more complex, its current waveform model is discussed in three cases.

Only clock pin is changed
In this case, the data pin D is stable and its value is the same as the output Q. In most cases, the internal signals, N1_1, N1_2, N2_1 and N2_2, are stable, too. Therefore, a supply current only occurs in the clock generator when only the clock pin is changing. The clock generator is often composed of two inverters to generate two inverse signals, c and cn, as shown in Fig. 13.
First, the case of CK rising (active edge) is discussed. Using the same idea for composite logic cells, the voltage waveforms of CK, cn and c will be rebuilt first. Then, the formulas of composite logic cells in the charging period can be used directly to decide T START , T PEAK , T END and I PEAK . However, there is still no timing information for the internal nodes of flipflops in the LIB file. In order to solve this problem, two assumptions are made to rebuild the internal signals (cn and c) with approximate timing information.
The first assumption is that the maximum current of the tri-state inverter (G6) occurs when its output voltage (N2_1) reaches 50% VDD, as illustrated in Fig. 13.  The second assumption is that the rising and falling times of the nodes cn and c are very similar because most clock buffers are designed to have similar rising and falling time. From the first assumption, the time when V(c)=0.5 × VDD + VT can be obtained. Following the same assumption for composite cells, the input signal of the second stage will start rising/falling when the output voltage of the previous stage achieves 50% VDD. In order to simplify the explanation, a time interval (PT) is defined in Fig. 14. Since PT can be obtained with these two assumptions, the times that c and cn reach 0.5×VDD can be expressed with PT. Then, the internal voltage waveforms can be rebuilt as shown in Fig. 14. The detailed corollary is listed as follows.
As to the CK falling case, no outputs change and no timing information is stored in the library because it is not the active edge. Although the internal nodes might change in this case, there is no information to make any reasoning. Therefore, the same timing information in the CK rising case is used to be the T START , T PEAK and T END when only CK is falling. The internal energy consumption when only CK is falling is available in the library. It can be used to calculate a different I PEAK for CK falling case.

Only data pin is changed
In this case, the clock pin CK is stable and only the data pin D is changed. The supply current is generated by the setup block only. If CK is logic-1, the gate G3 is turned off such that the whole cell has no switching current. When CK is logic-0, the current waveform is determined by whether the data pin D is rising or falling. Because the timing information of the internal nodes N1_1 and N1_2 are not stored in the library, two assumptions are made in this case to rebuild the approximate voltage waveforms of N1_1 and N1_2.
The first assumption is that the data propagation time from the input D to the internal node N1_1 equals to the setup time of this DFF. Because the definition of setup time is the minimum time that input data must be stable before clock arriving, it can be viewed as the time that the data has been propagated to N1_1 to enter the first latch.
The second assumption is that the node N1_2 will become stable before the gate G6 is turned on to allow the data to enter the second latch successfully. Because N2_1 is discharging in the D rising case, N1_2 must reach VDD when the voltage of the node c achieves VT. TC(VT) is defined to express the duration time between V(CK)=0.5×VDD and V(c)=VT. Following these assumptions, the time that N1_1 reaches 50% VDD and the time that N1_2 reaches VDD can be obtained. Then, following the same assumption of composite cells, the time that N1_1 reaches 50% VDD is the time that N1_2 reaches 0. The voltage waveforms of N1_1 andN1_2 can be rebuilt as shown in Fig. 15. Fig. 15. The parameters of a DFF when only D is rising.
In the D falling case, TR(D) and TSR(D) are changed to TF(D) and TSF(D), respectively. E INT is changed from the rising energy to the falling one. With the two internal waveforms of N1_1 and N1_2, the triangle parameters can be determined by the same approach for composite cells. Finally, the detailed corollary is shown as follows.

Output changed with clock active edge
In this case, the clock pin has an active edge, the data pin is stable, and the output Q is evaluated. Both the clock generator and the evaluation block generate supply currents. Therefore, the current waveform is composed of two triangular waveforms in this case. The first current waveform of the clock generator is discussed in Sect. 3.3.1. It is focus on how to estimate the second triangular waveform of the evaluation block in this section. Figure 16 illustrates the rebuilt signals of the evaluation block when output Q is rising. First, using the rebuilt internal signal c in Sect. 3.1.1, the time that N2_1 starts to discharge can be obtained when the voltage of node c reaches VT. Second, T(Q) -0.625 × TR(Q) implies the time that N2_1 reaches 0.5×VDD by the assumption of composite logic cells. Then, the internal waveform of N2_1 can be rebuilt. Third, T(QN) -0.625 × TF(QN) implies the time that N2_2 reaches 0.5×VDD by the assumption of composite logic cells, which helps to rebuild the internal waveform of N2_2. After rebuilding the internal signals of the evaluation block, the similar approach for composite logic cells can be used to generate the composite triangular waveform of this DFF. Fig. 16. The signals in a DFF when Q is rising with active clock edge.
When the output Q is falling, the time when c reaches VT is defined as the start time of N2_1 because the gate G6 starts to transition when c reaches VT. Then, changing TR(Q) and TF(QN) to TF(Q) and TR(QN) respectively, the same approach for the Q rising case can be used to rebuild the internal signals when the output Q is falling.
With the two internal waveforms of N2_1 and N2_2, T START of the evaluation block is defined as the earliest start time of N2_1 and N2_2. T END of the evaluation block is defined as the time that both Q and QN complete their transitions. T PEAK can be calculated by the waveforms of internal nodes. The consumed internal energy of the evaluation block is the internal energy of total DFF minus the internal energy of the clock generator obtained in Sect. 3.3.1. After adding the energy of the output loading, the total triangle area of the evaluation block and the I PEAK of this block can be obtained. Finally, combining the waveform of the evaluation block with the waveform of the clock generator calculated in www.intechopen.com Sect. 3.3.1, the supply current waveform of the DFF in this case is obtained. The detailed formulas to construct the current waveform in this case are summarized as follows.

IR-Drop aware library adjustment methods
In this section, an analytical library adjustment approach is proposed to consider the effects of the supply resistors without extra characterization. The timing and power information stored in LIB file can be modified to reflect the effect of the supply resistor by the proposed equations. Therefore, the proposed gate-level supply current estimation method can obtain the accurate waveforms with IR-drop effects. Most importantly, this method can be easily embedded into present design flow to improve the accuracy of gate-level IR-drop analysis and provide designers a fast solution to consider IR-drop effect at early design stages. In this section, the adjustment methods of combination cells, simple logic and composite logic cells are discussed first in Section 4.1. Then, in Section 4.2, the methods of sequential cell are presented. Finally, the adjustment methods of activity files (VCD) are explained in Section 4.3. Figure 17 illustrates a simple cell with a supply resistor. In the output rising case, the supply current flows through the supply resistor, which increases the transition time due to the increased total resistance. Therefore, the RC charging model is used to calculate the increased transition time caused by the supply resistor.

Output transition time
R EFF represents the effective resistance of the cell. C EFF represents the effective capacitance of the cell. E INT and E LOAD represent the energy consumption caused by the cell and its output loading. In the output rising case, the C EFF is approximated by the total energy divided by supply voltage. Assume TR(Y) ORG represents the original transition time in LIB files. TR(Y) ADJ represents the adjusted transition time in the output rising case. The detailed corollary and the adjustment formula can be derived as follows, in which the increased term is related to the known variables (R WIRE , C EFF ) only. In the output falling case, the transition time is not changed because the current does not flow through the supply resistor. If there is a resistor in current path to ground, similar approach can be used to adjust TF(Y).  Fig. 18. The circuit structure of a composite cell (BUFFER) with a supply resistor in (a) the output rising case (b) the output falling case Figure 18 illustrates a composite cell with a supply resistor. Typically, this kind of cells is composed of multiple stages of simple cells. In Fig.18(a), the supply current flows through the second stage in the output rising case. The first stage is in the output falling case. Therefore, only the increased transition time of the second stage should be considered in the output rising case. Applying the same method for the simple logic cells on the second stage can obtain the increased transition time. In the output falling case, the output transition time is still not changed because the current does not flow through the second stage. Only the propagation delay may be changed in such case, which is discussed in the next section.

Propagation delay time
According to the same model shown in Fig.18, the adjustment method of the propagation time for simple logic cells can be derived. Similarly, only the increased propagation time in the output rising case should be considered to adjust the original timing information. The adjustment formulas are listed as follows, in which the increased term is related to the known variables (R WIRE , C EFF ) only.
() l n 0 . 5 For composite logic cells, the adjustment of the propagation time in the output rising case is the same with the simple logic cell as shown in Fig.18 (a). In the output falling case shown in Fig.18(b), C EFF is the internal capacitance C INT . This internal capacitance can be approximated as the E INT divided by the supply voltage because the operation current flows through the cell only. The adjustment formulas are listed as follows, in which the increased term is related the known variables only.

Internal energy
Assume E INT(ORG) represents the internal energy stored in standard libraries, and E INT(ADJ) represents the modified internal energy. This internal energy can be viewed as the shortcircuit energy by ignoring the effect of internal capacitances. Therefore, E INT(OLD) can be expressed as the short-circuit current (I SC ) times the duration of the short-circuit current (T SC ). Since I SC can be rewritten as VDD/ R INT , the E INT(ADJ) can be derived by the ratio of R EFF and R ADJ , as shown in the following equations. Please be noted that the R EFF can be calculated from the original propagation time because the short-circuit current happens at the logic transition period. www.intechopen.com

Timing and power adjustment of sequential elements
Only the output Q rising case is to explain the adjusted formulas because the formulas fir other cases can be derived by similar ways. One difficulty of the adjustment of DFF cases is to estimate the effective capacitance of the gate because the internal capacitance is unavailable. In this work, the internal energy is used to approximate the effective capacitance. The other difficulty is the adjustment of effective supply resistance because more than one gates switch in the DFF. Therefore, the simple parallel connection formula is applied first to approximate the effective supply resistance seen by each switching gate. The details of the adjusted formulas in the timing and internal energy are discussed in the following subsections.

Output transition time
Only the increased transition time caused by the output stage (G9) should be added to adjust the output transition time of output Q. The E INT (CK RISE Q RISE ) represents the internal energy consumption stored in the library for the output Q rising case when CK actives, which is composed of the energy of G1, G2, G6, G7, G9 and G10. The E INT (CK RISE ) represents the internal energy consumption of G1 and G2 when only CK actives. It implies that the energy consumption of G6, G7, G10 and G9 in Fig.19 can be calculated by E INT (CK RISE Q RISE )-E INT (CK RISE ). Therefore, the C EFF of the path through G9 can be approximated as a half of E INT (CK RISE Q RISE )-E INT (CK RISE ) divided by VDD because the energy are separated into two rising gates (G7 and G9).
When measuring the output transition time, three current paths travel through the R WIRE . Assume the three inverters G2, G7 and G9 have similar sizes, the equivalent supply resistor of each cell must be three times the lumped supply resistor (R WIRE ) according to the parallel connection formula. Therefore, the adjusted formula is modified a little bit as follows. The falling time of QN (TF(QN)) is not necessary to be adjusted because it is a falling gate. The adjustment formulas for the output transition time in output Q falling case are also listed as follows, which can be derived by similar way as in the output Q rising case.
The propagation delay time of the output QN TDF(CK QN) ADJ can be calculated by the similar approach of TDR(CK Q) ADJ . The adjustment formula is listed as follows, except that G7 is used instead of G9 for different output. Figure 20 illustrates the internal status of a DFF when data is setting up. Following the same assumption of the setup time in Section 3, the data must reach N1_2 before the internal node c rises to ensure that the data can enter the next stage successfully. Therefore, the setup time of the D rising case TSR(D) can be expressed as the following formula. (1 _ 2 ) ( l n 0 . 5 )

Setup time
Therefore, the formula of the adjusted setup time TSR(D) ADJ can be obtained as follows. The setup time in the D falling case can be obtained by the similar way. The formula is also listed as follows.

Internal energy
The internal energy of DFF cannot be separated to each cell. Therefore, the entire DFF is viewed as a super-gate to adjust its internal energy. The same formulas of the composite logic cells are used directly to adjust the internal energy of DFF.

Timing correction of cell switching activities
During gate-level simulation, the signal events are recorded in activity files (.vcd). Figure  21(a) shows the ideal timing diagram of four events, T(A), T(B), T(C), T(Y). With non-ideal supply lines, these events will occur at different time thus incurring different current waveforms. Therefore, the modification of activity files is also proposed in this paper, as illustrated in Fig.21(b). First, the modified propagation delay time TD(G1) ADJ can be obtained by the modification method of the signal cell. Then, Diff(G1) can be implied by TD(G1) ADJ -TD(G1) ORG and be propagated to next event T(B). T(B) ADJ is derived by the summation of T(B) and Diff(G1). The other events can be modified in the similar way. After the timing errors are corrected, the accuracy of the constructed waveforms based on those events can be further improved.

Experimental result of supply current waveform estimation method
We have implemented a supply current waveform estimation tool in C/C++. Given an input pattern, this tool can calculate the triangle that simulates the supply current waveform of each cell. The overall supply current waveform is then obtained by combining all triangles of every changed cell in time. All the input files of this tool follow standard formats, which are Verilog netlist file of the gate-level design, value changed dump (VCD) file of the design under given input patterns, and the LIB file of the standard cell library. The output format is a (time, voltage) pair that can be used to plot the dynamic supply current waveform. Those input/output files are compatible with current EDA tools. It allows our solution to be plugged into the existing EDA flow smoothly.
Very few commercial tools can provide the current waveform information at gate level. We choose PrimeTime-PX (Synopsys, 2009) (Shimazaki et al., 2000) is also rebuilt in our environment and tested in the same experiments to show our improvements on accuracy. Because they did not mention how to apply their approach on sequential cells, only combinational circuits are compared.
In the experiments, ISCAS'85 and ISCAS'89 benchmark circuits, which are implemented with TSMC 0.13um process, are used to test the accuracy. For each benchmark circuit, 200 random patterns are generated to trigger the circuit. After all, the average errors of the peak current and position with 200 pattern-pairs are shown in the row eI p of Tables 1 and 2. The standard deviation of the peak current and position with the 200 results is shown in the row sI p of Tables 1 and 2. The last column AVG in Tables 1 and 2 shows the average values of all cases. Figure 22 shows the estimated current waveforms of c7552 and s9234 as examples, which are very similar to HSPICE results.
According to the results estimated by PrimeTime-PX, the CCSM libraries significantly improve the accuracy of peak current estimation. However, the cycle-accurate results are still not accurate enough for analyzing the peak power or the IR-drop noise. The estimation results of the proposed methods, which are listed in the row GCM of Tables 2 and 3, demonstrates that the proposed approach can provide accurate estimations on the supply current waveforms by using the same information provided in traditional LIB libraries. The average estimation errors on eI PEAK and eT PEAK are about 10% with small standard deviation. The correlation between the estimated waveforms and HSPICE waveforms is higher than 0.97, which shows the similarity between the two waveforms. Compared to the rough estimation in (Shimazaki et al., 2000), the proposed approach does have a significant improvement on the estimation accuracy. Most importantly, the proposed approach can deal with sequential circuits, which enables this approach to be applied to modern designs.
The run time of the current waveform estimation for each benchmark circuit is provided in Table 3, which is measured on a XEON 3G machine with 2G RAM. The row GCM shows the run time of the proposed approach in seconds. The row HSPICE shows the run time of HSPICE simulation with the same patterns in hours. The row Ratio shows the ratio of the run time between HSPICE and GCM, which demonstrates a significant speed improvement. Fig. 22. The estimation supply current waveforms of (a)c7552 (b)s9234.  Table 3. Experimental results of run time

Experimental result of library adjustment method
In order to demonstrate the accuracy of the IR-drop-aware adjustment approach, the same ISCAS85 and ISCAS89 benchmark circuits are used to perform some experiments. For each benchmark circuit, 200 random pattern pairs are generated to trigger the circuit. The average results of all circuits are illustrated in Fig.23. The average peak current errors using the method without adjustment the library information is draw with dash lines (w/o). The proposed library method is draw with bold line(w). According to the results, the proposed www.intechopen.com Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 207 method can reduce the estimation errors successfully. Figure 24 shows the estimated supply current waveforms of c7552 circuit as example, which also confirm the accuracy of the proposed approach (GCM (ADJ) ). The waveforms obtained without IR-drop consideration (GCM) are also used to estimate the IR-drop directly with the same input pattern. The results show that estimation without considering R wire effects suffers large errors when the resistance on supply lines is getting larger. The proposed adjustment can consider the R wire effects and have a significant improvement on accuracy.

Conclusion
In this article, a library-based IR-drop estimation method is presented. This method concludes two parts, one is a gate-level supply current waveform estimation method using standard library information and the other is an analytical library adjustment method with IR-drop effect consideration. Extra characterization efforts and regression cost can be avoided to obtain accurate IR-drop estimation with less overhead. As shown in the experimental results, such an efficient modification method can provided good accuracy on IR-drop estimation with limited information. The estimation errors of our approach are about 5% compared with HSPICE results.