Character Projection Lithography for Application-Specific Integrated Circuits

In the recent fabrication of semiconductor devices, quite various devices are produced while most of them result in small production volumes. A small production volume of ICs leads to a rise of the price of an IC because the expensive investment made in its photomask set must be redeemed by passing on the price. The price of photomasks increases rapidly as the transistor integration advances. The price of photomasks has a great impact on the price of semiconductor devices. Electron beam direct writing (EBDW) is a solution to fabricating small-lot ICs at a cheap cost. The EBDW can draw patterns onto silicon wafers masklessly or quasi-masklessly (Inanami, 2000; Pfeiffer, 1979). The throughput of the conventional EBDW equipment which adopts the variable shaped beam (VSB) method (Pfeiffer, 1978) is, however, extremely low. In the VSB method, exposed patterns are divided into a large number of small rectangular and triangular shapes to draw them as shown in the left of Fig. 1. In this figure Letter “E” is divided into four rectangles and consequently needs four “EB shots” to be drawn. The conventional VSB equipment shoots rectangular and triangular shapes onto silicon wafers and results in a lot of EB shots, which deteriorate the throughput of the equipment.


Introduction
In the recent fabrication of semiconductor devices, quite various devices are produced while most of them result in small production volumes. A small production volume of ICs leads to a rise of the price of an IC because the expensive investment made in its photomask set must be redeemed by passing on the price. The price of photomasks increases rapidly as the transistor integration advances. The price of photomasks has a great impact on the price of semiconductor devices. Electron beam direct writing (EBDW) is a solution to fabricating small-lot ICs at a cheap cost. The EBDW can draw patterns onto silicon wafers masklessly or quasi-masklessly (Inanami, 2000;Pfeiffer, 1979). The throughput of the conventional EBDW equipment which adopts the variable shaped beam (VSB) method (Pfeiffer, 1978) is, however, extremely low. In the VSB method, exposed patterns are divided into a large number of small rectangular and triangular shapes to draw them as shown in the left of Fig. 1. In this figure Letter "E" is divided into four rectangles and consequently needs four "EB shots" to be drawn. The conventional VSB equipment shoots rectangular and triangular shapes onto silicon wafers and results in a lot of EB shots, which deteriorate the throughput of the equipment. Character projection (CP) lithography is a promising one in which a pattern more complex than a triangle or a rectangle, called a character, is projected onto a silicon wafer with an EB shot as shown in the right of Fig. 1 (Sakitani et al., 1992;Hattori et al., 1993;Hirumi et al., 2003;Inanami et al., 2000;Inanami et al., 2003;Nakamura et al., 2006;Nakasugi et al., 2003). The e-BEAM Corporation developed a low-energy electron beam direct writing (LEEBDW) system, which was named "EBIS" (Electron Beam Integrated System) (Inanami et al., 2000;Inanami et al., 2003;Nakamura et al., 2006;Nakasugi et al., 2003). The system can accommodate 400 characters on a CP aperture mask and any character can be chosen at every EB shot, so that the throughput of the system can be enhanced quite effectively with the CP lithography. The projection system can also project rectangular and triangular shapes with the VSB lithography. Their system is capable of projecting patterns with both the VSB and CP lithographies.  Yasuda et al. proposed a multi-column-cell (MCC) system, which can project multiple characters in parallel by equipping it with multiple projection mechanisms called columncells (Yasuda et al., 2004). The motivation to develop the MCC system is to achieve higher www.intechopen.com throughput to produce ICs than sequential projection systems by parallelizing projection operations. Several ASIC design techniques were discussed (Sugihara, 2008(Sugihara, , 2010. This chapter focuses on design techniques for single-column-cell projection equipment.

Cell library development for character projection equipment
Standard cell methodology is a quite popular design method to design an ASIC. The standard cell methodology exploits a cell library which is a collection of low-level logic functions, called cells, such as NAND gates, NOR gates, flip-flops, latches and buffers. From a viewpoint of character projection lithography, it is important to project as many cells as possible with character projection lithography. Cell library development methodologies were studied for character projection lithography (Sugihara et al., 2005, 2006a, 2006c, 2007b, 2008, 2010, Inanami et al., 2000. In this section, we focus on a cell library development methodology for a single-column-cell system (Sugihara et al., 2005(Sugihara et al., , 2006a(Sugihara et al., , 2006c(Sugihara et al., , 2007b. Cells, which are components for IC designs, are ordinarily utilized as the basis of characters. The characters are placed in an array on a CP apertu re mask as sho wn in F ig . 4. It accommodates several hundred characters, which are several-m squares.

Cell selection for CP aperture masks
In this section, a mathematical programming model is shown to select an optimal set of cells which are placed on a CP aperture mask so that the number of EB shots to draw an entire chip is minimized. Before we describe the mathematical programming model, we briefly describe the ILP (Integer Linear Programming) to review. The ILP is a well-known way to minimize loss or maximize benefit in logistics, transportation, manufacturing and so forth (Williams, 1999). The goal of the ILP is to minimize (or maximize) a linear objective function on a set of integer variables, while satisfying a set of linear constraints. A typical ILP model can be described as follows: minimize: (1) subject to: , such that where Ax is an objective function to minimize, A is an objective vector, B is a constraint matrix, C is a column vector of constants, and x is a vector of integer variables. Efficient ILP solvers are now readily available (ILOG, 2003). A mathematical formulation is shown to select an optimal set of the cells which are placed on a CP aperture mask so that the number of EB shots to draw an entire chip is minimized We name this mathematical problem ("A" stands for assignment). The problem can be stated as follows: For given kinds of cell objects, their reference counts , ,⋯, , their EB shots by the CP method, , ,, , their EB shots by VSB method, , ,⋯, , and a CP aperture mask capable of loading characters, determine each cell's drawing method, the CP or VSB method, such that the total EB shots to draw the entire chip are minimized. This problem is a typical combinatorial optimization problem and can be shown to be NPhard. However, for realistic cell libraries, the sizes of the problem instances are small. The problem instances can be solved exactly using an ILP solver within short computation time.
To model this problem, consider a chip for which kinds of cell objects are employed. Cell appears times in the chip and is drawn with either the CP or VSB methods. If Cell is drawn with the VSB method, let the number of EB shots to draw a cell instance of Cell be . Likewise, If Cell is drawn with the CP method, let the number of EB shots to draw a cell instance of Cell be . We introduce binary variables (where ), which are used to determine a projection method of cells, that is the CP or VSB method. Let be a binary variable defined as follows: if cell object is drawn with the CP, if cell object is drawn with the VSB. ( The total number of EB shots is to draw the entire chip is given by EB shots with the CP EB shots with the VSB ∑ ∑ ∑ ∑ . ( The second summation in the above equation does not include any variables so only the first summation is considered in the objective function of Eq. (1).

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Depending on the size of a cell object, the number of characters to draw a cell instance of the cell object may differ from that of another. Cell occupies characters on a CP aperture mask. The area of the CP aperture makes a constraint on the number of characters. The following constraint, therefore, is introduced.
where is the maximum number of characters available on the CP aperture mask, is the number of characters necessary to draw an instance of Cell and is equivalent to . From Eqs. (1), (2) and (3), a mathematical programming model for this problem can be formulated as follows. Objective: Minimize ′ ∑ , subject to ∑ , i.e. every cell adopts one drawing method, the CP or VSB in conformity with the restriction of the area of the CP aperture. The total number of EB shots is given by ′ ∑ . The above model mainly aims to develop an optimal cell library set dedicated to a product but can be applied to developing a general cell library to various products. In order to make a cell library more general among multiple products, the reference counts of cells defined as should be set as the reference counts of cells through the total production of the multiple products. Both dedicated and general cell libraries can be easily obtained by our proposal once the reference counts of cells are given. The decision to make a cell library of a product dedicated or general is made by the following two factors. The cost reduction by reducing the number of EB shots with a newly developed set of CP aperture masks. The cost increase to newly develop the set of CP aperture masks dedicated to a product. Even if CP aperture masks are made to dedicate to a product, the total cost for the CP aperture masks is much cheaper than that for the photomask costs of the other lithography. The total amount of data to draw patterns on masks is a dominant factor in the costs of the both kinds of masks. The amount of data for photomasks is linear to the number of transistors while that for CP aperture masks to the number of cell objects on them. The developing cost of CP aperture masks is, therefore, much cheaper than that of photomasks. The CP lithography with a set of CP aperture masks is still quasi-maskless in terms of cost.

The impact of cell directions on area and delay
There are basically four directions of cells as cell instances are physically placed as shown in Fig. 5. A basic direction is literally a basis of the other directions. Mirror-X, mirror-Y and mirror-XY directions are horizontally-flipped, vertically-flipped and horizontally-andvertically-flipped ones respectively. The patterns of these directions of a cell function must be distinguished from the other as different patterns on CP aperture masks. In this section, we examine the influence of the existence of the cell directions on both area and delay time of a chip. We used a logic-synthesizable benchmark circuit which was a Z80compatible microprocessor. We used a cell library whose feature size was 0.35 m. The logic synthesis for the circuit was done with Synopsys Design Compiler (Synopsys, 2005). Placeand-route was done with Avant! Apollo (Avanti, 1998). Delay times for four cell directional variations are shown in Table 1. In the table, the four-bit vectors which follow "Conf. X" denote the existence of the four cell directions in the processes of place-and-route. The first bit of the vectors denotes the existence of the basic direction. If the direction is taken into account, the number is 1, otherwise 0. Likewise, the second, third and fourth bits denote the existences of the mirror-X, mirror-Y and mirror-XY directions respectively. A number in each column denotes the delay time with the least area "N/A" means that the given areas were infeasible to place and route the circuit with the place-and-route tool. For example, the least area and the delay time for the area were obtained as . and 7.09 ns respectively in Conf. 1. The least areas in Confs. 1, 2, 3, and 4 were . , . , , and . respectively. About 14% area increased when the mirror-Y and the mirror-XY were forbidden. Theoretically speaking, delay time decreases under a case in which one can use a larger place-and-route area. Delay time in a column of the table is expected to decrease downward but it did not. This is because the CAD tool is based on approximate algorithm. Comparing the two values of Conf. 2, 6.6% delay time increased while place-and-route area increased. Conf. 1 is the configuration in which all the four cell directions are available and is supposed to be best with regard to area and delay time among the configurations because its design space includes design space of the other configurations. In other words, any layout based on Confs. 2, 3 or 4 can be realized by Conf. 1. The results which the CAD tool reported does not straightforwardly reflect this supposition because the layouts obtained by the CAD tool are approximate solutions, e.g. the delay time of Conf. 2 (6.97 ns) was shorter than that of Conf. 1 (7.09 ns) as the place-and-route area was . ! Conf. 2 is the configuration in which the horizontal flippings are removed from Conf. 1. In other words, the mirror-X and mirror-XY directions are not taken into account in Conf. 2. There was no great difference of delay times among Confs. 1 and 2. Horizontal flipping seems not to be so effective to reduce delay time and area. Conf. 3 is the configuration in which the vertical flippings (mirror-Y and mirror-XY) are removed from Conf. 1. Experimental results show that the vertical flipping of cells had little influence on delay time of the chip and it had some influence on the area. Comparing Conf. 3 with Conf. 1, about 14% area increased. This is because the gaps between cell areas were added by eliminating vertical flipping of cells and each cell area got to own its own power and ground lines. Conf. 4 is the configuration in which any flipping cells are forbidden and only a basic direction of cells is available. Comparing Conf. 4 with Conf. 1, the differences of the delay times were insignificant while those of the areas were noticeable, that is about 14% area increase. This is because of the same reasons that the area of Conf. 3 increased. Comparing Conf. 4 with Conf. 3, the differences of their best delay times were insignificant while those of their areas were about 4.2%. Horizontal flipping had some influence on the area increase as vertical flipping was completely forbidden. There was no great difference among delay times between the four configurations. It was experimentally confirmed that cell directions were not strongly relevant to the increase of delay time. The existence of vertical flipping of cells was relevant to increase of area. This was because gaps between cell areas come to arise and each cell area got to own its own power and ground lines.

Case study
In this section, a case study is shown for five cases to examine the relation between the number of EB shots and how to select cell objects to place on characters. The five cases are described in Table 2. We developed the cell selection software described in Section 2.1.1 with a commercial mathematical optimization engine, ILOG CPLEX 9.0 (ILOG, 2003). Every optimization process finished within a second.

Case 1
Only a basic cell direction is available. The optimal set of cells is exactly searched out by solving an ILP problem instance.

Case 2
The basic and Mirror-Y directions are available. It is assumed that the reference count of a direction of a cell function is equal to that of the other direction of the cell function. Each direction is assigned 1/2 of available characters to. This is after the fashion of Inanami's (Inanami, 2000).

Case 3
The basic and Mirror-Y directions are available. Cell objects to be placed on a CP aperture mask are exactly searched with our cell selection method.
Case 4 The four cell directions are available. It is assumed that the reference count of a direction of a cell function is equal to that of the other directions. Each direction is assigned 1/4 of available characters to. This is also after the fashion of Inanami's (Inanami, 2000) Case 5 The four cell directions are available. Cell objects to be placed on a CP aperture mask are exactly searched with our cell selection method.

Table 2. Cell directional variations for experiments
The specification of the CP equipment for which we assumed is shown in Table 3. Two benchmark circuits were used to examine their numbers of EB shots under the five cases. The description for the benchmark circuits is shown in Table 4. Note that the cell library is from academia and comprises fewer kinds of cells than that from industry.
The maximum width and length of rectangles for VSB 3.5 m The width and length of characters for CP 5 m The number of characters on a CP aperture mask 400  According to Table 5, as the number of cell objects increases, in other words, the number of cell directions increases, the number of EB shots increases. This is because the reduction of cell directions enables more cell functions to be on a CP aperture mask and to be projected with the CP. The area of Circuit 2 under Case 1 was largest among the five cases as shown in Table 6 because only a single direction, that is a basic direction, was adopted for place-androute. This was because the gaps between cell areas came to arise and each cell area got to own its own power and ground lines. Theoretically speaking, the design with the four cell directions should be best among the five cases with regard to area and delay time. Similarly, the design with the two cell directions should be intermediate. The experimentally obtained values of areas do not reflect this supposition. The delay time of Circuit 2 under Cases 2 and 3 was found best. This is because the CAD tool returned approximate solutions of layout and happened to result against the supposition. Note that the values shown in Table 1 and Table 6 are nothing more than the ones the CAD tool reported. If a design obtained with the two cell directions is better than a design obtained with the four cell directions, the design of two-cell direction may be adopted as a design of four-cell direction.
Comparing the number of EB shots of Circuit 1 under Case 4 with that under Case 5, 3.85% reduction of the number of EB shots was achieved. The difference in the numbers of EB shots was caused by solving the problem instances exactly or approximately. The optimal sets of cells was selected exactly under Cases 3 and 5 while sets of cells was selected It was experimentally found that the elimination of cell directions is quite effective to reduce EB shots. It was experimentally found that the elimination of horizontal flipping reduced the much number of EB shots effectively while it has small impact on area and delay time of chips.

Conclusion
In this section, we proposed an ILP-based cell library development methodology to reduce the number of EB shots. All optimization processes finished within a second. More than 3.85% reduction of EB shots was achieved only by distinguishing between the differently mirrored cells whose functions are identical. We examined the influence of cell directions on both area and delay time of the circuit. It was experimentally confirmed that both of the horizontal and vertical flipping of cells had little influence on delay time of chips. The horizontal flipping had little influence on area while the vertical flipping had some influence on area. This examination helps which cell direction should be implemented on CP aperture masks. The forbiddance of horizontal flipping caused little deterioration of area while 25.6% reduction of EB shots. It was found that the forbiddance of horizontal flipping was effective to reduce the number of EB shots while it deteriorated little area and delay time of chips. The forbiddance of vertical flipping caused 13.9% increase of area while it caused less than 1% increase of delay time. The forbiddance of vertical flipping should be determined with taking a tradeoff between area and EB shots into account. For many chips of the state of the art, cells are placed so "loosely" that the deterioration of area caused by forbiddance of multi directions of cells might have less impact on area. The relation between cell directions and EB shots in design of such chips should be further examined as future work.

Character size optimization for higher projection throughput
Character size optimization techniques were studied for character projection (Sugihara, 2006c(Sugihara, , 2007b(Sugihara, , 2010. We first presented an idea to optimize a character size for higher projection throughput (Sugihara et al., 2006c). We presented a character size optimization by enumerating all possible character sizes and generating a cell library for every given character size (Sugihara et al., 2006c). Next we presented a cell library development methodology in which a character size and a set of cells were optimized at the same time (Sugihara et al., 2007b). We also presented a character size optimization technique for multicolumn-cell projection equipment. In this section, we focus on the first work (Sugihara et al., 2006c) for a simple explanation.

Character size optimization problem
In Section 2, the size of characters on CP masks was given and treated as a constant because of the restriction which attributes to character projection equipment. Cells used in a design were, consequently, partitioned to fit the constant size of characters by intuition. In this section, we present a character size optimization problem to minimize the number of EB shots, which affect the throughput of the CP equipment ("S" stands for size). The mathematical problem can be stated as follows. For given kinds of cell objects, their reference counts , ,⋯, , the numbers of their EB shots by the CP method, , , the numbers of their EB shots with the VSB method, , ,⋯, , the width and length of a CP mask, and , and the gap between neighboring characters, , determine the length and width of characters, and , and each cell's drawing method , that is the CP or the VSB method, such that the number of the total EB shots to draw the entire chip is minimized. The number of EB shots of each cell with the CP method depends on both the size of characters and a pattern of a target layer. After the fashion of Equation (3) Depending on the size of a cell, the number of characters to draw a cell instance varies from cell to cell. The area of the CP mask makes a constraint on the number of characters. The following constraint, therefore, is introduced.
where , is the number of characters on the CP mask for Cell and is equal to the number of its EB shots , with the CP method, , , , , is the maximum number of characters available on the CP mask when the length and width of characters are and respectively, the length and width of a CP mask are and respectively, and the gap between characters is . Equations (5) and (6) include nonlinear terms and need to be linearized if we solve this problem as an ILP problem. We did not linearize this problem but enumerate problem instances by varying both and . Both and are discrete with a narrow range. The character size enumeration results in a small number even if all problem instances are enumerated. Problem can be easily solved by enumeration of Problem .

Case study
We developed software to optimize the character size and select an optimal projection method for every cell so that the number of EB shots to draw an entire chip is minimized. In this development, a commercial mathematical optimization engine, ILOG CPLEX 9.0 (ILOG, 2003), was utilized. We examined the numbers of EB shots for four benchmark circuits described in Table 7. All cell libraries adopted for the four circuits include more than 300 cell functions while each circuit consists of less than 100 cell functions as a result of logic synthesis. Cells which are logically identical but are differently mirrored must be distinguished from one another on CP masks. The numbers of cell objects with or without mirroring considered are shown in the table. The numbers of cell instances are also shown in the table. Note that the size of Problems and are not affected by the number of cell instances but by that of cell objects. The number of cell instances affects the reference counts of cells, which are constants in the ILP model. It is the number of cell objects that is equal to the number of variables in Problem and affects the size of problem instances. The www.intechopen.com experiments were based on the CP equipment which was described in Table 8. In the equipment, patterns on CP masks are demagnified to 1/5 on a wafer and all the values on the table are demagnified to 1/5 on silicon wafer. This means that a CP mask is capable of 441 characters of a 5.0 m-square which occupies a 25.0 m-square on CP masks. We assumed that the maximum size of an electron beam for the CP is a 10 m-square on silicon wafers with the state-of-the-art electron beam technology. The length and width of CP masks 650 Gap between neighboring characters 5 The maximum length of characters 50 Table 8. Description for CP equipment We examined the numbers of EB shots to draw a polysilicon gate layer of the devices under three cases shown in Table 9. In Case 1, we assumed that characters were 5.0 m-squares. These values were given in Inanami's work (Inanami, 2000) and this size was based on the specification of the CP equipment. In Case 2, it was assumed that the size of electron beams was smaller than a 10 m-square and the character size was optimized under the character size constraint. In Case 3, we assumed that any size of an EB was available and the character size was optimized under the character size constraint. Conventional square. This value is given from the equipment specification.

Case 2 Searched Searched within feasible beam-size
Optimal rectangle with feasible beam-size.

Case 3 Searched Searched within any beamsize
Optimal rectangle with ideal beamsize. The numbers of EB shots obtained by our experiments are shown in Table 10. Comparing Case 1 with Case 2, 72.0% of EB shots was reduced in the best. The feasible EB size was utilized in both Cases 1 and 2 and the difference between them was whether or not the character size was optimized. The gap between Cases 1 and 2 implies that the beam size of the CP equipment should be configurable for users so that the throughput of their equipment can be increased. Supposing any size of EBs can be utilized, more reduction of EB shots can be achieved as the numbers in Case 3 in Table 10 show. Comparing Case 1 with Case 3, 75.9% of EB shots was reduced in the best. Comparing Case 2 with Case 3, 39.5% of EB shots were reduced in the best. The gap between Cases 2 and 3 implies that the development effort to seek for a larger size of EBs is capable of reducing 39.5% of EB shots. The gap between Cases 2 and 3 is directive for equipment developers to determine the EB size of their equipment. The computing platform for experiment was an Intel Pentium 4 2.4 GHz with 1 GB of main memory. Computation times to obtain the optimal character sizes under the three cases were shown in Table 11. All character size optimization processes were finished within less than two minutes. Note that computation time was not affected by the number of cell instances but by the number of cell objects. All character size optimization processes were done within practical computation time.

Conclusion
We proposed the character size optimization technique for improving the throughput of the CP equipment by defining a mathematical problem as an ILP problem. We also showed some experimental results by solving mathematical program instances for several benchmark circuits. According to our experiment, 72.0% reduction of EB shots was achieved with a feasible EB size in the best, comparing with the conventional and intuitional character sizing. It was experimentally found that our character size optimization technique was so Fig. 6. The number of EB shots for Circuit 3 effective to reduce the number of EB shots. The experimental results imply that the CP equipment should be capable of modifying the size of characters by customers' demands after it is shipped out to them. Our systematic character size optimization scheme can achieve the lower number of EB shots and can enhance the throughput of the CP equipment. The throughput enhancement of the CP equipment causes the higher production volume of semiconductors devices at a lower cost. It consequently accelerates the application of semiconductor devices to various industrial fields even if their production volumes are small. Likewise, the throughput enhancement of the CP equipment promises a lower cost in developing photomasks if the CP method is utilized in developing photomasks in the future.

Technology mapping technique for character projection equipment
Technology mapping techniques were discussed for character projection lithography of a single-column-cell system (Sugihara et al., 2006b(Sugihara et al., , 2007c. A technology mapping technique was also proposed for a multi-column-cell system (Sugihara et al., 2007a). This section mainly discusses a technology mapping technique which reduces projection time of a singlecolumn-cell system (Sugihara et al., 2006b(Sugihara et al., , 2007c.

Review on technology mapping
In the most popular paradigm for logic synthesis, after a technology independent optimization of a set of logic equations, the result is mapped into a feasible circuit which is optimal with respect to area and satisfies a maximum critical-path delay. In this paradigm, the role of technology mapping is to finish the synthesis of the circuit by performing the final gate selection from a particular cell library. The role of technology mapping is the actual cell choice to implement the equations -for example, choosing the fastest cells along the critical path, and using the most area-efficient combination of cells off the critical path (Hachtel, 1996). A set of base functions is chosen such as a two-input NAND-gate and an inverter. The logic equations are optimized in a technology-independent manner and are then converted into a graph where each node is restricted to one of the base functions. This graph is called the subject graph. The logic function for each library gate is also represented by a graph where www.intechopen.com each node is restricted to one of the base functions. Each graph for a library gate is called a pattern graph. For any given logic function there are many different representations of the function using the base function set. Therefore, each library gate is represented by many different pattern graphs (Hachtel, 1996). Let us see some examples of technology mapping for the following Boolean network: The Boolean network and its subject graph are shown as Fig. 7 and Fig. 8. Note that a twoinput NAND-gate and an inverter are chosen as the base functions. Fig. 9 and Fig. 10 show differently technology-mapped circuits for the original one.

Linear combination of area and the number of EB shots
The conventional technology mapping does not consider the number of EB shots for the CP lithography because most ICs are fabricated with photolithography. The price of a photomask set is getting unaffordable and the CP lithography will be utilized gradually. This section discusses how to treat the number of EB shots to project an entire IC in the process of technology mapping. Now let us discuss the objectives in technology mapping. The area of a circuit is simply represented with the sum of areas of the cell instances which are utilized for realizing the function the designers want and is shown as follows: where Area , Ref , and Area are the total area of the IC, the reference count of Cell Function , and the area of an instance of Cell respectively. Likewise, the number of EB shots to project the entire IC is shown as follows: where Shots and Shots are the number of EB shots to project entire IC and that to project an instance of Cell Function respectively. In the conventional IC design, only Equation (6) is minimized under a timing constraint. In the design adopting the CP lithography, both of Equations (6) and (7) must be taken into account to fabricate small ICs within short fabrication time. We introduce the linear combination of Area and Shots as follows: where and are some constant values and should be chosen depending on the importance of area and EB shots. Technology-mapped circuits which are implemented with small area and a small number of EB shots can be obtained by minimizing the objective values in Equation (10) under a timing constraint.

Case study 4.3.1 Experimental setup
We have developed a design framework in which both area and the number of EB shots can be optimized in the process of technology mapping as shown in Fig. 11. The design flow www.intechopen.com starts with the generation of a cell library for the CP lithography. The cell library for the CP can be directly applied to a commercial logic synthesis tool. Once ASIC designers obtain the cell library for the CP, they can logic-synthesize their circuit in the same manner as the typical logic synthesis flow. Fig. 11. Design flow in our design framework In the design framework, a conventional cell library, the number of EB shots for every cell function, and a projection method for every cell function are required for generating a cell library specialized in the CP. The optimal projection method for every cell function can be obtained with the cell library development methodology, which we proposed in the previous work (Sugihara et al., 2005(Sugihara et al., , 2006a. The simplified procedure for choosing the optimal projection method for every cell function is summarized as follows. 1. Obtain the reference counts of all cell functions, their numbers of EB shots to project a cell instance with the CP and VSB lithographies, and the number of characters available on a CP aperture mask. 2. With the above numbers, solve the mathematical problem instance shown in the previous work (Sugihara et al., 2005(Sugihara et al., , 2006a. A solution to the mathematical problem instance specifies the optimal projection method for every cell functions. To obtain the projection method for every cell functions, we have utilized a benchmark circuit, b19 from the ITC'99 benchmark circuit suite (Davidson, 1999), as a referential circuit. The benchmark circuit has been logic-synthesized to minimize its area and then the mathematical problem instance has been solved for its netlist with a commercial ILP solver (ILOG, 2003). We adopted commercial EDA tools as possible as we could in order to reduce software development. For the design framework, we have adopted the Synopsys Design Compiler as a logic synthesis tool and the Synopsys Library Compiler as a cell library generation tool. A cell library specialized in the CP (written in the Synopsys ".lib" format) has been generated with the following three things: a conventional cell library (also written in the Synopsys ".lib" format), the numbers of EB shots which are needed to project an instance of every cell function with the CP and VSB lithographies, and the optimal projection method of every cell function. In the cell library file format specification for the Design Compiler, the attributes designating area, delay, and power can be specified for each cell function but the number of EB shots cannot be specified. The attribute "area" has been used to represent both area and the number of EB shots by setting the linear combination of them as the attribute "area" for making the Design Compiler capable of optimizing them. And then the ".lib" file of the cell library has been converted into the Synopsys ".db" format file with the Synopsys Library Compiler.
We have utilized two cell libraries, high-performance and low-power ones, which were provided by the VLSI Design and Education Center (VDEC) at the University of Tokyo, as conventional cell libraries. The technology node of the two cell libraries was 0.35 m. We have demagnified all patterns of the two cell libraries by a factor of 90/350 in order to simulate the number of EB shots at the 90 nm technology node. With the two conventional cell libraries, we have generated cell libraries specialized in the CP system whose specification is shown in Table 12. The numbers of cell functions, on-characters cell functions, and off-characters cell functions are described in Table 13. Note that the cell libraries were supplied from academia and the number of cell functions is smaller than commercial ones. This means that the usage of an industrial cell library increases the number of off-characters cell functions and possibly deteriorates the throughput of the projection system in exchange for more design flexibility.
The maximum width and height of rectangles for VSB 3.5 m The width and height of characters for CP 5.0 m The number of characters available on a CP aperture mask 440

Experimental results
We examined the numbers of EB shots to project several benchmark circuits with the two cell libraries. First, we examined the relation between area and the number of EB shots to project each of ITC'99 benchmark circuits (Davidson, 1999). In the examination, all circuits were logicsynthesized for two objectives: area-minimization (=1, =0 in Equation (8)) and EB-shotsminimization (=0, =1 in the equation). The purpose of this examination was to obtain the minimal values of both area and EB shots of all benchmark circuits. We logic-optimized each of circuits ten times and have taken the best value of area and EB shots among the results. Fig. 12 and Fig. 13 show area and shots ratios for both area-minimized logic synthesis (=1, =0) and shots-minimized one ( = 0,  = 1) with the two cell libraries, respectively.  Changing ratio /, we examined the relation between area and the number of EB shots for a benchmark circuit, b18_1, as shown in Fig. 14. We show the range of both area and the number of EB shots observed in the process of ten logic optimizations in the figure in order to observe the tendency of area and the number of EB shots to change. This is because the logic synthesis tool returns quasi-optimal circuits with some variation of both area and EB shots and makes it hard to observe a consistent tendency of them. The figure shows that area tends to increase as the ratio / increases while the number of EB shots tends to decrease. These results show that there exists a tradeoff between area and the number of EB shots. We think that area-saving and off-characters cell functions are mapped as area is important. Such cell functions are substituted on-characters ones as the number of EB shots becomes important. ASIC designers should choose the ratio / according as they want to reduce area or the number of EB shots.  We have examined area and the number of EB shots under several timing constraints with a Z80-compatible processor. Fig. 15 and Fig. 16 show area and the number of EB shots under various timing constraints. When timing constraints were given, the effectiveness of the shots-minimization and area-minimization became less but the number of EB shots was reduced up to 26.6% nevertheless. The area increase accompanied with EB shots minimization was from 10.6% to 46.2%. These results show that area and the number of EB shots decreased as the timing constraint was loosened. We think that there exists a tradeoff between delay time and the number of EB shots (or area

Conclusion
Our technology mapping technique for the CP lithography achieved a 54.6% less number of EB shots with 8.4% area increase under no timing constraints than the conventional one. Our technology mapping for the CP lithography also achieved a 26.6% less number of EB shots with 41.1% area increase and without any performance degradation than the conventional one. Varying the ratio /, we found that there exists a tradeoff between area and the number of EB shots. In the other experiments, tightening timing constraint increased area and the number of EB shots. It was found that there exists a tradeoff between delay time and the number of EB shots. We think that a timing constraint for shorter delay time has caused a logic synthesis tool to choose the off-characters cell functions that have higher current drivability. Our technology mapping technique reduced the number of EB shots to project patterns for the FEOL with some area increase. It is probable that some increase of cell instances causes the number of wires to increase and does the number of EB shots for projecting the BEOL patterns to increase. A technology mapping technique should be studied for reducing the number of EB shots required for both the FEOL and the BEOL patterns as future work. The number of cell functions which are placed on a CP aperture mask will increase as the technology node proceeds. It is probable that all cell functions of a commercial cell library, which includes more than 500 cell functions, will be placed on a single CP aperture mask at the 32 nm technology node. This indicates that the VSB lithography will be required less and less for projecting such cell functions. We suppose that our technology mapping technique is effective before the 32 nm technology node. We think that another technology mapping technique will be needed to increase throughput of MCC systems after the 32 nm technology node. It is easy for both IC designers and equipment developers to adopt our technology mapping technique because a software approach such as our technique imposes no modification on CP equipment. This means that no additional cost is necessary to adopt our technique in their IC design.

Conclusion
Character projection lithography is one of promising projection methods for manufacturing application specific integrated circuits at a low cost. From the viewpoint of ASIC design, the number of EB shots, which reflects the manufacturing cost for ASICs, is reduced by (i) cell library generation and (ii) technology mapping. Cell library generation consists of two parts: cell selection and character sizing. We presented a cell selection method (Sugihara et al., 2005(Sugihara et al., , 2006a and character sizing methods (Sugihara et al., 2006c(Sugihara et al., , 2007b. Cell selection and character sizing achieved 72.0% reduction of EB shots with a feasible EB size in the best, comparing with the conventional and intuitional character sizing. We also presented a technology mapping technique for reducing the number of EB shots in character projection lithography. Our technology mapping technique for the CP lithography has achieved a 54.6% less number of EB shots with 8.4% area increase under no timing constraints than the conventional one. Our technology mapping for the CP lithography has also achieved a 26.6% less number of EB shots with 41.1% area increase and without any performance degradation than the conventional one. Our experiments suggested that there exists a tradeoff between area and the number of EB shots.